KR20010063502A - Method for fabricating flash memory device - Google Patents
Method for fabricating flash memory device Download PDFInfo
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- KR20010063502A KR20010063502A KR1019990060589A KR19990060589A KR20010063502A KR 20010063502 A KR20010063502 A KR 20010063502A KR 1019990060589 A KR1019990060589 A KR 1019990060589A KR 19990060589 A KR19990060589 A KR 19990060589A KR 20010063502 A KR20010063502 A KR 20010063502A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 229920000642 polymer Polymers 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- UAJUXJSXCLUTNU-UHFFFAOYSA-N pranlukast Chemical compound C=1C=C(OCCCCC=2C=CC=CC=2)C=CC=1C(=O)NC(C=1)=CC=C(C(C=2)=O)C=1OC=2C=1N=NNN=1 UAJUXJSXCLUTNU-UHFFFAOYSA-N 0.000 abstract description 17
- 229960004583 pranlukast Drugs 0.000 abstract description 17
- 238000004140 cleaning Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 메모리 소자 제조방법에 관한 것으로, 특히 플로팅 게이트(Floating gate)와 유전막(inter dielectric material) 및 컨트롤게이트(Control gate)가 차례로 적층된 스택(stack) 게이트를 갖는 플래쉬 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a flash memory device having a stack gate in which a floating gate, an inter dielectric material, and a control gate are sequentially stacked. It is about.
도1은 통상적인 플래쉬 메모리 소자의 스택 게이트 구조를 보여주는 것으로, 플래쉬 메모리 소자의 스택 게이트는 실리콘 기판(11) 상에 터널 산화막(tunnel oxide)(12), 플로팅 게이트 전도막(13), ONO 유전막(14) 및 컨트롤 게이트 전도막(15)이 차례로 적층되는 구조를 갖는다. 여기서 ONO 유전막(14)은 산화막(14c)/질화막(14b)/산화막(14a)이 차례로 적층된 층이다.1 shows a stack gate structure of a conventional flash memory device, in which a stack gate of a flash memory device is formed on a silicon substrate 11 with a tunnel oxide 12, a floating gate conductive film 13, and an ONO dielectric film. 14 and the control gate conductive film 15 are sequentially stacked. The ONO dielectric film 14 is a layer in which an oxide film 14c, a nitride film 14b, and an oxide film 14a are sequentially stacked.
이러한 구조를 갖는 플래쉬 메모리 소자의 스택게이트를 제조하기 위한 종래 방법을 살펴본다.A conventional method for manufacturing a stack gate of a flash memory device having such a structure will be described.
먼저, 터널 산화막(12)이 형성된 기판 상에 예컨대 폴리실리콘막과 같은 플로팅 게이트 전도막(13)과 ONO 유전막(14)을 증착한 다음, ONO 마스크 및 식각공정을 실시한다. 이어서, 컨트롤 게이트 전도막(15)을 증착하고, 게이트 마스크 및 식각 공정을 실시하게 된다.First, a floating gate conductive film 13 such as a polysilicon film and an ONO dielectric film 14 are deposited on a substrate on which the tunnel oxide film 12 is formed, and then an ONO mask and an etching process are performed. Subsequently, the control gate conductive layer 15 is deposited, and a gate mask and an etching process are performed.
ONO 유전막 식각 공정은 도2에 도시된 바와 같이, 셀 지역이 아닌 주변회로 지역에서, 포토레지스트(16)로 마스킹을 하고 저전압 트랜지스터 또는 고전압 트랜지스터와 같은 특정 트랜지스터의 ONO 유전막(14)을 식각하는 공정을 수행한다. 이때 하부층(underlayer)인 플로팅 게이트 전도막(13)의 폴리실리콘막이 손상 받지 않도록 선택적으로 식각함이 필요하다.In the ONO dielectric film etching process, as shown in FIG. 2, the photoresist 16 is masked in the peripheral circuit area, not in the cell area, and the ONO dielectric film 14 of a specific transistor such as a low voltage transistor or a high voltage transistor is etched. Do this. In this case, it is necessary to selectively etch the polysilicon film of the floating gate conductive film 13 which is an underlayer so as not to be damaged.
그리고, 산화막 건식 식각 장비에서 ONO 유전막(13)을 식각하고 O2플라즈마에 의해 포토레지스트를 스트립(strip)한 다음, 황산 세정(cleaning)을 실시하게되는데, 이때 도3에 도시된 바와 같이 폴리머(polymer) 잔유물(residue)이 완전히 제거되지 않는 점과 폴리실리콘막(즉, 플로팅 게이트 전도막)에 대한 높은 선택비를 얻기가 어려다는 단점을 갖게 된다.In addition, the ONO dielectric layer 13 is etched in the oxide dry etching equipment, the photoresist is stripped by O 2 plasma, and sulfuric acid cleaning is performed. polymer residues are not completely removed and high selectivity to the polysilicon film (i.e., floating gate conductive film) is difficult to obtain.
한편, 폴리머 잔유물을 제거하기 위해서는 포토레지스트 스트립 후 황산에 의한 세정이 아닌 BOE(buffered oxide etchant)에 의한 세정이 필요하지만, 이 경우 셀영역내에 존재하는 게이트의 상부 산화막(14c)이 손상 받으므로 공정 적용이 불가능하다.On the other hand, in order to remove the polymer residue, it is necessary to clean by BOE (buffered oxide etchant) instead of sulfuric acid after the photoresist strip, but in this case, the upper oxide film 14c of the gate existing in the cell region is damaged. It is not applicable.
따라서, 도4에 도시된 바와 같이 ONO 유전막(14) 위에 버퍼층(buffer layer)인 커버(cover) 폴리실리콘층(17)을 증착하고 ONO 유전막(14) 식각 공정에서 폴리실리콘층(17)과 ONO 유전막(14)을 연이어 식각한 다음, BOE 세정을 실시하고 있다. 즉, ONO 유전막(14)을 폴리실리콘층(17)이 덮고 있으므로 BOE에 의해 셀영역 내의 ONO 유전막중 상부 산화막(14c)이 손상을 받지 않는다.Therefore, as shown in FIG. 4, a cover polysilicon layer 17, which is a buffer layer, is deposited on the ONO dielectric layer 14, and the polysilicon layer 17 and ONO are etched in the ONO dielectric layer 14 etching process. The dielectric film 14 is subsequently etched, and then BOE cleaning is performed. That is, since the polysilicon layer 17 covers the ONO dielectric film 14, the upper oxide film 14c in the ONO dielectric film in the cell region is not damaged by the BOE.
그러나, 식각 공정에서 폴리실리콘(17) 식각 장비와 산화막(14c) 식각 장비, 즉 두 대의 장비를 사용해야 하는 단점이 있으며, 앞서 언급한 것 처럼 식각공정에 있어서 피식각층의 자체의 두께가 얇기 때문에 선택적 식각이 힘들다.However, in the etching process, there is a disadvantage of using two devices, namely, polysilicon 17 etching equipment and oxide film 14c etching equipment, and as described above, the etching target layer has a small thickness in the etching process. Etching is difficult
본 발명은 플래쉬 메모리 소자의 스택 게이트를 제조함에 있어, 포토레지스트 스트립 후, 황산 세정이 아닌 BOE 세정을 실시하여 폴리머 문제를 해결하면서 이와 동시에 BOE 세정시 발생될 수 있는 셀 영역 내의 유전막(플로팅게이트와 컨트롤 게이트 사이에 개재된 유전막)이 손상 받는 것을 방지하여, 공정 단순화 및 소자 특성 저하를 방지할 수 있는 플래쉬 메모리 소자의 스택 게이트 제조방법을 제공하는데 그 목적이 있다.According to the present invention, in manufacturing a stack gate of a flash memory device, after a photoresist strip, BOE cleaning is performed instead of sulfuric acid cleaning to solve a polymer problem and at the same time, a dielectric film (floating gate and It is an object of the present invention to provide a method of manufacturing a stack gate of a flash memory device, which can prevent the dielectric film interposed between the control gates from being damaged, thereby preventing process simplification and deterioration of device characteristics.
도1, 도2, 도3 및 도4는 종래기술에 따른 플래쉬 메모리 소자의 스택 게이트 구조를 보여주는 도면.1, 2, 3 and 4 show a stack gate structure of a flash memory device according to the prior art.
도5a 및 도5b는 본 발명에 따른 플래쉬 메모리 소자의 스택 게이트 구조를 보여주는 단면도.5A and 5B are cross-sectional views showing a stack gate structure of a flash memory device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
101 : 반도체 기판 102 : 터널 산화막101 semiconductor substrate 102 tunnel oxide film
103 : 플로팅 게이트 전도막 104 : ONON 유전막103: floating gate conductive film 104: ONON dielectric film
105 : 컨트롤 게이트 전도막 106 : 포토레지스트105: control gate conductive film 106: photoresist
상기 목적을 달성하기 위한 본 발명의 플래쉬 메모리 소자의 스택 게이트 제조방법은, 반도체기판 상에 터널산화막 및 플로팅 게이트 전도막을 차례로 적층 형성하는 단계; 상기 플로팅 게이트 전도막 상에 하부로부터 차례로 제1산화막, 제1질화막, 제2산화막 및 제2질화막이 적층된 유전막을 형성하는 단계; 포토레지스트 패턴으로 마스킹하고 주변회로 영역 내의 일부 상기 유전막을 식각하는 단계; 상기 포토레지스트를 스트립하고 폴리머를 제거하기 위하여 BOE 용액에서 세정을 실시하는 단계; 컨트롤 게이트 전도막을 형성하는 단계; 및 마스크 및 식각 공정으로 상기 반도체기판 상에 적층된 층들을 패터닝하는 단계를 포함하여 이루어짐을 특징으로 한다.The stack gate manufacturing method of the flash memory device of the present invention for achieving the above object comprises the steps of sequentially forming a tunnel oxide film and a floating gate conductive film on a semiconductor substrate; Forming a dielectric film in which a first oxide film, a first nitride film, a second oxide film, and a second nitride film are sequentially stacked on the floating gate conductive film from the bottom; Masking with a photoresist pattern and etching a portion of the dielectric film in the peripheral circuit area; Stripping the photoresist and performing a wash in a BOE solution to remove polymer; Forming a control gate conductive film; And patterning the layers stacked on the semiconductor substrate by a mask and an etching process.
이와 같이, 본 발명은 플래쉬 메모리 소자의 스택 게이트를 제조함에 있어서 플로팅 게이트와 컨트롤 게이트 사이의 유전막을 제1산화막, 제1질화막, 제2산화막 및 제2질화막이 차례로 적층된 ONON 유전막으로 적용하며, 유전막 식각후의 포토레지스트 스트립 후 황산 세정이 아닌 BOE 세정을 실시하여, 폴리머 문제를 해결하면서 이와 동시에 BOE 세정시 발생될 수 있는 셀 영역 내의 유전막이 손상 받는 것을 방지함과 동시에 유전막 식각을 하나의 식각장비에 실시할 수 있도록 하였다.As described above, the present invention applies a dielectric film between a floating gate and a control gate as an ONON dielectric film in which a first oxide film, a first nitride film, a second oxide film, and a second nitride film are sequentially stacked in manufacturing a stack gate of a flash memory device. BOE cleaning, not sulfuric acid cleaning, after the photoresist strip after dielectric film etching, solves the polymer problem and at the same time prevents the dielectric film in the cell region that may be generated during BOE cleaning and damages the dielectric film. To be carried out.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도5a 및 도5b는 본 발명의 일실시예에 따른 스택 게이트 제조 방법을 보여준다.5A and 5B show a stack gate manufacturing method according to an embodiment of the present invention.
먼저, 도5a를 참조하면 반도체 기판(101) 상에 터널산화막(102), 예컨대 폴리실리콘막과 같은 플로팅 게이트 전도막(103) 및 질화막(104d)/산화막(104c)/질화막(104b)/산화막(104a)이 적층된 ONON 유전막(104)을 형성한다.First, referring to FIG. 5A, a floating gate conductive film 103 such as a tunnel oxide film 102, for example, a polysilicon film, and a nitride film 104d / oxide 104c / nitride film 104b / oxide film on a semiconductor substrate 101, for example. An ONON dielectric film 104 in which 104a is stacked is formed.
이어서, 주변회로 영역의 저전압 트랜지스터 또는 고전압 트랜지스터와 같은 특정 트랜지스터의 일부 ONON 유전막(104)을 식각하기 위하여 ONON 유전막(104) 상에 포토레지스트(106) 패턴을 형성한다.A photoresist 106 pattern is then formed on the ONON dielectric film 104 to etch some ONON dielectric film 104 of a particular transistor, such as a low voltage transistor or a high voltage transistor in the peripheral circuit region.
셀 영역 내의 ONON 유전막(104)은 포토레지스트에 의해 완전히 덮혀 있고 주변회로 영역의 ONON 유전막(104) 일부만이 노출되어 있다.The ONON dielectric film 104 in the cell region is completely covered by the photoresist and only a portion of the ONON dielectric film 104 in the peripheral circuit region is exposed.
이어서, 일부 주변회로 영역의 ONON 유전막(104)을 식각하고 O2플라즈마에 의해 포토레지스트(106)를 스트립(strip)한 다음, 폴리머를 제거하기 위하여 BOE 용액에서 세정을 실시한다.Subsequently, the ONON dielectric film 104 in some peripheral circuit areas is etched and the photoresist 106 is stripped by O 2 plasma and then cleaned in a BOE solution to remove the polymer.
여기서, ONON 유전막(104)의 최상부층은 BOE 용액에서 식각선택비가 매우 높은 질화막(104d)이므로, 종래와 같이 별도의 버퍼 폴리실리콘층을 사용하지 않더러도 셀 영역의 ONON 유전막(104)의 손상을 방지 할 수 있다.Here, since the top layer of the ONON dielectric film 104 is a nitride film 104d having a very high etching selectivity in the BOE solution, the ONON dielectric film 104 in the cell region is damaged even without a separate buffer polysilicon layer as in the prior art. Can be prevented.
그리고 BOE 세정을 이용하므로 황산 세정을 실시하였던 종래보다 폴리머 제거 효율을 높일 수 있다. 또한, 산화막과 질화막은 하나의 산화막 건식 식각 장비에서 식각 공정을 진행 할 수 있기 때문에 종래처럼 두대의 식각 장비를 사용하지 않아도 된다는 잇점이 있다.In addition, since the BOE cleaning is used, the polymer removal efficiency can be improved compared with the conventional sulfuric acid cleaning. In addition, since the oxide film and the nitride film may proceed with the etching process in one oxide dry etching equipment, there is an advantage that does not need to use two etching equipment as conventional.
도5b는 컨트롤 게이트 전도막(105)을 증착하고, 게이트 마스크 및 식각 공정을 실시하여 셀 영역내에서 스택 게이트 패턴이 완성된 상태를 보여준다. 통상 컨트롤 게이트 전도막(105)은 폴리실리콘막 및 실리사이드막이 적층된 폴리사이드 구조로 형성된다.5B illustrates a state in which a stack gate pattern is completed in a cell region by depositing a control gate conductive layer 105 and performing a gate mask and an etching process. Typically, the control gate conductive film 105 is formed of a polyside structure in which a polysilicon film and a silicide film are stacked.
이상에서 설명한 바와 같이, 본 발명은 ONO 대신 ONON막을 사용하므로 커패시터 용량이 감소하는 단점이 있지만, 최상부층 질화막(14d)의 용도가 BOE에 대한 보호막으로서 BOE에서 질화막에 대한 선택비가 매우 높으므로 최상부층 질화막(104d) 두께는 최소화하여 커패시터 용량의 증가를 최소화 할 수 있다.As described above, the present invention has a disadvantage in that the capacitor capacity is reduced because the ONON film is used instead of ONO. However, since the use of the top layer nitride film 14d is a protective film for the BOE, the selectivity for the nitride film in the BOE is very high, the top layer The thickness of the nitride film 104d may be minimized to minimize an increase in the capacitor capacity.
또한 DRAM과 달리 플래쉬 소자에서 커패시터의 용량은 그리 중요한 문제가 아니며 약간의 용량의 증가는 터널 산화막의 두께, 게이트 폭(Gate width), 액티브 폭(Active width) 등을 조절함으로써 보완이 가능하다.In addition, unlike DRAM, the capacitance of a capacitor in a flash device is not a significant problem, and a slight increase in capacitance can be compensated by adjusting the thickness of the tunnel oxide, the gate width, and the active width.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 공정 단순화 및 소자 특성 저하를 방지하는 효과가 있다.The present invention has the effect of preventing the process simplification and deterioration of device characteristics.
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| KR1019990060589A KR20010063502A (en) | 1999-12-22 | 1999-12-22 | Method for fabricating flash memory device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100466190B1 (en) * | 2002-06-29 | 2005-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
| KR100489519B1 (en) * | 2002-09-07 | 2005-05-16 | 동부아남반도체 주식회사 | Method for manufacturing control gate etch in semiconductor device |
| KR100661232B1 (en) * | 2004-12-31 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Method for removing the ONO residue in flash device |
| KR100870321B1 (en) * | 2006-09-29 | 2008-11-25 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
-
1999
- 1999-12-22 KR KR1019990060589A patent/KR20010063502A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100466190B1 (en) * | 2002-06-29 | 2005-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
| KR100489519B1 (en) * | 2002-09-07 | 2005-05-16 | 동부아남반도체 주식회사 | Method for manufacturing control gate etch in semiconductor device |
| KR100661232B1 (en) * | 2004-12-31 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Method for removing the ONO residue in flash device |
| KR100870321B1 (en) * | 2006-09-29 | 2008-11-25 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
| US7544567B2 (en) | 2006-09-29 | 2009-06-09 | Hynix Semiconductor Inc. | Method of manufacturing a flash memory device |
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