KR20030023334A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to reduce the size the PMOS transistor of the precharge-equalizer block by re-using the MOS transistor of the driver block as a precharge device at the read/write operation through the read/write operation control block, thereby realizing the memory operable at a high speed. CONSTITUTION: A semiconductor memory device includes a data transferring block(100) for transmitting the external data during the write operation, a driver block(200) for transmitting the data to the data line during the write operation, a read/write operation control block(300) for controlling the function of the write driver during the write operation by controlling the driver block(200) with receiving the data from the data transferring block(100) and to implement the precharge after the read operation, a precharge-equalizer block(400) and a data sense amplifying block(500) for sensing the voltage difference between the data lines during the read operation.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, a semiconductor capable of reducing the size of a MOS transistor of a pracharge means by recycling elements of a write driver part during precharge during a read / write operation. Relates to a memory device.

FIG. 1 illustrates a write driver of a conventional semiconductor memory device. The driver 10 inputs a first signal a and a second signal b to a gate terminal, and a power supply voltage VDD to a source terminal. This commonly applied pull-up first and second PMOS transistors P1 and P2, an inverted signal by the inverter IV1 of the first signal a, and an inverter IV2 of the second signal b. Is a pull-down signal for outputting data to the data line (SDB) (/ SDB) while the inverted signal is inputted to the gate terminal and commonly connected to the drain terminal of the first and second PMOS transistors P1 and P2. It consists of a 1st, 2nd NMOS transistor (N1) (N2).

In the driver unit 10, for example, when the first signal a is at the 'high' level and the second signal b is at the 'low' level, the driver P10 and the second NMOS transistor may be used. The N2 is turned on to serve as a driver, but in other cases, that is, in a floating state during a read operation or a non-operation, the first and second NMOS and PMOS transistors N1 and N2 (N2). None of P1 and P2 are driven.

This only serves as the loading of the data line SDB (/ SDB) when the first and second PMOS transistors P1 and P2 of the driver unit 10 are viewed in the read operation. Although not made, only the PMOS transistors constituting the precharge and equalization parts are used. Therefore, in order to guarantee the precharge of the complete data line SDB (/ SDB), the size of the PMOS transistors constituting the precharge and equalization parts must be appropriately large.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of recycling elements of a write driver part to precharge means during a read operation and serving as a driver during a write operation. will be.

1 is a circuit diagram of a conventional semiconductor memory device.

2 is a circuit diagram of a semiconductor memory device of the present invention.

Explanation of symbols on the main parts of the drawings

100: data transfer unit 110: latch means

120: data transfer means 200: driver unit

300: lead / light operation control unit 400: precharge-equalization unit

500: data sense amplification unit

The semiconductor memory device of the present invention for achieving the above object includes a data transfer unit for transferring external data during a write operation, a driver unit for transferring data to a data line during the write operation, and data from the data transfer unit. A read / write operation control unit which controls the driver unit to receive the light driver during the write operation, and performs a precharge role after the read operation while receiving the read unit; And an equalization unit and a data sense amplifier configured to sense a voltage difference between the data lines during the read operation.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2 is a circuit diagram illustrating an embodiment of a semiconductor memory device of the present invention, and FIG. 3 is a circuit diagram illustrating another embodiment of the present invention.

As shown in FIG. 2, the semiconductor memory device of the present invention includes a data transfer unit 100 for transferring external data during a write operation, and data to the data line SDB (/ SDB) during the write operation. The driver unit 200 to transmit and control the driver unit 200 while receiving data from the data transfer unit 100 serves as a write driver during a write operation, and after a read operation, the pre-cha And a read / write operation control unit 300 for controlling to perform a precharge role. In addition, a precharge-equalization unit 400 and a data sense amplifier 500 for sensing a voltage difference of a data line during a read operation are included.

Here, the data transfer unit 100 includes a latch unit 110 for latching data, and a data transfer unit 120 for transferring the latched data to the read / write operation control unit 300 during a write operation. It includes.

The latch unit 110 is configured by two inverters 111 and 112 fed back, and the data transfer unit 120 receives a write command signal (WBEN) and a write enable signal (WTEN) per bit. From the first NAND gate ND1, the first inverter IV1 for inverting the signal received therefrom, the second inverter IV2 directly connected to the first inverter IV1, and the latch means 110. A third inverter IV3 for inverting a signal of the second inverter; a second NAND gate ND2 for receiving a signal from the latching means 110 and a signal inverted by the first inverter IV1; And a third NAND gate ND3 for receiving signals from IV1) and third inverter IV3.

Also, the read / write operation control unit 300 receives a signal from the first NAND gate ND1 and a fourth NAND gate that receives an enable signal (hereinafter, referred to as / SDBEN) of the precharge-equalization unit 400. ND4, the fifth NAND gate ND5 for receiving signals from the fourth NAND gate ND4 and the second NAND gate ND2, the fourth NAND gate ND4 and the third NAND gate ND3. The sixth NAND gate ND6 that receives a signal from the first NAND gate, the first NOR gate NR1 that receives the signals from the fifth NAND gate ND5, and the second inverter IV2, and the sixth NAND gate ND6. ) And a second NOR gate NR2 that receives a signal from the second inverter IV2.

In addition, the driver unit 200 inputs signals from the fifth NAND gate ND5 and the sixth NAND gate ND6 to the gate terminal, respectively, and a pull-up first in which a power supply voltage VDD is commonly applied to the source terminal. And the signals of the second PMOS transistor P1 and P2, the first and second NOR gates NR1 and NR2 are respectively input to the gate terminal, and the first and second PMOS transistors P1 and P2 are respectively input. And first and second NMOS transistors N1 and N2 for pull-down which output data to the data line SDB (/ SDB) while being connected to the drain terminal of the same.

The precharge-equalization unit 400 is composed of three PMOS transistors (not shown) as is known, and the data sense amplifier unit 500 is also known. Description of the configuration and operation thereof will be omitted.

Reference numeral 402 denotes an inverter for inverting the / SDBEN signal to enable the precharge-equalization unit 400.

Hereinafter, the operation of the semiconductor memory device having the above configuration will be described.

First, when the data is 'high' level during the write operation, when the data is latched by the latch means 110, the write data valid through the inverter 112 and the third inverter IV3 of the data transfer means 120 are valid. The WBEN and WTEN signals maintain the 'high' level during the write operation and the / SDBEN signal sets the 'low' level so that the data during the write operation can be loaded on the data line (SDB) (/ SDB). Keep it. Under these conditions, the 'high' level is output from the fourth NAND gate ND4 of the read / write operation control unit 300 and the write data latched through the second and third NAND gates ND2 and ND3 may pass. The way is provided. Since the output of the first inverter IV1 is at the 'high' level and the output of the second inverter IV2 is at the 'low' level, the latched data drives the driver 200 to drive the data line SDB (/ SDB). ) Will contain valid data.

Then, when the write operation is completed, the WBEN, WTEN, and / SDBEN signals maintain the 'low', 'low', and 'high' levels, respectively. This condition is applied to the data line SDB (/ SDB) through the read / write operation control unit 300 and the first and second PMOS transistors P1 and P2 for the pull-up of the driver unit 200 and the precharge equalizer. Praise and equalize by the rise unit 400.

Next, when a read operation is performed in the precharge and equalized states, the WTEN and WBEN signals are maintained at a 'low' level so that the output of the second inverter IV2 is at a 'high' level. The outputs of the first and second NOR gates NR1 and NR2 become 'low' levels to turn off the first and second NMOS transistors N1 and N2 for pull-down. Meanwhile, when the read data is to be sensed, the / SDBEN signal becomes 'low' level, and the precharge-equalize unit 400 is turned off to release the precharge and equalize. At the same time, the read data is sensed to read the data.

Then, when the read operation is completed, the / SDBEN signal becomes 'high' level as in the write operation, and the first and second PMOS transistors P1 and P2 for pull-up of the driver unit 200 and precharge-equal equalization. The rise line 400 precharges and equalizes the data line.

Unlike the related art, the operation of the semiconductor memory device of the present invention described above allows the MOS transistor of the driver unit 200 to be recycled to the precharge device in the read / write operation through the read / write operation control unit 300. It is possible to reduce the size of the PMOS transistors of the precharge-equalization unit 400.

In addition, the above-described embodiment describes the case where the precharge level is set to the VDD level during the read / write operation, and the read / write operation control unit and the driver unit are modified according to the precharge level as the VSS level. The same operation can be performed without departing from the gist of the present invention.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

According to the semiconductor memory device of the present invention described above, the MOS transistor of the driver unit 200 is recycled to the precharge element in the read / write operation through the read / write operation control unit 300 so as to precharge-equal-equalize. It is possible to reduce the size of the PMOS transistors of the rise unit 400.

As a result, the loading of the data line SDB (/ SDB) can be reduced, and a memory capable of high-speed operation can be implemented.

Claims (5)

In a semiconductor memory device, A data transfer unit for transferring external data during a write operation; A driver unit transferring data to a data line during the write operation; A read / write operation for controlling the driver to receive data from the data transfer unit to serve as a write driver during the write operation, and to perform a precharge role after the read operation; With the control unit, Precharged equalizing part, And a data sense amplifier configured to sense a voltage difference of a data line during the read operation. The method of claim 1, The data transfer unit comprises latch means for latching the data; And data transfer means for transferring the latched data to the read / write operation control unit during the write operation. The method of claim 2, The data transfer means includes: a first NAND gate configured to receive a write command signal and a write enable signal per bit; A first inverter for inverting the signal received from the first NAND gate; A second inverter directly connected to the first inverter, A third inverter for inverting the signal from the latch means; A second NAND gate receiving a signal from the latch means and a signal inverted by the first inverter, And a third NAND gate configured to receive signals from the first inverter and the third inverter. The method of claim 3, wherein The read / write operation control unit comprises a fourth NAND gate receiving a signal from the first NAND gate and an enable signal of the precharge-equalization unit; A fifth NAND gate that receives signals from the fourth NAND gate and the second NAND gate; A sixth NAND gate configured to receive signals from the fourth NAND gate and the third NAND gate; A first noble gate that receives signals from the fifth NAND gate and the second inverter, And a second NOR gate configured to receive signals from the sixth NAND gate and the second inverter. The method of claim 4, wherein The driver unit inputs signals from the fifth and sixth NAND gates to the gate terminal, respectively, and pull-up first and second PMOS transistors to which a power supply voltage is commonly applied to the source terminal; First and second pull-down signals for inputting signals of the first and second noah gates to the gate terminals, respectively, and commonly connecting the drain signals of the first and second PMOS transistors to output data to the data lines; A semiconductor memory device comprising two NMOS transistors.