KR100373350B1 - Low power embedded sram - Google Patents

Abstract

The present invention prevents the precharging and equalizing operation of the bit line in the write operation, prevents the driving of the sense amplifier which is unnecessary during the write operation, and also prevents the input terminal of the sense amplifier bit during the bit line precharge operation in the read operation period. It is an object of the present invention to provide a built-in SRAM for suppressing the occurrence of glitches in the sense amplifier output by preventing the line from being affected. The present invention provides an equalization and precharge for equalizing and precharging a pair of bit lines. A circuit section, a first control circuit section for disabling the equalization and precharge circuit sections during a write operation in response to a clock and write enable signal, a column selector for selecting a bit line by a column select signal, and a column selector Sensing to sense and amplify the signal on the bitline A switching element for switching-connecting an amplifier, the bit line and the sense amplifier input terminal, and disabling the sense amplifier during a write operation in response to a clock and write enable signal and the sense during bit line precharge during a read operation. And a second control circuit unit for disabling the amplifier and the switching element, and a data input driver for transferring the input data to the bit line during the write driving in response to the write enable signal.

Description

LOW POWER EMBEDDED SRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to an embedded static random access memory (SRAM) for storing data in a system integrated circuit (IC).

Recently, high-performance microprocessors or communication systems have emerged, and the scale of such systems has increased day by day, diversifying the functions of the system and making efforts to manufacture existing systems and memory devices on the same chip for processing large amounts of data. It is becoming. This is because when the memory device is implemented on the same chip, the operation speed and the power consumption can be satisfied at the same time. In addition, as process technology advances, the chip density increases and the memory size increases, requiring a low power memory.

1 schematically shows a SRAM configuration according to the prior art, and shows some configurations of a memory cell and its peripheral circuits.

Referring to FIG. 1, a conventional SRAM includes a memory cell 10 connected to a word line and a pair of bit lines to store data, and a bit line to bit data. Equalize and precharge circuit unit 20 for equalizing and precharging and column selector for selecting bit lines (bit, / bit) by column select signal (COLUMN). and a sense-amplifier 40 and a data input driver 50 for sensing and amplifying a signal of a bit line (bit, / bit) transmitted through the column selector.

In detail, the equalization and precharge circuit unit 20 includes an NMOS transistor N1 having a source-drain path connected between the power supply terminal VDD and the positive bit line, and receiving a clock CLK to the gate terminal. ), The NMOS transistor N2 receiving the clock CLK to the gate terminal and the source-drain path connected between the power supply terminal VDD and the sub-bit line (/ bit), and a bit line (bit). And a PMOS transistor (P1) connected between the source and the drain paths and the bit line (/ bit) and receiving an inverted signal of the clock (CLK) through the inverter (I1) as a gate terminal. Precharges the positive and negative bit lines (bit, / bit) while the clock (CLK) has a logic 'high' level through the MOS transistors N1 and N2, and the clock (CLK) by the PMOS transistor P1. Equalizes the positive and sub bit lines (bit, / bit) while having this 'high' level.

In addition, the sense amplifier 40 may include the NMOS transistors N3 and N4 for receiving the positive bit line signal and the sub bit line signal selected by the column selector 30, and the PMOS transistor P2 constituting the current mirror. And a source-drain path connected between the ground power supply terminal and the NMOS transistors N3 and N4, and an inverted transistor N5 receiving an inverted signal of the clock CLK by the inverter I2 to the gate terminal. It consists of. Accordingly, the sense amplifier 40 is enabled while the clock has a 'low' level to sense and amplify signals of positive and negative bit lines (bit, / bit) to output data (DOUT).

The data input driver 50 is controlled by the write enable signal WE, which is a high active signal, and transmits the input data DIN to the memory cell 10.

A conventional SRAM operation configured as described above will be described.

The write mode is performed when the write enable signal WE is activated 'high', and the input data DIN is transferred to the bit line by the data input driver 50 and then stored in the cell 10. At this time, the bit line is first precharged and equalized in the section where the clock CLK is 'high' level, and then the input data DIN is stored in the cell in the section where the clock CLK is 'low'.

The read mode is performed when the write enable signal WE is deactivated to 'low'. The data stored in the cell 10 is transferred to the sense amplifier 40 through the bit line and then amplified to output data DOUT. Are exported to). In this case, the bit line is precharged and equalized in the section where the clock CLK is at the 'high' level, and then the sense amplifier is enabled when the clock is at the 'low' level to output data.

However, the SRAM configured as described above has two problems in terms of power consumption.

First, during the write operation, the precharge is continuously performed regardless of what voltage is applied to the previous positive bit line and the sub bit line. Therefore, the voltage changes every cycle, which causes unnecessary power consumption. .

Secondly, during the precharge during the read operation, the voltages of the positive bit line and the sub bit line change to the precharge voltage, and glitches are generated at the output of the sense amplifier as shown in FIG. Cause power consumption.

Thirdly, the sense amplifier operates unnecessarily during the write operation, which also brings power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide an embedded SRAM which reduces power consumption by preventing precharge and equalization of bit lines in a write operation.

Another object of the present invention is to provide a built-in SRAM for preventing the driving of a sense amplifier that is unnecessary during a write operation.

It is still another object of the present invention to provide an embedded SRAM for suppressing the generation of glitches in the sense amplifier output by preventing the input terminal of the sense amplifier from being affected by the bit line during the bit line precharge operation in the read operation period.

1 is a circuit diagram schematically showing the configuration of an SRAM according to the prior art;

2 is a circuit diagram schematically showing a configuration of an SRAM according to an embodiment of the present invention;

3 is a timing diagram of each control signal and an input / output data signal in FIG. 2;

4 shows simulation results showing the action of the present invention for suppressing glitches.

* Description of the main parts of the drawing

10 memory cell 20 equalization and precharge means

30: column selector 40: sense amplifier

50: data input driver 500: first control circuit

600: second control circuit 700: switching element

pre: precharge control signal

SE: sense enable signal

According to another aspect of the present invention, there is provided an embedded SRAM, including: a positive bit line and a sub bit line connected to a cell; Equalizing and precharging means for equalizing and precharging the positive bit line and the sub bit line; Sensing amplifier means for sensing and amplifying and outputting the signals of the positive bit line and the sub bit line; And control means for disabling the equalization and precharge means during a write operation in response to a clock and write enable signal.

According to another aspect of the present invention, there is provided an embedded SRAM, including: a positive bit line and a sub bit line connected to a cell; Equalizing and precharging means for equalizing and precharging the positive bit line and the sub bit line; Sensing amplifier means for sensing and amplifying and outputting the signals of the positive bit line and the sub bit line; And control means for disabling said sense amplifier means during a write operation in response to a clock and write enable signal.

According to another aspect of the present invention for achieving the above object, the present invention is characterized in that the positive and negative charges are controlled while the equalizing and precharging means are enabled during a read operation under the control of the output of the control means. Switching means for electrically switching between the bit line and the input terminal of the sense amplifier means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 2 schematically illustrates an SRAM configuration according to an embodiment of the present invention, and illustrates a partial configuration of a memory cell and a peripheral circuit thereof.

Referring to FIG. 2, an SRAM according to an embodiment of the present invention is connected to a word line (WORD) and a pair of bit lines (bit, / bit) to store data and a bit line ( Equalize and precharge circuitry 20 for equalizing and precharging the bit and / bit, and the write operation in response to the clock CLK and the write enable signal WE. A first control circuit 500 for disabling the equalization and precharge circuits 20, and a column selector for selecting bit lines (bit, / bit) by the column select signal COLUMN ( 30), a sense-amplifier 40 for sensing and amplifying a signal of a bit line (bit, / bit) transmitted through the column selector, and for switching the bit line and the sense amplifier input terminal The write operation is performed in response to the switching elements 700a and 700b, the clock CLK, and the write enable signal WE. A second control circuit unit 600 for disabling the sense amplifier 40 during operation and disabling the sense amplifier 40 and the switching elements 700a and 700b during bit line precharge during a read operation, and And a data input driver 50 for transferring input data to the bit line during write driving in response to the write enable signal WE.

Specifically, the first control circuit unit 500 inverts and outputs the first inverter I21 for inverting and outputting the write enable signal WE, and the AND gate for outputting the output of the inverter I21 and the clock CLK. The second inverter I22 is configured to invert the output of the AND and the AND gate AND.

The equalization and precharge circuit unit 20 receives a source-drain path connected between a supply power supply terminal VDD and a positive bit line, and receives an output signal pre of the AND gate AND to a gate terminal. The source-drain path is connected between the NMOS transistor N1, the supply power supply terminal VDD, and the sub-bit line (/ bit), and the output signal pre of the AND gate AND is applied to the gate terminal. A source-drain path is connected between the MOS transistor N2 and the positive bit line (bit) and the sub bit line (/ bit), and the PMOS transistor P1 receiving the signal of the second inverter I22 to the gate terminal. It is implemented by).

Due to the configuration of the first control circuit 500 and the equalization and precharge circuit 20, the pair of bit lines (bit, / bit) has a write enable signal WE of a logic level 'low' and a clock CLK. Precharge and equalize only when the logic is 'high'. That is, unlike the related art, when the write enable signal WE is at the logic level 'high' (write operation period), the bit line is not precharged because the control signal pre is deactivated regardless of the clock CLK. Therefore, power consumption can be reduced. In this case, it is preferable that the data input driver 50 transferring the input data DIN to the positive bit line and the sub bit line during the write operation increases the driving force so that the data is sufficiently transmitted to the memory cells.

The second control circuit unit 600 is constituted by a NOR gate NOR that negates and logically combines the clock CLK and the write enable signal WE, and the sense amplifier 40 is maintained by the column selector 30. NMOS transistors N3 and N4 for receiving the signal of the transistor line and the signal of the sub-bit line, PMOS transistors P2 and P3 constituting the current mirror, ground power terminal Vss, and the NMOS transistor N3. A source-drain path is connected between the common source terminals of N4 and an NMOS transistor N5 receives the output signal SE of the NOR gate NOR to the gate terminal.

Due to the configuration of the second control circuit unit 600 and the sense amplifier 40, the sense amplifier 40 is different from the conventional case when the write enable signal WE is at a logic level 'high' (write operation section). The sense amplifier is disabled regardless of the clock CLK. Therefore, the sense amplifier does not operate unnecessarily during the write operation period, thereby reducing power consumption.

In addition, the switching elements 700a and 700b have a source-drain path connected between a positive bit line and a positive input terminal (gate terminal of transistor N3) of the sense amplifier 40, and the NOR gate NOR is connected to a gate terminal. The source-drain path is connected between the NMOS transistor 700a receiving the output signal of the N-th transistor) and the sub-bit line (/ bit) and the sub-input terminal of the sense amplifier 40 (the gate terminal of the transistor N4). The NMOS transistor 700b is configured to receive the output signal of the NOR gate NOR. As a result, the switching elements 700a and 700b have a period in which the write enable signal WE is logic 'low'. Suppresses the occurrence of glitches at the output (DOUT) of the sense amplifier by electrically separating the bit line and the sense amplifier when precharge is applied to the bit line (i.e. during a read operation). Done.

FIG. 3 is a timing diagram of each control signal and an input / output data signal in FIG. 2, and FIG. 4 is a diagram illustrating a simulation result showing the operation of the present invention for suppressing glitches. Shall be.

A control signal during read and write operations will be described with reference to a timing diagram of FIG. The write enable signal WE is a signal for controlling write and read operations of the SRAM. The write enable signal WE is a 'high' active signal for performing a write operation mode at a logic 'high' level.

First, when the write enable signal WE is 'high', that is, during a write operation, the precharge signal pre and the sense amplifier enable signal SE are always at a logic 'low' level regardless of the clock CLK. Eventually, equalization and precharge circuitry 20 and sense amplifier 40 are disabled.

Next, when the write enable signal WE is 'low', that is, during a read operation. It can be seen that the precharge signal pre has the same signal level as the clock CLK and the sense amplifier enable signal SE has the inverted signal phase of the clock CLK. As a result, while the bit line is precharged in the read mode, the sense amplifier is disabled and the input terminal of the sense amplifier is electrically disconnected from the bit line.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can implement a low-power embedded SRAM by preventing the precharge operation and the driving of the sense amplifier generated during the write operation of the SRAM, and preventing the glitch from being generated in the sense amplifier output signal. In particular, when high speed operation and a large number of memory devices are required, such as a microprocessor or a communication chip, cost reduction and performance increase can be obtained.

Claims (9)

In built-in SRAM, A positive bit line and a sub bit line connected to the cell; Equalizing and precharging means for equalizing and precharging the positive bit line and the sub bit line; Sensing amplifier means for sensing and amplifying and outputting the signals of the positive bit line and the sub bit line; And Control means for disabling the equalization and precharge means during a write operation in response to a clock and write enable signal Built-in SRAM, including. The method of claim 1, The control means disables the equalization and precharge means regardless of a clock when the write enable signal is activated, And disabling or enabling the equalizing and precharging means according to the logic state of the clock when the write enable signal is deactivated. The method of claim 2, The control means, A first inverter for inverting and outputting the write enable signal; An AND gate for performing an AND operation on the output of the inverter and the clock signal; And And a second inverter for inverting and outputting the output of the AND gate. The method of claim 3, The equalizing and precharging means, A first NMOS transistor connected between a power supply terminal VDD and a positive bit line, and receiving an output signal of the AND gate to a gate terminal; A second NMOS transistor connected between a source power supply terminal VDD and a sub bit line, and receiving an output signal of the AND gate to a gate terminal; And And a PMOS transistor having a source-drain path connected between the positive bit line and the sub bit line (/ bit) and receiving the output signal of the second inverter as a gate terminal. In built-in SRAM, A positive bit line and a sub bit line connected to the cell; Equalizing and precharging means for equalizing and precharging the positive bit line and the sub bit line; Sensing amplifier means for sensing and amplifying and outputting the signals of the positive bit line and the sub bit line; And Control means for disabling the sense amplifying means during a write operation in response to a clock and write enable signal Built-in SRAM, including. The method of claim 5, And switching means for electrically switching between the positive and sub bit lines and an input terminal of the sense amplifying means while the equalizing and precharging means are enabled under the control of the output of the control means. Built-in SRAM. The method of claim 5, The control means disables the sense amplification means regardless of a clock when the write enable signal is activated, And disabling or enabling the sense amplifying means according to the logic state of the clock when the write enable signal is deactivated. The method of claim 6, The switching means, A first NMOS transistor connected between the positive bit line and the positive input terminal of the sense amplifying means and receiving an output signal of the control means to a gate terminal; And And a second NMOS transistor connected between the sub-bit line and the sub-input terminal of the sense amplifying means and receiving an output signal of the control means to a gate terminal. The method according to any one of claims 5 to 8, The control means, And a NOR gate configured to output a negative logic sum of the clock and the write enable signal.