KR20030021652A - Unit Cell Of Static RAM And Method Of Fabricating The Same - Google Patents

Abstract

PURPOSE: A unit cell of a static random access memory(SRAM) is provided to minimize a three dimension phenomenon by making transistors constituting the unit cell of the SRAM have a rectangular type, and to increase an operation speed by forming the unit cell whose width and length are similar. CONSTITUTION: The first and second active regions(310,320) are disposed in a straight line of a semiconductor substrate, crossing the center of the unit cell and separated from each other. The third and fourth active regions(330,340) are in parallel with the first and second active regions, disposed in the semiconductor substrate at both sides of the first and second active regions, respectively. An isolation layer pattern is disposed in a predetermined region of the semiconductor substrate to define the first, second, third and fourth active regions. The first and second gate electrodes(410,420) cross the first and third active regions and the second and fourth active regions, respectively. A word line(400) of a straight line type passes through a gap between the first and second gate electrodes and crosses the third and fourth active regions.

Description

Unit cell of static ram and method of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a unit cell of SRAM and a method of manufacturing the same.

A unit cell of a typical static RAM has two driver transistors, an access transistor, and a load transistor, respectively, for low standby current value and high data retention capability. load transistor). The unit cell of the SRAM may be further classified into a high resistance load cell, a TFT cell, and a full CMOS cell according to the type of the load transistor.

The full CMOS cell is typically composed of four NMOS transistors constituting the driving transistor and an access transistor and two PMOS transistors constituting the load transistor. Such full CMOS cells are attracting the most attention as unit cell types of SRAM because they have excellent electrical characteristics and simple processes. However, in order to achieve high integration of semiconductor devices that have always been required in the manufacture of semiconductor devices, semiconductor devices having a desired structure must be formed within a minimum area. However, due to the fact that a full CMOS cell type SRAM has to form an NMOS transistor and a PMOS transistor together in a unit cell, it has a disadvantage of occupying a relatively large area compared to the other types of SRAM structures described above.

Several techniques have been proposed to overcome the shortcomings of the full CMOS cells. One of them is a method for manufacturing an SRAM having unit cells having different lengths and widths. However, in this case, there is a problem that the operation speed of the SRAM is slow. Another method for overcoming the shortcomings of the full CMOS cell is a method of manufacturing an SRAM in which the six transistors are formed in a minimum area and at the same time have a similar length and width. However, in this case, in order to make the unit cell occupy the smallest area, a complex shape, for example, a gate electrode is formed in a 'T' shape. However, when the shape of the desired material film pattern is complicated, the material film pattern actually formed by the 3D effect or the proximity effect does not have the desired shape. In particular, when the shape of the gate is not properly formed as described above, seriously affect the electrical characteristics of the semiconductor device. Accordingly, there is a need for a technique of constituting a unit cell of an SRAM having a shape that can avoid the 3D effect and having a similar length and width.

An object of the present invention is to provide a unit cell of the SRAM suitable for high integration and high speed.

Another technical problem to be achieved by the present invention is to provide a method for manufacturing a unit cell of the SRAM suitable for high integration and high speed.

1A to 5A are plan views illustrating the planar structure corresponding to each process step in detail in the method of manufacturing a unit cell of an SRAM according to a preferred embodiment of the present invention.

1B to 5B are process cross-sectional views illustrating respective cross sections according to 1-1 ′ of FIGS. 1A to 5A to explain a method of manufacturing a unit cell of an SRAM according to a preferred embodiment of the present invention.

1C to 5C are process cross-sectional views illustrating respective cross sections according to 2-2 ′ of FIGS. 1A to 5A to explain a method of manufacturing a unit cell of an SRAM according to a preferred embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a unit cell of SRAM having a unit cell having a similar length and width and a straight word line across a central portion of the unit cell. The unit cell of the SRAM includes a first active region and a second active region which are disposed in a straight line on the semiconductor substrate to cross the central portion of the unit cell and are spaced apart from each other. Third and fourth active regions parallel to the first and second active regions are disposed on the semiconductor substrates of both the first and second active regions, respectively. The first, second, third and fourth active regions are defined by a device isolation layer pattern disposed in a predetermined region of the semiconductor substrate. A first gate electrode and a second gate electrode are disposed on the semiconductor substrate to cross the first and third active regions and the second and fourth active regions, respectively. A word line having a straight line is disposed across the third and fourth active regions through the first and second gate electrodes.

Preferably, the first, second, third and fourth active regions have a rectangular shape. In addition, the first and second gate electrodes and the word lines are also preferably rectangular in shape.

In order to achieve the above another technical problem, the present invention provides a method of manufacturing a unit cell of an SRAM having a straight line. The method of manufacturing a unit cell of the SRAM includes forming a device isolation layer pattern defining a first, second, third and fourth active regions on a semiconductor substrate. In this case, the first and second active regions cross the central portion of the unit cell in a straight line, and the third and fourth active regions are formed to be parallel to them on both sides of the first and second active regions, respectively. It features. Thereafter, a gate oxide film is formed on the entire surface of the semiconductor substrate including the device isolation layer pattern, and first and second gate electrodes and word lines are formed. In this case, the first gate electrode is formed to cross the first and third active regions on the gate oxide layer, and the second gate electrode is formed to cross the second and fourth active regions. The word line may be formed to cross the third and fourth active regions.

The forming of the device isolation layer pattern may be performed such that the first, second, third and fourth active regions have a rectangular shape. In addition, the first and second gate electrodes and the word line may also be formed to have a rectangular shape.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

1A to 5A are plan views illustrating the planar structure corresponding to each process step in detail in the method of manufacturing a unit cell of an SRAM according to a preferred embodiment of the present invention. 1B to 5B and 1C to 5C are each 1-1 'and 2-2' of FIGS. 1A to 5A to explain a method of manufacturing a unit cell of an SRAM according to a preferred embodiment of the present invention. Process cross-sections showing the cross section accordingly.

Referring to FIG. 1A, a first active region 310 and a second active region 320 are disposed in a predetermined region on a semiconductor substrate. Each of the first and second active regions 310 and 320 constitutes an active region of a load transistor constituting a unit cell of the SRAM. The first and second active regions 310 and 320 are disposed in a straight line while crossing the center of the unit cell, and they are spaced apart from each other.

The third active region 330 and the fourth active region 340 are disposed on both side surfaces of the first and second active regions 310 and 320, respectively. In this case, each of the third and fourth active regions 330 and 340 is parallel to the first and second active regions 310 and 320 and crosses the unit cell. Each of the third active region 330 or the fourth active region 340 constitutes an active region in which one driving transistor and one access transistor are formed. The driving transistor and the access transistor together with the load transistor constitute a unit cell of the SRAM.

The first, second, third and fourth active regions 310, 320, 330, and 340 are defined by the device isolation region 110. Therefore, the device isolation region 110 is interposed between the first and second active regions 310 and 320.

The first and second active regions 310 and 320 are semiconductor substrates containing N-type impurities, and the third and fourth active regions 330 and 340 are semiconductor substrates containing P-type impurities. In addition, the first, second, third and fourth active regions 310, 320, 330, and 340 are preferably rectangular or close in shape to minimize the 3D phenomenon described in the prior art. By forming the active region having such a rectangular shape, it is possible to minimize the stress of the semiconductor substrate caused in the complex pattern form. In addition, in order to speed up the operation speed of the SRAM, the unit cell is composed of a rectangle having a similar length and length. Preferably, the unit cell has a square shape.

Referring to FIGS. 1B and 1C, trenches defining an active region may be formed by forming trench mask patterns sequentially stacked on the semiconductor substrate 100 and etching the semiconductor substrate 100 using the same as an etching mask. 5) form. The first, second, third and fourth active regions 310, 320, 330, and 340 described with reference to FIG. 1A are determined through the trench 5 formation process. After forming the device isolation layer filling the trench 5, the device isolation layer pattern 110 is formed by planar etching using a conventional method.

An ion implantation process is performed on the semiconductor substrate 100 including the device isolation layer pattern 110 to form first conductive wells 10 and second conductive wells 20 on the semiconductor substrate 100. . The first conductivity type well 10 may be formed under the third active region 330 and the fourth active region 340, and may include P-type impurities. In addition, the second conductivity type well 20 may be formed under the first active region 310 and the second active region 320, and may include N-type impurities. In order to adjust the characteristics of the semiconductor device, a plurality of further ion implantation processes may be further performed in addition to the ion implantation process described above. Thereafter, the gate oxide film 120 is formed on the entire surface of the semiconductor substrate subjected to the ion implantation process.

Referring to FIG. 2A, a first gate electrode 410 is disposed across the first and third active regions 310 and 330, and is formed to cross the second and fourth active regions 320 and 340. Two gate electrodes 420 are disposed. However, the first gate electrode 410 does not cross the fourth active region 340, and the second gate electrode 420 does not cross the third active region 330. In this case, the first and second gate electrodes 410 and 420 may also have a rectangular shape in order to minimize the 3D phenomenon described in the prior art.

The first and second gate electrodes 410 and 420 are respectively between the first active region 310 and the fourth active region 340, and the second active region 320 and the third active region 330. ) Has an area for electrical connection. For stable electrical connection, the area for electrical connection may have a wider width than the gate electrodes 410, 420 at the position passing through the first or second active area 310, 320. Accordingly, the first and second gate electrodes 410 and 420 may have a shape that is deformed from a rectangular shape, which is the preferred case. However, since the region for the electrical connection is formed on the isolation region 110, it is different from the prior art in that it does not significantly affect the electrical characteristics of the semiconductor device. Preferably, the first and second gate electrodes 410 and 420 preferably have symmetrical shapes with respect to the center point of the unit cell. In addition, the third and fourth active regions 330 and 340 may also have symmetrical shapes with respect to the center point of the unit cell.

A rectangular word line 400 intersecting the third and fourth active regions 330 and 340 is disposed between the first and second gate electrodes 410 and 420. The word line 400 serves as a gate electrode of an access transistor formed in each of the third and fourth active regions 330 and 340. In addition, the word line 400 may pass through a spaced portion between the first and second active regions 310 and 320.

As described above, the SRAM includes two driving transistors, an access transistor, and a load transistor, respectively. The access transistor is disposed in the third active region 330 and the fourth active region 340 that cross the word line 400. In more detail, the word line 400 is a gate electrode, and the third and fourth active regions 330 and 340 on the side of the word line 400 are source / drain. In addition, one driving transistor is formed in each of the third active region 330 crossing the first gate electrode 410 and the fourth active region 340 crossing the second gate electrode 420. . In more detail, the driving transistor includes the first and second gate electrodes 410 and 420 as gate electrodes, and the third and fourth active regions 330 on the side surfaces of the first and second gate electrodes 410 and 420. , 340 as a source / drain. One load transistor is formed in each of the first active region 310 crossing the first gate electrode 410 and the second active region 320 crossing the second gate electrode 420. In this case, a portion of the first active region 310 not covered by the first gate electrode 410 and a portion of the second active region 320 not covered by the second gate electrode 420 may be formed. Each of the source and drain regions of the load transistor is formed.

The source / drain regions of the load transistor are regions containing high concentration impurities of a different conductivity type from the first and second active regions 310 and 320. Therefore, preferably, the source / drain regions of the load transistor include a P-type impurity. On the other hand, the source / drain regions of the driving transistor and the access transistor are regions containing high concentration impurities of a different conductivity type from the third and fourth active regions 330 and 340, and preferably include N type impurities. . That is, it is preferable that the load transistor is composed of a PMOS transistor, and the access transistor and the driving transistor are composed of an NMOS transistor.

2B and 2C, a gate electrode 130 is formed on a semiconductor substrate including the gate oxide layer 120. The gate electrode 130 may be a gate conductive layer and a hard mask layer that are sequentially stacked. The gate electrode 130 forms the first and second gate electrodes and word lines 410, 420, and 400 described with reference to FIG. 2A. Using a conventional technique, spacers 150 are formed on sidewalls of the gate electrode 130.

Thereafter, a plurality of ion implantation processes are performed on the semiconductor substrate including the spacer 150 to form the source / drain 15 and 25 in the active region on the side of the gate electrode 130. The ion implantation process is performed such that the source / drain 15 and 25 formed accordingly have a conductivity type different from that of the active region through which each gate electrode 130 passes. That is, the source / drain 15 formed in the first and second active regions 310 and 320 may contain a high concentration of N-type impurities, and may be formed in the third and fourth active regions 330 and 340. The source / drain 25 preferably contains a high concentration of P-type impurities. The source / drains 15 and 25 formed in the respective active regions may use a conventional LDD formation technique to have an LDD structure.

Referring to FIG. 3A, contact wirings 170 are connected to the respective sources / drains of the access transistor, the driving transistor, and the load transistor. In addition, gate contact wirings 171 for connecting to the first and second gate electrodes 410 and 420 are disposed. The gate contact wiring 171 is connected to a region for the electrical connection among the first and second gate electrodes 410 and 420. The contact wirings and the gate contact wirings 170 and 171 are surrounded by a first interlayer insulating layer covering the first and second gate electrodes and the word lines 410, 420, and 400.

3B and 3C, a first interlayer insulating layer 160 is formed on the entire surface of the semiconductor substrate on which the source / drain 15 and 25 are formed. The first interlayer insulating film 160 is preferably a silicon oxide film. The first interlayer insulating layer 160 is patterned to expose a portion of the source / drain 15 and 25 of each transistor and to expose a portion of the upper surface of the first and second gate electrodes 410 and 420. A contact hole is formed. Subsequently, a metal film is formed on the entire surface of the semiconductor substrate including the contact hole and then planarized to be etched to form contact wires 170 connected to the source / drain 15 and 25 and the first and second gate electrodes 410. A gate contact wiring 171 connected to 420 is formed. The contact wirings and the gate contact wirings 170 and 171 may be formed of a metal film containing tungsten.

Referring to FIG. 4A, a local wiring 500 connecting the drain of the load transistor connected to the first gate electrode 410 and the drain of the driving transistor to the second gate electrode 420 is disposed. In addition, another symmetrically arranged local wiring 500 connects the drain of the load transistor and the drain of the driving transistor connected to the second gate electrode 420 to the first gate electrode 410. For this purpose, the local wiring 500 connects the contact wiring 170 connected to the drain of the load transistor and the drain of the driving transistor to the gate contact wiring 171. The source of the driving transistor is connected to the ground wiring 510 by the contact wiring 170. The ground wire 510 is spaced apart from the local wire 500 and passes over the contact wire 170. In addition, the drain of the access transistor and the source of the load transistor are connected to the lower bit line pad 520 and the lower Vcc pad 530 respectively covering the contact wiring 170. The local wiring 500, the ground wiring 510, the lower bit line pad 520, and the lower Vcc pad 530 are preferably metal films including aluminum, with a second interlayer insulating film interposed therebetween. do.

4B and 4C, after the second interlayer insulating layer 180 is formed on the entire surface of the semiconductor substrate including the contact wiring 170, the upper surface of the contact wiring 170 is formed by using a damascene process. A first conductive film pattern 190 is formed to be in contact. The first conductive layer pattern 190 forms the local wiring 500, the ground wiring 510, the lower bit line pad 520, and the lower Vcc pad 530 described with reference to FIG. 4A. The first conductive layer pattern 190 may also be formed by first forming a first conductive layer on the entire surface of the semiconductor substrate including the contact wiring 170 and then patterning the first conductive layer 190. In this case, the first conductive layer pattern 190 is insulated through a subsequent process of forming the second interlayer insulating layer 180.

Referring to FIG. 5A, a Vcc line 710 and two bit lines 700 crossing the word line 400 are disposed. The Vcc line 710 passes over the source / drain top of the load transistor. One bit line 700 is disposed on both sides of the Vcc line 710 to pass over the drain of the access transistor. Preferably, the bit line 700 and the Vcc line 710 have a rectangular shape.

An upper bit line pad 620 is disposed between the bit line 700 and the lower bit line pad 520 to connect the drain of the access transistor to the bit line 700. In addition, an upper Vcc pad 630 is disposed between the Vcc line 710 and the lower Vcc pad 530 to connect the source of the load transistor to the Vcc line 710. Side surfaces of the upper bit line pad 620 and the upper Vcc pad 630 are surrounded by a third interlayer insulating layer, and the bit line 700 and the Vcc line 710 pass over the upper bit line pad 620 and the upper Vcc pad 630.

5B and 5C, after the third interlayer insulating film 200 is formed on the entire surface of the semiconductor substrate including the first conductive film pattern 190, the first conductive layer may be formed in a predetermined region using a Damask process. A second conductive film pattern 210 is formed to be in contact with the film pattern 190. The third interlayer insulating film 200 may connect the second conductive film pattern 210 only to the lower bit line pad 520 and the lower Vcc pad 530 described with reference to FIG. 5A of the first conductive film pattern 190. Is patterned. That is, the second conductive layer pattern 210 forms the upper bit line pad 620 and the upper Vcc pad 630 described with reference to FIG. 5A.

A third conductive film pattern 220 is formed by stacking and patterning a metal film on the entire surface of the semiconductor substrate including the second conductive film pattern 210. The third conductive layer pattern 220 forms the bit line 700 and the Vcc line 710 described with reference to FIG. 5A.

According to the present invention, the transistors constituting the unit cell of the SRAM is configured in a pattern having a rectangular shape. Accordingly, transistors are formed in a desired shape to minimize 3D phenomenon. As a result, the production of highly integrated SRAMs is possible. In addition, by constructing a unit cell having a similar length and width, it is possible to manufacture a fast SRAM.

Claims (15)

In the unit cell of SRAM, A first active region and a second active region disposed in a straight line on a semiconductor substrate to cross a central portion of the unit cell and spaced apart from each other; Third and fourth active regions disposed on semiconductor substrates on both the first and second active regions so as to be parallel to the first and second active regions, respectively; An isolation layer pattern disposed in a predetermined region of the semiconductor substrate to define the first, second, third and fourth active regions; First and second gate electrodes crossing the first and third active regions and the second and fourth active regions, respectively, on the semiconductor substrate; And And a word line having a straight line crossing between the first and second gate electrodes and crossing the third and fourth active regions. The method of claim 1, And the first active region and the second active region through which the first gate electrode and the second gate electrode pass include N-type impurities. The method of claim 1, The first active region and the second active region on the side of the first gate electrode and the second gate electrode, the unit cell of the SRAM, characterized in that containing a high concentration of P-type impurities. The method of claim 1, And the third active region and the fourth active region through which the first gate electrode and the second gate electrode pass include a P-type impurity. The method of claim 1, The third active region and the fourth active region between the first gate electrode, the second gate electrode, and the word line may include a high concentration of N-type impurities. The method of claim 1, Wherein the first, second, third and fourth active regions have a rectangular shape. The method of claim 1, And the first and second gate electrodes and the word line have a rectangular shape. The method of claim 1, The unit cell of the SRAM characterized in that the form of a square. In the manufacture of the unit cell of the SRAM, Defining a first active region and a second active region which cross the central portion of the unit cell in a straight line on the semiconductor substrate, and a third active region and a fourth active region parallel to them on both sides of the first and second active regions, respectively; Forming a device isolation film pattern; Forming a gate oxide film on an entire surface of the semiconductor substrate including the device isolation pattern; And A first gate electrode crossing the first and third active regions, a second gate electrode crossing the second and fourth active regions, and a word line crossing the third and fourth active regions on the gate oxide layer. Unit cell manufacturing method of the SRAM comprising the step of forming a. The method of claim 9, The forming of the device isolation layer pattern may be performed such that the first, second, third and fourth active regions have a quadrangular shape. The method of claim 9, And the first and second gate electrodes and the word line are formed in a rectangular shape. The method of claim 9, After forming the device isolation layer pattern, an ion implantation process for injecting an N-type impurity into the first active region and the second active region further comprising the step of manufacturing a unit cell of SRAM. The method of claim 9, After forming the device isolation layer pattern, an ion implantation process for injecting P-type impurities into the third active region and the fourth active region further comprising the step of manufacturing a unit cell of SRAM. The method of claim 9, After forming the first and second gate electrodes and the word line, an ion implantation process of implanting P-type impurities into the first and second active regions on the side surfaces of the first and second gate electrodes is further performed. The unit cell manufacturing method of the SRAM. The method of claim 9, After forming the first and second gate electrodes and the word line, an ion implantation process of implanting N-type impurities into the third and fourth active regions on the side surfaces of the first and second gate electrodes and the word line is further performed. Unit cell manufacturing method of SRAM characterized in that.