KR20030016855A - Stacked chip scale package - Google Patents

Stacked chip scale package Download PDF

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Publication number
KR20030016855A
KR20030016855A KR1020010050631A KR20010050631A KR20030016855A KR 20030016855 A KR20030016855 A KR 20030016855A KR 1020010050631 A KR1020010050631 A KR 1020010050631A KR 20010050631 A KR20010050631 A KR 20010050631A KR 20030016855 A KR20030016855 A KR 20030016855A
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KR
South Korea
Prior art keywords
chip scale
scale package
package
wire
chip
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KR1020010050631A
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Korean (ko)
Inventor
김신
Original Assignee
삼성전자주식회사
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Priority to KR1020010050631A priority Critical patent/KR20030016855A/en
Publication of KR20030016855A publication Critical patent/KR20030016855A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: A stacked chip scale package is provided to miniaturize a stacked chip scale package by stacking a plurality of chip scale packages. CONSTITUTION: The first and the second metal layers(117,127) and the first and the second slots(112a,122a) are formed on the first and the second tape substrates(112,122), respectively. The first and the second semiconductor chips(111,121) includes the first active surface and the second active surface(121a) having the first and the second bonding pads(113,123) and the first back side and the second back side(121b), respectively. The first and the second protective layers(116,126) are formed on the first and the second metal layers(117,127) in order to expose the first and the second wire fingers(117a,127a), respectively. The first and the second connection portions(114,124) are connected with the first and the second bonding pads(113,123) and the first and the second metal layers(117,127) through the first and the second slots(112a,122a), respectively. The first and the second connection portions(114,124) are sealed with the first and the second sealing portion(118,128), respectively.

Description

적층 칩 스케일 패키지{Stacked chip scale package}Stacked chip scale package

본 발명은 적층 칩 패키지(stacked chip package)에 관한 것으로, 좀더 상세하게는 칩 스케일 패키지(chip scale package 또는 chip size package; CSP)를 적층한 후, 와이어를 이용하여 전기적으로 연결시킴으로써 구비된 적층 칩 스케일 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked chip package, and more particularly, to stack a chip scale package (CSP) or a chip scale package (CSP), and to stack the chip by electrically connecting the same. Relates to a scale package.

최근, 반도체 칩의 집적도가 증가함에 따라, 반도체 칩 패키지는 크기가 소형화되면서 용량은 증가되고 그 기능이 다양화되었다. 이와 같은 추세에 부합되기 위한 반도체 칩 패키지에는 칩 스케일 패키지가 있다. 칩 스케일 패키지는 그 크기가 칩 크기 수준으로 극소화될 수 있으며, 볼 그리드 어레이(Ball Grid Array: BGA) 방식을 도입함으로써 많은 수의 리드가 필요한 반도체 칩에 적용 가능하다.In recent years, as the degree of integration of semiconductor chips increases, the size of semiconductor chip packages has become smaller and the capacity has increased and the functions thereof have been diversified. There is a chip scale package in the semiconductor chip package to meet this trend. Chip scale packages can be minimized to chip size and can be applied to semiconductor chips requiring a large number of leads by adopting a ball grid array (BGA) method.

반면에 다기능화를 위한 반도체 칩 패키지에는, 패키지 몸체 형성이 완료된 반도체 칩 패키지를 적층하여 형성한 적층 칩 패키지가 있다. 종래 기술에 따른 적층 칩 패키지는, 반도체 칩을 적층한 후 패키지 몸체를 형성하거나, 패키지 몸체 형성 공정까지 완료된 반도체 칩 패키지를 적층함으로써 구비된다.On the other hand, in the semiconductor chip package for multifunction, there is a stacked chip package formed by stacking a semiconductor chip package in which package body formation is completed. The stacked chip package according to the prior art is provided by stacking semiconductor chips to form a package body or stacking semiconductor chip packages completed up to the package body forming process.

이하, 도면을 참조하여 종래 기술에 따른 적층 칩 패키지를 설명하겠다.Hereinafter, a multilayer chip package according to the related art will be described with reference to the drawings.

도 1 및 도 2는 종래 기술에 따른 적층 칩 패키지의 단면도이다.1 and 2 are cross-sectional views of stacked chip packages according to the prior art.

도 1과 같이 종래 기술에 따른 적층 칩 패키지는, 적층된 반도체 칩(211, 221)과, 반도체 칩(211, 221)에 구비된 본딩 패드(213, 223)와 와이어(215, 225)에 의해 연결된 리드(240), 및 반도체 칩(211, 221)과 와이어(215, 225), 일부분의 리드(240)를 봉지하여 형성된 패키지 몸체(230)가 구비된다.As shown in FIG. 1, the stacked chip package according to the related art is formed by stacked semiconductor chips 211 and 221, bonding pads 213 and 223 and wires 215 and 225 provided in the semiconductor chips 211 and 221. A package body 230 formed by encapsulating the leads 240 connected to each other, the semiconductor chips 211 and 221, the wires 215 and 225, and a part of the leads 240 are provided.

이와 같은 적층 칩 패키지(200)는 복수개의 반도체 칩(211, 221)이 적층되어 구비된다. 따라서 하부에 위치한 반도체 칩(211)은 에지 본딩 패드형(edgy bonding pad type)으로 구비되어야 하며, 상부에 위치된 반도체 칩(221)만이 선택적으로 구비될 수 있다. 또한 공정 중 형성된 일련의 공정이 완료된 후 적층 칩 패키지(200)의 전기 검사가 실시될 수 있으므로, 불량 반도체 칩(211, 221)을 인식하지 못하고 최종 공정까지 진행되므로 공정 소모에 따른 생산성 및 경제성이 감소된다.The stacked chip package 200 includes a plurality of semiconductor chips 211 and 221 stacked thereon. Therefore, the semiconductor chip 211 disposed below should be provided as an edge bonding pad type, and only the semiconductor chip 221 located above may be selectively provided. In addition, since the electrical inspection of the multilayer chip package 200 may be performed after a series of processes formed in the process, the defective semiconductor chips 211 and 221 are not recognized, and the process proceeds to the final process. Is reduced.

도 2에 따른 종래 기술에 따른 적층 칩 패키지(300)는, 복수개의 반도체 칩 패키지(320)가 적층되어 구비된다. 반도체 칩 패키지(320)는 본딩 패드(323)가 구비된 반도체 칩(321)과, 본딩 패드(323)와 와이어(325)에 의해 연결된 리드(324), 반도체 칩(321)과 일부분의 리드(324) 및 와이어(325)가 포함되도록 봉지되어 형성된 패키지 몸체(326)가 구비된다. 이와 같은 반도체 칩 패키지(320, 320)들은 수직으로 적층된 후, 패키지 몸체(326) 외부로 노출된 리드(324)에 의해 상호 물리적, 전기적으로 연결되어 적층 칩 패키지(300)로 구비된다.In the stacked chip package 300 according to the related art of FIG. 2, a plurality of semiconductor chip packages 320 are stacked. The semiconductor chip package 320 includes a semiconductor chip 321 having a bonding pad 323, leads 324 connected by the bonding pads 323 and wires 325, semiconductor chips 321, and a portion of the leads ( The package body 326 encapsulated to include the 324 and the wire 325 is provided. After the semiconductor chip packages 320 and 320 are vertically stacked, the semiconductor chip packages 320 and 320 are physically and electrically connected to each other by leads 324 exposed to the outside of the package body 326 to be provided as the stacked chip package 300.

이와 같은 적층 칩 패키지(300)는 개개의 반도체 칩 패키지(310, 320)의 반도체 칩(321)이 센터 본딩 패드형 또는 에지 본딩 패드형으로 구비될 수 있으며, 검사 공정에 의해 완료된 정상 제품으로 판정된 반도체 칩 패키지(310, 320)가 적층되므로 불량 제품으로 인한 공정 소모가 감소된다. 그러나, 반도체 칩(321)이 센터 본딩 패드형으로 구비되는 경우, 와이어(325) 길이 및 루프 높이(loop height)가 증가되어 패키지 몸체(326) 외부로 와이어(325)가 돌출되거나 반도체 칩(321)이그 위치를 벗어나게 될 우려가 있다. 더불어 자체 크기가 비교적 큰 반도체 칩 패키지(310, 320)가 적층되므로, 적층 수가 증가될수록 적층 칩 패키지의 경박 소형화는 더욱 어려워진다.The stacked chip package 300 may include a semiconductor chip 321 of each semiconductor chip package 310 or 320 as a center bonding pad type or an edge bonding pad type, and may be determined as a normal product completed by an inspection process. Since the semiconductor chip packages 310 and 320 are stacked, process consumption due to defective products is reduced. However, when the semiconductor chip 321 is provided as a center bonding pad type, the length of the wire 325 and the loop height are increased so that the wire 325 protrudes out of the package body 326 or the semiconductor chip 321 is increased. There is a possibility that it will be out of position. In addition, since the semiconductor chip packages 310 and 320 having a relatively large size are stacked, as the number of stacks increases, the miniaturization of the laminated chip package becomes more difficult.

본 발명의 목적은 칩 스케일 패키지 복수개를 적층하여 적층 칩 패키지를 구현하는데 있다.An object of the present invention is to implement a stacked chip package by stacking a plurality of chip scale packages.

도 1 및 도 2는 종래 기술에 따른 적층 칩 패키지의 단면도,1 and 2 are cross-sectional views of a stacked chip package according to the prior art,

도 3은 본 발명에 따른 적층 칩 스케일 패키지의 단면도이다.3 is a cross-sectional view of a stacked chip scale package according to the present invention.

* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing

100 : 적층 칩 스케일 패키지100: Stacked Chip Scale Package

111, 121, 211, 221, 321 : 반도체 칩111, 121, 211, 221, 321: semiconductor chip

110 : 하부 칩 스케일 패키지120 : 상부 칩 스케일 패키지110: lower chip scale package 120: upper chip scale package

112, 122 : 테이프 기판112a, 122a : 슬롯112, 122: tape substrate 112a, 122a: slot

113, 123, 213, 223, 323 : 본딩 패드113, 123, 213, 223, 323: bonding pads

114, 124 : 접속 수단115, 215, 225, 325 : 와이어114, 124: connection means 115, 215, 225, 325: wire

116, 126 : 보호막117, 127 : 금속층116, 126: protective film 117, 127: metal layer

117a, 127a : 와이어 핑거118, 128 : 봉합부117a, 127a: wire finger 118, 128: suture

119, 129 : 봉지부150 : 접착 수단119, 129: sealing portion 150: adhesive means

160 : 솔더 볼163 : 솔더 패드160: solder ball 163: solder pad

200, 300 : 적층 칩 패키지230, 326 : 패키지 몸체200, 300: stacked chip package 230, 326: package body

240, 324 : 리드310, 320 : 반도체 칩 패키지240, 324: lead 310, 320: semiconductor chip package

상기 목적을 달성하기 위하여, 본 발명에 따른 적층 칩 스케일 패키지는, 소정의 회로가 구성된 금속층이 형성된 상면과 상면과 반대되는 하면 및 상면과 하면을 관통하는 슬롯을 갖는 테이프 기판과, 와이어 핑거가 노출되도록 금속층 상에 형성된 보호막과, 본딩 패드가 형성된 활성면과 그와 반대되는 배면을 가지며 슬롯 입구에 본딩 패드가 위치되도록 기판에 활성면이 부착된 반도체 칩과, 슬롯을 통해 본딩 패드와 금속 패턴을 전기적으로 연결하는 접속 수단과, 슬롯 및 와이어를 봉지하는 봉합부를 포함하는 상부 칩 스케일 패키지와 하부 칩 패키지를 포함하며, 하부 칩 스케일 패키지의 배면은 상부 칩 스케일 패키지의 보호막과 마주보도록 접착 수단에 의해 부착되고, 하부 칩 스케일 패키지의 와이어 핑거는 그와 대응되는 상부 칩 스케일 패키지의 와이어 핑거와 와이어에 의해 연결되며, 하부 칩 스케일 패키지의 금속층에 구비된 솔더 패드에는 솔더 볼이 부착되는 것을 특징으로 한다.In order to achieve the above object, the laminated chip scale package according to the present invention, a tape substrate having a lower surface opposite to the upper surface and the upper surface and a slot penetrating through the upper surface and the lower surface on which a metal layer formed with a predetermined circuit is formed, the wire finger is exposed A semiconductor layer having a protective film formed on the metal layer, a back surface opposite to the active surface on which the bonding pad is formed, and an active surface attached to the substrate so that the bonding pad is positioned at the slot inlet, and the bonding pad and the metal pattern through the slot. An upper chip scale package and a lower chip package including connecting means for electrically connecting and a seal for sealing a slot and a wire, wherein a rear surface of the lower chip scale package is formed by adhesive means so as to face a protective film of the upper chip scale package. The wire fingers of the lower chip scale package are attached to the upper chip scale pads corresponding thereto. Is connected by a wire magazine finger and the wire, the solder pads provided on the metal layer of the lower chip scale package is characterized in that the mounting solder balls.

여기서, 와이어가 포함되도록 하부 칩 스케일 패키지의 와이어 핑거와 측면 및, 상부 칩 스케일 패키지의 와이어 핑거에는 봉지부가 구비되는 것이 바람직하다. 또한 반도체 칩은 센터 본딩 패드형 또는 에지 본딩 패드형인 것이 바람직하다.Here, the encapsulation is preferably provided on the wire finger and the side of the lower chip scale package and the wire finger of the upper chip scale package to include the wire. In addition, the semiconductor chip is preferably a center bonding pad type or an edge bonding pad type.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 3은 본 발명에 따른 적층 칩 스케일 패키지의 단면도이다.3 is a cross-sectional view of a stacked chip scale package according to the present invention.

도 3과 같이, 본 발명에 따른 적층 칩 스케일 패키지(100)는 상부 칩 스케일 패키지(120) 상에 하부 칩 스케일 패키지(110)가 적층되어, 물리적, 전기적으로 상호 연결됨으로써 구비된다.As shown in FIG. 3, the stacked chip scale package 100 according to the present invention is provided by stacking a lower chip scale package 110 on an upper chip scale package 120 to be physically and electrically interconnected.

상부 칩 스케일 패키지(120)와 하부 칩 스케일 패키지(110)는, 소정의 회로가 구성된 금속층(117, 127)이 형성된 상면과, 상면과 반대되는 하면, 및 상면과 하면을 관통하는 슬롯(112a, 122a)을 갖는 테이프 기판(112, 122)이 구비된다. 반도체 칩(111, 121)은 본딩 패드(113, 123)가 형성된 활성면(111a, 121a)과 그와 반대되는 배면(111b, 121b)을 가지며, 이 때 테이프 기판(112, 122)의 슬롯(112a, 122a)을 통해 본딩 패드(113, 123)가 노출되도록 테이프 기판(112, 122)의 하면에 활성면(111a, 121a)이 부착된다. 또한 보호막(116, 126)은 와이어 핑거(117a, 127a)가 노출되도록 금속층(117, 127) 상에 형성되고, 접속 수단(114, 124)은 슬롯(112a, 122a)을 통해 본딩 패드(113, 123)와 금속층(117, 127)을 전기적으로 연결한다. 접속 수단(114, 124)은 빔 리드 본딩(beam lead bonding)법에 의해 구비되고, 슬롯(112a, 122a) 및 슬롯(112a, 122a) 내부에 위치된 접속 수단(114, 124)은 봉합부(118, 128)에 의해 봉지된다. 봉합부(118, 128)는 에폭시 몰딩수지(epoxy molding compound; EMC)와 같은 플라스틱 봉지 수지에 의해 구비된다.The upper chip scale package 120 and the lower chip scale package 110 may include an upper surface on which metal layers 117 and 127 including predetermined circuits are formed, a lower surface opposite to the upper surface, and slots 112a penetrating through the upper and lower surfaces. Tape substrates 112 and 122 having 122a) are provided. The semiconductor chips 111 and 121 have active surfaces 111a and 121a on which the bonding pads 113 and 123 are formed and rear surfaces 111b and 121b opposite thereto, and slots of the tape substrates 112 and 122 The active surfaces 111a and 121a are attached to the lower surfaces of the tape substrates 112 and 122 so that the bonding pads 113 and 123 are exposed through the 112a and 122a. In addition, the passivation layers 116 and 126 are formed on the metal layers 117 and 127 so that the wire fingers 117a and 127a are exposed, and the connecting means 114 and 124 are bonded to the bonding pads 113 and 124 through the slots 112a and 122a. 123 and the metal layers 117 and 127 are electrically connected to each other. The connecting means 114 and 124 are provided by a beam lead bonding method, and the connecting means 114 and 124 located inside the slots 112a and 122a and the slots 112a and 122a are sutures ( 118, 128). The seals 118 and 128 are provided by a plastic encapsulation resin such as an epoxy molding compound (EMC).

이와 같은 하부 칩 스케일 패키지(110)의 반도체 칩(111)의 배면(111b)은 적층될 상부 칩 스케일 패키지(120)의 보호막(126)과 마주보도록 접착 수단(150)에 의해 부착되어 적층되고, 이 때 사용되는 접착 수단(150)으로는 시트 타입(sheet type)의 엘라스토머(elastomer)가 적합하다. 접착 수단(150)은 상부/하부 패키지(110, 120)의 물리적인 접착 기능이외에도, 상부 칩 스케일 패키지(120)의 봉합부(128)를 보호하는 기능을 갖는다. 하부 칩 스케일 패키지(110)의 와이어 핑거(117a)는 그와 대응되는 상부 칩 스케일 패키지(120)의 와이어 핑거(127a)와 와이어(115)에 의해 연결됨으로써, 상부/하부 칩 스케일 패키지(110, 120)들을 상호 전기적, 물리적으로 연결시킨다. 더불어 하부 칩 스케일 패키지(110)의 금속층(117)에 구비된 솔더 패드(163)에는 솔더 볼(160)이 부착된다.The rear surface 111b of the semiconductor chip 111 of the lower chip scale package 110 is attached and laminated by the adhesive means 150 to face the passivation layer 126 of the upper chip scale package 120 to be stacked. At this time, the adhesive means 150 is a sheet type (elastomer) is suitable. The adhesive means 150 has a function of protecting the seal 128 of the upper chip scale package 120 in addition to the physical adhesive function of the upper / lower packages 110 and 120. The wire fingers 117a of the lower chip scale package 110 are connected by the wires 115 and the wire fingers 127a of the upper chip scale package 120 corresponding thereto, whereby the upper / lower chip scale packages 110, 120) are electrically and physically connected to each other. In addition, the solder ball 160 is attached to the solder pad 163 provided in the metal layer 117 of the lower chip scale package 110.

하부 칩 스케일 패키지(110)의 와이어 핑거(117a)와 측면 및, 상부 칩 스케일 패키지(120)의 와이어 핑거(127a)에는 와이어(115)가 포함되도록 봉지부(119)가 구비된다. 봉지부(119)는 봉합부(118, 128)와 같은 에폭시 몰딩 수지와 같은 플라스틱 봉지 수지에 의해 구비되어, 와이어(115) 및 와이어 핑거(117a, 127a)와 와이어(115)의 접합부를 외부 환경으로부터 보호하는 기능을 갖는다.The encapsulation portion 119 is provided to include the wire 115 at the wire finger 117a and the side of the lower chip scale package 110 and the wire finger 127a of the upper chip scale package 120. The encapsulation portion 119 is provided by a plastic encapsulation resin such as an epoxy molding resin such as the encapsulation portions 118 and 128, so that the junction between the wire 115 and the wire fingers 117a and 127a and the wire 115 is external to the environment. Has the function of protecting against.

상부/하부 칩 스케일 패키지(110, 120)의 반도체 칩(111, 121)은 센터 본딩 패드형 또는 에지 본딩 패드형으로 구비될 수 있으며, 두 가지를 혼용한 형태의 적층 칩 스케일 패키지로 구비될 수 있다.The semiconductor chips 111 and 121 of the upper / lower chip scale packages 110 and 120 may be provided in a center bonding pad type or an edge bonding pad type, and may be provided in a stacked chip scale package of two types. have.

이와 같은 상부/하부 칩 스케일 패키지의 제조 공정은 종래 기술에 따른 칩스케일 패키지의 제조 공정과 유사하므로 종래의 장치를 이용 할 수 있으므로 추가 장치가 구비될 필요가 없다. 또한 단위 칩 스케일 패키지의 제조가 완료된 후, 검사 공정이 실시될 수 있다. 따라서 양품을 선별하여 적층 공정을 실시할 수 있으므로, 불량품을 적층함에 따른 공정 소모가 방지될 수 있다.Since the manufacturing process of the upper / lower chip scale package is similar to the manufacturing process of the chip scale package according to the prior art, a conventional apparatus may be used, and thus no additional apparatus is required. In addition, after the manufacturing of the unit chip scale package is completed, the inspection process may be performed. Therefore, since the lamination process may be performed by selecting good products, process consumption due to lamination of defective products may be prevented.

한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented.

본 발명의 구조에 따른 적층 칩 스케일 패키지는 복수개의 칩 스케일 패키지를 적층하여 구비되므로 적층 칩 패키지의 경박 소형화가 가능하며, 각 칩 스케일 패키지는 검사 공정이 완료된 후 적층이 실시되므로, 제품의 신뢰성 증가 및 불량품 적층으로 인한 공정 소모가 감소될 수 있다.Since the stacked chip scale package according to the structure of the present invention is provided by stacking a plurality of chip scale packages, it is possible to reduce the thickness of the stacked chip package, and each chip scale package is stacked after the inspection process is completed, thereby increasing the reliability of the product. And process consumption due to defective stacking.

또한 반도체 칩은 빔 리드 본딩법에 전기적으로 연결되므로, 와이어 사용에 따른 두께 증가, 와이어 뒤틀림 등의 종래 기술에 따른 문제 발생없이 센터 본딩 패드형 또는 에지 본딩 패드형의 반도체 칩으로 선택적으로 구비될 수 있다.In addition, since the semiconductor chip is electrically connected to the beam lead bonding method, the semiconductor chip may be selectively provided as a center bonding pad type or an edge bonding pad type semiconductor chip without problems such as an increase in thickness and wire distortion caused by wire use. have.

더불어 본 발명의 칩 스케일 패키지는 종래 기술에 따른 칩 스케일 패키지의 장치를 이용하여 구비될 수 있으므로 추가 장치가 설치될 필요가 없으므로, 새로운 장치 및 기술 개발에 따른 경제적, 생산적 소모가 감소될 수 있다.In addition, since the chip scale package of the present invention can be provided using the device of the chip scale package according to the prior art, it is not necessary to install additional devices, so that economic and productive consumption of new devices and technology development can be reduced.

Claims (4)

소정의 회로가 구성된 금속층이 형성된 상면과 상기 상면과 반대되는 하면 및 상기 상면과 하면을 관통하는 슬롯을 갖는 테이프 기판과, 와이어 핑거가 노출되도록 상기 금속층 상에 형성된 보호막과, 본딩 패드가 형성된 활성면과 그와 반대되는 배면을 가지며 상기 슬롯 입구에 상기 본딩 패드가 위치되도록 상기 기판에 활성면이 부착된 반도체 칩과, 상기 슬롯을 통해 상기 본딩 패드와 금속 패턴을 전기적으로 연결하는 접속 수단과, 상기 슬롯 및 와이어를 봉지하는 봉합부를 포함하는 상부 칩 스케일 패키지와 하부 칩 패키지를 포함하며,A tape substrate having a top surface on which a metal layer having a predetermined circuit is formed, a bottom surface opposite to the top surface, a slot penetrating the top surface and a bottom surface, a protective film formed on the metal layer so that wire fingers are exposed, and an active surface on which a bonding pad is formed A semiconductor chip having an active surface attached to the substrate such that the bonding pad is positioned at the inlet of the slot, and connecting means for electrically connecting the bonding pad and the metal pattern through the slot; An upper chip scale package and a lower chip package including a seal for sealing a slot and a wire, 상기 하부 칩 스케일 패키지의 상기 배면은 상기 상부 칩 스케일 패키지의 보호막과 마주보도록 접착 수단에 의해 부착되고, 상기 하부 칩 스케일 패키지의 와이어 핑거는 그와 대응되는 상기 상부 칩 스케일 패키지의 와이어 핑거와 와이어에 의해 연결되며, 상기 하부 칩 스케일 패키지의 금속층에 구비된 솔더 패드에는 솔더 볼이 부착되는 것을 특징으로 하는 적층 칩 스케일 패키지.The back surface of the lower chip scale package is attached by adhesive means to face the passivation layer of the upper chip scale package, and the wire fingers of the lower chip scale package are connected to the wire fingers and wires of the upper chip scale package corresponding thereto. And a solder ball is attached to a solder pad provided in the metal layer of the lower chip scale package. 제 1항에 있어서, 상기 와이어가 포함되도록 하부 칩 스케일 패키지의 와이어 핑거와 측면 및, 상기 상부 칩 스케일 패키지의 와이어 핑거에는 봉지부가 구비되는 것을 특징으로 하는 적층 칩 스케일 패키지.The multilayer chip scale package of claim 1, wherein an encapsulation part is provided on the wire finger and the side of the lower chip scale package and the wire finger of the upper chip scale package to include the wire. 제 1항에 있어서, 상기 반도체 칩은 센터 본딩 패드형인 것을 특징으로 하는The method of claim 1, wherein the semiconductor chip is characterized in that the center bonding pad type. 적층 칩 스케일 패키지.Stacked chip scale package. 제 1항에 있어서, 상기 반도체 칩은 에지 본딩 패드형인 것을 특징으로 하는 적층 칩 스케일 패키지.The stacked chip scale package of claim 1, wherein the semiconductor chip is an edge bonding pad type.
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