KR20030016053A - a thin film transistor array panel having a structure for preventing light leakage - Google Patents

Abstract

PURPOSE: A thin film transistor substrate with the structure of preventing light loss is provided to reduce light loss caused by influence of data line potential by forming shielding semiconductor layers on wires adjacent to data lines. CONSTITUTION: A thin film transistor substrate with the structure of preventing light loss includes an insulating substrate; a plurality of gate wires having gate lines(20) and gate electrodes; a plurality of maintenance wires including maintenance capacity lines(30) parallel to the gate lines and a plurality of maintenance electrodes(31,34); a gate insulating film formed on the gate lines and the maintenance wires; a channel part semiconductor layer(50) formed on the gate insulating film; shielding semiconductor layers(51,54) formed on the gate insulating film and overlapped with the part of the maintenance electrodes; a plurality of data wires including data lines(70) crossing the gate lines, source electrodes(71) spread over the channel part semiconductor layer, drain electrodes(72) facing the source electrodes spread over the channel part semiconductor layer; a protective layer covering the data wires and having contact holes exposing the drain electrodes; and pixel electrodes(90) formed in pixel areas and connected with the drain electrodes through the contact holes(81).

Description

A thin film transistor array panel having a structure for preventing light leakage

The present invention relates to a liquid crystal display device and a substrate used therein.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

However, in order for the liquid crystal display to have excellent image quality, the light transmission amount of each pixel must be accurately controlled by the input image signal. For this purpose, the electric field formed between each pixel electrode and the common electrode should be individually adjustable without being influenced by the surroundings. However, a data line for supplying an image signal and a gate line for supplying a scan signal are formed on the lower substrate on which the pixel electrode is formed, and the signal continuously flows through these wirings. Electrical signals flowing through these wires affect the electric field around them. As a result, the arrangement of the liquid crystal molecules is changed and unwanted transmission of light occurs. This phenomenon is called light leakage. In order to prevent such light leakage, a method of covering the boundary of the pixel region with a black matrix is provided, but light leakage still exists due to multiple reflections between the wiring and the black matrix.

An object of the present invention is to reduce the light leakage of the liquid crystal display device.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display device formed by combining the thin film transistor substrate and the color filter substrate of FIG. 1, and is a cross-sectional view taken along the line II-II ′ of FIG. 1.

3 is a view for explaining a principle of reducing light leakage in the liquid crystal display according to the first exemplary embodiment of the present invention.

4 is a graph showing transmittance curves according to angles in one gradation with and without light leakage;

FIG. 5 is a graph comparing reflectivity of light according to angles of a liquid crystal display according to a first exemplary embodiment of the present invention and a liquid crystal display according to the related art.

FIG. 6 is a graph in which the graph of FIG. 5 is normalized based on a reflectance of light of a liquid crystal display according to the related art (100%).

7A is a conceptual diagram illustrating an angle change of an optical path inside and outside a panel of a liquid crystal display device;

7B is a graph showing an optical path angle inside the panel corresponding to the optical path angle outside the panel;

8A, 9A, and 10A are views illustrating a process of manufacturing the thin film transistor substrate for the liquid crystal display device illustrated in FIG. 1, according to a process sequence;

8B, 9B and 10B are cross sectional views taken along line VIIIb-VIIIb 'of FIG. 8A, line IXb-IXb' of FIG. 9A, and line Xb-Xb 'of FIG. 10A, respectively.

11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

13 is a layout view of a color filter substrate for a liquid crystal display according to a third embodiment of the present invention;

14 is a layout view of a liquid crystal display according to a third exemplary embodiment of the present invention, in which a black matrix and color filter lines are omitted.

15 is a sectional view taken along line XV-XV ',

FIG. 16 is a diagram for describing a principle of reducing light leakage in the liquid crystal display according to the third exemplary embodiment of the present invention.

In order to solve this problem, in the present invention, the light shielding semiconductor layer is disposed around the data line.

Specifically, a plurality of holdings formed in the form of an insulating substrate, a gate wiring including a gate line formed on the substrate in a horizontal direction and a gate electrode which is a part of the gate line, and a storage capacitor line parallel to the gate line and a branch of the storage capacitor line. A storage wiring including an electrode, a gate insulating film formed on the gate line and the storage wiring, a channel portion semiconductor layer formed on the gate insulating film, and a light shielding layer formed on the gate insulating film and overlapping with some of the storage electrodes A semiconductor layer, a data line intersecting the gate line, a source electrode connected to the data line and over the channel portion semiconductor layer, and a drain electrode facing the source electrode and over the channel portion semiconductor layer. Data wiring, said A protective film covering a data line and having a contact hole for exposing the drain electrode, and a pixel electrode formed in a pixel region where the gate line and the data line cross each other and connected through the drain electrode and the contact hole; And a storage electrode overlapping the light blocking semiconductor layer to form a thin film transistor substrate formed in parallel with the data line.

In this case, the light blocking semiconductor layers may be disposed on upper portions of the sustain electrodes disposed on both sides of the data line, and the light blocking semiconductor layers may be disposed on both sides from below the data lines. It may be formed over the upper portion of the sustain electrode, wherein the pixel electrode is composed of several small portions, the small portion is a first flow that covers the sustain electrode and a second flow that does not cover the sustain electrode In order to distinguish, it is preferable that the said light shielding semiconductor layer is adjacent to the said 2nd class. The sustain electrode may be refracted to have a vertical portion and a horizontal portion, and the light blocking semiconductor layer may overlap the vertical portion of the sustain electrode, and at least a portion of the data line may overlap the data line. The semiconductor device may further include a data line semiconductor layer formed in a vertical direction and refracted to maintain a predetermined distance from the vertical portion of the sustain electrode.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the liquid crystal display formed by combining the thin film transistor substrate and the color filter substrate of FIG. 1. A cross-sectional view of the -II 'line.

The liquid crystal display according to the first exemplary embodiment of the present invention includes an upper substrate 100, a thin film transistor, a pixel electrode 91, etc., on which a black matrix 110, a color filter 120, a common electrode 130, and the like are formed. The lower substrate 10 and the liquid crystal material 200 injected between the upper substrate 100 and the lower substrate 10 are formed.

First, the lower substrate 10 will be described in more detail.

A gate line 20 extending in the horizontal direction is formed on a transparent insulating substrate 10 such as glass, and a storage capacitor line 30 is formed in parallel with the gate line. 21) It is formed in the form of a projection, and the first and second storage electrodes 31 and 34 are connected to the storage capacitor line 30 in the form of a branch. The first storage electrode 31 and the second storage electrode 34 are directly connected to the storage capacitor line 30 and are formed in the vertical direction. These two storage electrodes 31 and 34 are connected to the storage electrode connection part 35. Are connected to each other. The storage electrode connection part 35 is formed to cross the data line 70, which will be described later. A gate insulating film 40 is formed on the gate wirings 20 and 21 and the storage capacitor wirings 30, 31, 34, and 35, and a channel part made of amorphous silicon on the gate insulating film 40 above the gate electrode 21. The semiconductor layer 50 is formed. In addition, the light blocking semiconductor layers 51 and 54 are formed along the first and second storage electrodes 31 and 34 to extend vertically on the gate insulating layer 40 on the first and second storage electrodes 31 and 34. It is. Contact layers 61 and 62 made of amorphous silicon doped at high concentration with N-type impurities such as phosphorous are formed on the channel portion semiconductor layer 50. A source electrode 71 and a drain electrode 72 are formed on both contact layers 61 and 62, respectively, and the source electrode 71 is formed on the data line 70 extending in the vertical direction on the gate insulating film 40. It is connected. A passivation film 80 having a contact hole 81 exposing the drain electrode 72 is formed on the data lines 70, 71, and 72, and a drain electrode is formed on the passivation film 80 through the contact hole 81. The pixel electrode 90 connected to the 72 is formed. The pixel electrode 90 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As described above, when the light blocking semiconductor layers 31 and 34 are formed on the first and second sustain electrodes 31 and 34, light leakage caused by the influence of the potential of the data line 70 around the data line 70 is generated. Can be reduced. The reason why light leakage is reduced will be described later.

The upper substrate 100 will be described in more detail.

A black matrix 110 formed of a double layer of chromium and chromium oxide is formed on a transparent substrate 100 made of glass or the like to define a pixel region. Red, green, and blue color filters 120 are formed in each pixel area, and a common electrode 130 made of a transparent conductor is formed on the entire surface of the substrate 100 on the color filters 120.

The principle of light leakage is reduced by the present invention.

FIG. 3 is a diagram conceptually illustrating a periphery of the data line 70 of FIG. 2 to explain a principle of reducing light leakage in the liquid crystal display according to the first exemplary embodiment of the present invention.

First, look at the causes of light leakage.

Since the image signals must be sequentially supplied to all the pixel rows, the image signal voltage is continuously applied to the data line 70. However, due to the image signal voltage, the arrangement of liquid crystal molecules around the data line 70 is changed, and the polarization direction of light passing through the liquid crystal layer 200 is changed. When the light with the changed polarization direction is passed as it is, it is not blocked by the polarizing plate and is emitted through the screen of the liquid crystal display device to affect the image quality. In order to block such light, the black matrix 110 is formed to cover the periphery of the data line 70. However, a problem is that some of the light is reflected by the black matrix 110. Assuming that there is no light shielding semiconductor layer 54 in FIG. 3, a part of the light incident at an angle of θ ₂ is reflected by the black matrix 110, and then reflected by the second storage electrode 34, and thus the black matrix. Emitted through the portion not covered by 110.

However, when the light blocking semiconductor layer 54 is formed as shown in FIG. 3, even though some light is reflected by the black matrix 110, the semiconductor layer 54 absorbs and blocks the light. This is because the semiconductor layer 54 has a lower reflectance of light and absorbs most of incident light than the sustain electrode 34 which is a metal thin film.

In FIG. 3, light incident at an angle of θ ₁ may be emitted through a portion that is not obscured by the black matrix 110 even though the light blocking semiconductor layer 54 is present. It does not matter much because it does not contribute much.

4 is a graph showing transmittance curves according to angles in one gradation when light leakage occurs and when no light leakage occurs.

Referring to FIG. 4, when there are light leakages, light leakages appear only at one side angle. This is due to misalignment of the exposure mask generated during the thin film transistor substrate fabrication, so that light leakage is biased to one side. As shown in FIG. 4, when light leakage occurs severely, the transmittance is about 20-30%. This degree of transmittance is a degree which a viewer can fully recognize. Human perception is less than about 5%. Therefore, severe levels of light leakage, as in FIG. 4, need to be reduced to less than 1/5. In addition, it can be seen that the angle of light leakage is severe from 20 ° to 50 °.

FIG. 5 is a graph comparing reflectivity of light according to angles of a liquid crystal display according to a first exemplary embodiment of the present invention and a liquid crystal display according to the related art, and FIG. 6 illustrates the graph of FIG. 5 according to the prior art. It is a graph normalized by the reference (100%) of the light reflectance of a liquid crystal display device. In FIG. 5 and FIG. 6, the measurement was performed only at a portion having an incidence angle of 25 ° or more due to limitations of the measuring equipment. However, based on the measured values, parts below 25 ° can be estimated.

5, it can be seen that the light reflectance is significantly lower in the case where there is a light shielding semiconductor layer (first embodiment of the present invention) compared to the case where there is no light shielding semiconductor layer at all measured angles (prior art). . 6, it can be seen that the reflectance of light in the case of the light shielding semiconductor layer (first embodiment of the present invention) is about 30% to 40% of the reflectance in the case of the absence of the light shielding semiconductor layer (prior art). have. The ratio of the reflectance increases as the angle increases because the reflection at the interface between the protective film and the semiconductor layer increases.

FIG. 7A is a conceptual diagram illustrating an angle change of an optical path inside and outside a panel of a liquid crystal display, and FIG. 7B is a graph illustrating an optical path angle inside a panel corresponding to an optical path angle outside the panel.

As shown in Fig. 7A, the optical path angle is different from outside and inside of the liquid crystal panel because it is refracted by Snell's law. However, as can be seen in Figure 4, the angle of light leakage problem when viewed from the outside of the liquid crystal panel is between about 20 ° to 50 °. When this angle is converted into an angle inside the liquid crystal panel, it is between about 13 ° and 31 ° (see FIG. 7B). This range is the part surrounded by the square box in FIG. 6, within this range, the reflectance of light in the case of the light shielding semiconductor layer (first embodiment of the present invention) is reduced to around 30% of the reflectivity in the case of the absence of the light shielding semiconductor layer (prior art). Therefore, by applying the semiconductor layers 51 and 54 on the sustain electrodes 31 and 34, the light leakage, which is 25%, can be reduced to about 7-8%.

Next, a method of manufacturing the liquid crystal display device according to the first embodiment of the present invention will be described.

First, a method of manufacturing a thin film transistor substrate (lower substrate) will be described.

8A, 9A, and 10A are views illustrating a process of manufacturing the thin film transistor substrate for the liquid crystal display device shown in FIG. 1, according to a process sequence, and FIGS. 8B, 9B, and 10B are VIIIb-VIIIb ′ of FIG. 8A, respectively. It is sectional drawing about the line, the IXb-IXb 'line of FIG. 9A, and the Xb-Xb' line of FIG. 10A.

First, as shown in FIGS. 8A and 8B, the gate metal layers are stacked and photo-etched on the insulating substrate 10 to form the gate wirings 20 and 21 and the sustain electrode wirings 30, 31, 34, and 35. At this time, the gate metal layer is preferably formed of a double layer of a material having excellent physicochemical properties such as chromium and a material having excellent conductivity such as aluminum.

Next, as shown in FIGS. 9A and 9B, the silicon nitride, amorphous silicon, and amorphous silicon doped with N-type impurities are sequentially deposited on the gate wirings 20 and 21 and the sustain electrode wirings 30, 31, 34, and 35. To form the gate insulating film 40, the semiconductor layers 50, 51, 54 and the contact layer 60, and photo-etch the semiconductor layers 50, 51, 54 and the contact layer 60 together to form a channel portion semiconductor layer. 50 and the light shielding semiconductor layers 51 and 54 and the contact layer 60 thereon are patterned.

As shown in FIGS. 10A and 10B, data metal layers are stacked and photo-etched to form data wires 70, 71, and 72. At this time, the data metal layer is preferably formed of a double layer of a material having excellent physicochemical properties such as chromium and a material having excellent conductivity such as aluminum. Subsequently, the exposed contact layer 60 is etched using the data wires 70, 71, and 72 as an etch stop layer to form contact layers 61 and 62 separated on both sides of the channel portion semiconductor layer 50. In addition, all of the contact layers 60 are removed from the light blocking semiconductor layers 51 and 54.

Next, as shown in FIGS. 1 and 2, a silicon nitride or the like is deposited on the data lines 70, 71, and 72, or an organic layer is coated to form a passivation layer 80, and the passivation layer 80 is photo-etched to drain electrodes. The contact hole 81 exposing the 72 is formed. Subsequently, a transparent conductive material such as indium tin oxide (ITO) or indium tin oxide (IZO) is deposited and photo-etched to form a pixel electrode 90 connected to the drain electrode 72.

The method of manufacturing a color filter substrate (upper substrate) is the same as the manufacturing method of a conventional color filter substrate. That is, the black matrix 110 is formed by depositing and photo-etching chromium on the insulating substrate 100, and the process of repeatedly applying, exposing and developing photosensitive organic materials including pigments of each color to red, green, and blue. Color filter 120 is formed. Subsequently, a transparent conductive material such as ITO or IZO is deposited on the color filter 120 to form the common electrode 130. The black matrix 110 may be formed of a double layer of chromium and chromium oxide or may be formed of an organic material to further reduce light reflection. However, when the black matrix 110 is formed as a double layer, a process must be added, and since organic materials are expensive, the cost increases. Therefore, when the light shielding semiconductor layer is provided as in the present invention, it does not need to be applied.

A second embodiment of the present invention will be described.

11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

In the second embodiment, in the case where the semiconductor layer is left under the data line for the purpose of preventing the data line from being disconnected due to a step or reducing the parasitic capacitance, the light shielding semiconductor layer is formed from the semiconductor layer under the data line. It is designed to prevent sticking.

A gate line 20 extending in the horizontal direction is formed on a transparent insulating substrate 10 such as glass, and a storage capacitor line 30 is formed in parallel with the gate line. The gate electrode 20 is formed in the form of a protrusion of the gate electrode 21, and the storage electrodes 36, 37, 38, 32, and 33 are connected to the storage capacitor line 30 in the form of a branch. The storage electrodes 36, 37, 38, 32, and 33 are connected to the first vertical portion 36 and the first vertical portion 36, which are directly connected to the storage capacitor line 30 and formed in the vertical direction, and are horizontal. Is connected to the first horizontal portion 32, the first horizontal portion 32 formed in the direction, and is connected to the second vertical portion 36 and the second vertical portion 36 formed in the longitudinal direction, It consists of the 2nd horizontal part 33 formed in the direction, and the 3rd vertical part 36 connected to the 2nd horizontal part 33, and formed in the vertical direction. A gate insulating film 40 is formed on the gate wirings 20 and 21 and the storage capacitor wirings 30, 32, 33, 36, 37, and 38, and on the gate insulating film 40 above the gate electrode 21. The channel portion semiconductor layer 50 made of silicon is formed. In addition, on the gate insulating layer 40 on the first to third storage electrodes 36, 37, and 38, the light blocking semiconductor layers 55, 56, and 57 are respectively formed on the first to third storage electrodes 36, 37, and 38. It is formed long vertically along). In addition, the data line semiconductor layer 58 connected to the channel semiconductor layer 50 extends in the longitudinal direction. Here, the data line semiconductor layer 58 is partially refracted to maintain a constant distance from the light shielding semiconductor layers 55, 56, and 57. On the semiconductor layer 50 and the data line semiconductor layer 58, a contact layer (not shown) made of amorphous silicon heavily doped with N-type impurities such as phosphorous is formed. The source electrode 71 and the drain electrode 72 are formed on the contact layer, respectively, and the source electrode 71 is connected to the data line 70 extending in the vertical direction. The data line 70 is formed on the contact layer formed on the data line semiconductor layer 58. A passivation film 80 having a contact hole 81 exposing the drain electrode 72 is formed on the data lines 70, 71, and 72, and a drain electrode is formed on the passivation film 80 through the contact hole 81. The pixel electrode 90 connected with the 72 is formed. The pixel electrode 90 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

When the light blocking semiconductor layers 55, 56, 57 are formed in this manner, light leakage caused by the influence of the potential of the data line 70 around the data line 70 can be reduced, and the light blocking semiconductor layers 55, 56 and 57 can be prevented from being connected to the data line semiconductor layer 58.

A third embodiment of the present invention will be described.

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third embodiment of the present invention, FIG. 13 is a layout view of a color filter substrate for a liquid crystal display according to a third embodiment of the present invention, and FIG. FIG. 15 is a cross-sectional view of the liquid crystal display according to the third exemplary embodiment, omitting the black matrix and the color filter lines, and FIG. 15.

First, the thin film transistor substrate of the liquid crystal display according to the third embodiment will be described with reference to FIGS. 12 and 15.

The gate line 20 extending in the horizontal direction is formed on the transparent insulating substrate 10 such as glass, and the storage capacitor line 30 is formed in parallel with the gate line 20. The gate electrode 20 is formed in the form of a protrusion of the gate electrode 21, and the first to fourth storage electrodes 31, 32, 33, and 34 are connected to the storage capacitor line 30 in the form of a branch. have. The first storage electrode 31 is directly connected to the storage capacitor line 30 and formed in the vertical direction, and the second storage electrode 32 and the third storage electrode 33 are connected to the first storage electrode 31, respectively. Are stretched in the horizontal direction. The fourth storage electrode 34 is connected to the second and third storage electrodes 32 and 33 and extends in the vertical direction. In addition, the first storage electrode 31 and the fourth storage electrode 34 of neighboring pixels are connected to each other by the first and second storage electrode connectors 35 and 36. The gate insulating film 40 is formed on the gate wirings 20 and 21 and the storage capacitor wirings 30, 31, 32, 33, 34, 35, and 36. The channel portion semiconductor layer 50 made of amorphous silicon is formed on the gate insulating layer 40 on the gate electrode 21, and the first storage electrode 31 and the fourth storage electrode 34 of two neighboring pixels are formed. A light shielding semiconductor layer 52 is formed between the two sustain electrodes 31 and 34 so as to overlap with each other. On the semiconductor layers 50 and 52, contact layers 61, 62 and 63 made of amorphous silicon doped at high concentration with N-type impurities such as phosphorus are formed. The source electrode 71, the drain electrode 72, and the data line 70 are formed on the contact layers 61, 62, and 63, respectively, and the source electrode 71 extends in the vertical direction. Is connected to. A passivation film 80 having a contact hole 81 exposing the drain electrode 72 is formed on the data lines 70, 71, and 72, and a drain electrode is formed on the passivation film 80 through the contact hole 81. The pixel electrode 90 connected to the 72 is formed. The pixel electrode 90 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this case, the pixel electrode 90 is separated into first to third small portions 91, 92, and 93, and these small portions are connected to each other through the connecting portions 94 and 95. The first small portion 91 has a rectangular shape in which four corners are cut out (hereinafter referred to as "chamfering") at the lower half of the pixel area defined by the intersection of the two gate lines 20 and the two data lines 70. It is formed and is directly connected to the drain electrode 72 through the contact hole 81. The second and third small portions 92 and 93 are formed in a rectangular shape with four corners cut out on the upper half of the pixel region. The second small portion 92 is connected via the first small portion 91 and the first connecting portion 94, and the third small portion 93 is the second small portion 92 and the second connecting portion 95. Connected via In this case, the second storage electrode 32 is positioned between the first small portion 91 and the second small portion 92, and the third small portion 92 is disposed between the second small portion 92 and the third small portion 93. The storage electrode 33 is positioned, and the first storage electrode 31 and the fourth storage electrode 34 are positioned between the pixel electrode 90 and the data line 70. The first small portion 91 is longer than the side parallel to the data line and the side parallel to the gate line, and the second small portion and the third small portion is shorter than the side parallel to the data line and the side parallel to the gate line. In this case, the second and third small portions 92 and 93 overlap the first and fourth storage electrodes 31 and 34, but the first small portion 91 is the first and fourth storage electrodes 31 and 34. Do not overlap with). The storage capacitor line 30 is positioned between the gate line 20 and the third small portion 93. At this time, the common electrode potential of the color filter substrate which will be described later is usually applied to the storage capacitor wirings 30, 31, 32, 33, 34, 35, and 36.

As described above, when the storage capacitor line or the storage electrode to which the common potential is applied between the data line and the pixel electrode and between the gate line and the pixel electrode is disposed, the influence of the data line potential and the gate line potential on the electric field of the pixel region is maintained. The electrodes may be blocked to form stable domains.

Next, the color filter substrate of the liquid crystal display according to the third exemplary embodiment of the present invention will be described with reference to FIGS. 13 and 15.

A black matrix 110 made of chromium is formed on the transparent substrate 100 made of glass or the like to define the pixel region. A color filter 120 is formed in each pixel area, an overcoat layer 140 made of an organic insulating material is formed on the color filter 120, and a common electrode 130 made of a transparent conductor on the overcoat layer 140. ) Is formed on the entire surface of the substrate 100. In this case, the common electrode 130 has first to third openings 410, 420, and 430. The first opening 410 divides the lower half of the pixel area from side to side, and the second opening 420 and the third opening 430 divide the upper half of the pixel area into three parts. Both ends of each of the openings 410, 420, and 430 gradually expand to form an isosceles triangle.

In the above, the black matrix may be formed of a bilayer of chromium and chromium oxide or may be formed of an organic material.

Next, a liquid crystal display according to a third exemplary embodiment of the present invention will be described with reference to FIGS. 14 and 15.

When the thin film transistor substrate of FIG. 12 and the color filter substrate of FIG. 13 are aligned and combined, a liquid crystal material is injected between the two substrates to align vertically, and the two polarizing plates are disposed outside the two substrates such that their polarization axes are perpendicular to each other. A liquid crystal display device according to a third embodiment is provided. When the two substrates are aligned, the small portions 91, 92, and 93 of the pixel electrode 90 of the thin film transistor substrate and the openings 410, 420, and 430 formed in the common electrode 400 of the color filter substrate overlap with each other. The pixel region is divided into a plurality of domains. In this case, each of the small portions 91, 92, and 93 of the pixel electrode 90 has two long sides and two cross sections, and the long sides of each of the small portions are parallel to the data line 70 or the gate line 20. And it forms 45 degrees with the polarization axis of a polarizing plate. Here, when the long side of each of the small portions 91, 92, 93 of the pixel electrode is positioned adjacent to the data line 70 or the gate line 20, between the data line 70 and the long side and the gate line 20. The storage capacitor line 30 and the storage electrodes 31, 32, 33, and 34 are disposed between the long side and the long side. In this case, the storage capacitor line 30 or the storage electrodes 31, 32, 33, and 34 may partially overlap the pixel electrode 90. That is, the storage capacitor line 30 and the storage electrodes 31, 32, 33, and 34 may extend over the long side of the domain. On the other hand, the storage capacitor wirings 30, 31, 32, 33, and 34 are not arranged around the short sides of the small portions 91, 92, and 93 of the pixel electrode, or the pixel electrodes 90 are disposed when the storage capacitor wirings 30, 31, 32, 33, 34 are arranged. Completely covered or at least 3 μm away from the pixel electrode 90.

As described above, by arranging the sustain wiring to which the common potential is applied between the data line and the gate line and the long side of the pixel electrode, the sustain wiring is blocked while maintaining the effect of the data line potential and the gate line potential on the electric field inside the domain. The common potential applied to the sustain wiring serves to strengthen the fringe field (an inclined electric field intentionally formed to control the direction in which the liquid crystal is inclined) to form a stable domain. In addition, the storage capacitor line or the storage electrode is not disposed around the short side of the small portion of the pixel electrode, or the pixel electrode is disposed so as to cover the storage wiring (the holding wiring is located inside the domain) or to be spaced 3 m or more away. This prevents the common potential applied to the sustain wiring from affecting the electric field inside the domain. This is because, on the short side, unlike the long side of the small portion of the pixel electrode, the common potential of the sustain wiring acts to disperse the fringe field inside the domain.

In addition, by providing the light shielding semiconductor layer 52, light leakage caused by the influence of the data line 70 potential around the data line 70 can be reduced. This will be described with reference to FIG. 16.

FIG. 16 is a diagram for describing a principle of reducing light leakage in the liquid crystal display according to the third exemplary embodiment of the present invention.

Referring to FIG. 16, light incident to light at the angle θ ₁ or θ ₂ may cause light leakage around the data line 70 to pass through the light blocking semiconductor layer 52 once. In the process of passing through the light shielding semiconductor layer 52, a considerable amount of light is absorbed and blocked. Therefore, light leakage is reduced.

In the above, although described with reference to the most practical and preferred embodiment of the present invention, the present invention is not limited to the embodiment disclosed above. It is intended that the scope of the invention include various modifications and equivalents falling within the scope of the following claims.

By forming the light shielding semiconductor layer on the wiring adjacent to the data line, light leakage due to the influence of the data line potential can be reduced.

Claims (6)

Insulation board, A gate wiring including a gate line formed on the substrate in a horizontal direction and a gate electrode which is a part of the gate line; A storage wiring including a plurality of storage electrodes formed in the form of a branch of the storage capacitor line parallel to the gate line and the storage capacitor line; A gate insulating film formed over the gate line and the sustain wiring; A channel portion semiconductor layer formed on the gate insulating layer; A light blocking semiconductor layer formed on the gate insulating layer and overlapping with a portion of the sustain electrode; A data line including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode on the channel portion semiconductor layer, and a drain electrode facing the source electrode and on the channel portion semiconductor layer; A protective film covering the data line and having a contact hole exposing the drain electrode, A pixel electrode formed in the pixel area where the gate line and the data line cross each other and connected through the drain electrode and the contact hole; And a sustain electrode overlapping the light blocking semiconductor layer, the thin film transistor substrate being formed in parallel with the data line. In claim 1, The light blocking semiconductor layer is disposed on an upper portion of the sustain electrode disposed on both sides of the data line. In claim 1, The light blocking semiconductor layer is formed from a lower portion of the data line to an upper portion of the sustain electrode disposed on both sides thereof. In claim 3, The pixel electrode is composed of several small portions, and when the small portions are divided into a first class covering the sustain electrode and a second class not covering the sustain electrode, the light blocking semiconductor layer is formed of the second class. Adjacent thin film transistor substrates. In claim 1, The sustain electrode is refracted to have a vertical portion and a horizontal portion, and the light blocking semiconductor layer overlaps the vertical portion of the sustain electrode. In claim 5, The thin film transistor substrate further includes a data line semiconductor layer overlapping at least a portion of the data line and formed in a vertical direction along the data line and refracted to maintain a predetermined distance from the vertical portion of the sustain electrode. .