KR20030015781A - Plasma Display Panel And Method Of Driving The Same - Google Patents

Abstract

PURPOSE: A plasma display panel is provided, which minimizes mis-discharge generation. CONSTITUTION: An upper plate has a sustain electrode pair, an upper dielectric layer and a protection film formed sequentially on an upper substrate. A lower plate has an address electrode(52), a lower dielectric layer, a partition wall and a luminous layer formed sequentially on a lower substrate. A data signal for selecting cells displayed is supplied to the address electrode(52). In the address electrode(52), the width of a portion intersected with a scan/sustain electrode of the sustain electrode pair is formed more widely by about 20 micrometers.

Description

Plasma Display Panel And Method Of Driving The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and a driving method thereof capable of minimizing the occurrence of false discharge.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. The PDP normally displays an image by adjusting the discharge period of each pixel according to the digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is a perspective view illustrating a cell structure typically arranged in an alternating current PDP in a matrix form, and FIG. 2 is a cross-sectional view of the PDP shown in FIG. 1.

1 and 2, the PDP cell includes an upper plate having sustain electrode pairs 14 and 16, an upper dielectric layer 18, and a passivation layer 20 sequentially formed on the upper substrate 10, and a lower substrate ( 12, a lower plate having an address electrode 22, a lower dielectric layer 24, a partition wall 26, and a phosphor layer 28, which are sequentially formed on the substrate 12, is provided. The upper substrate 10 and the lower substrate 12 are spaced in parallel by the partition wall. Each of the sustain electrode pairs 14 and 16 has a relatively wide width and transparent electrodes 14A and 16A made of transparent electrode material (ITO) for transmitting visible light, and a relatively narrow width and transparent electrodes 14A and 16A. In order to compensate for the resistive components of the metal electrodes 14B and 16B. The sustain electrode pairs 14 and 16 are composed of scan / sustain electrodes and sustain electrodes. The scan signal for panel scanning and the sustain signal for discharging sustain are mainly supplied to the scan / hold electrode 14, and the sustain signal is mainly supplied to the sustain electrode 16. Charges accumulate in the upper dielectric layer 18 and the lower dielectric layer 24. The protective film 20 prevents damage to the upper dielectric layer 18 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 20, magnesium oxide (MgO) is usually used. The address electrode 22 is formed to cross the sustain electrode pairs 14 and 16. The address electrode 22 is supplied with a data signal for selecting cells to be displayed. The partition wall 26 is formed in parallel with the address electrode 22 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells. The phosphor layer 28 is applied to the surfaces of the lower dielectric layer 24 and the partition wall 26 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

The PDP cell of this structure is selected by the counter discharge between the address electrode 22 and the scan / hold electrode 14, and then maintains the discharge by the surface discharge between the sustain electrode pairs 14 and 16. In the PDP cell, the fluorescent substance 28 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted outside the cell. As a result, the PDP having cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the cell, that is, the number of sustain discharges, according to the video data.

The AC surface discharge type PDP is driven by being divided into a plurality of subfields to express the gray level of the image. In each subfield period, gray scale display is performed by performing light emission in a number of times proportional to the weight of video data. do. For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell 11 is divided into eight subfields. It is divided into (SF1 to SF8). Each subfield SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that discharge is maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally assigned to each subfield period.

FIG. 3 is a driving waveform diagram for driving the PDP shown in FIG. 1 during one subfield period, in which Y, Z, and X are scan / sustain electrodes 14, sustain electrodes 16, and address electrodes 22, respectively. The drive waveform supplied to each is shown.

In the reset period RPD, the reset pulse RP is supplied to the scan / hold electrode 14. The reset pulse RP has a form of ramp wave in which the voltage increases when set-up and the voltage decreases when set-down. During setup, a reset discharge is generated between the scan / hold electrode 14 and the sustain electrode 16 to form wall charges in the upper dielectric layer 18. Subsequently, unnecessary charged particles are partially erased by the decreasing voltage during set down, and the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, the positive DC voltage Vs is supplied to the sustain electrode 16 in the set-down period of the reset pulse RP. The reset pulse RP is supplied in a gradually decreasing form to the positive DC voltage Vs so that the scan / hold electrode 14 is relatively negative to the sustain electrode 16 during set down. This reduces the wall charges generated during the setup period, i.e. by inverting the polarity. In this way, the reset discharge is generated by the supply of the reset pulse RP, and the wall charges necessary for the address discharge are formed in the cells of all the screens.

In the address period APD, the scan pulse SP is supplied to the scan / sustain electrode 14 and the data pulse DP is supplied to the address electrode 22 to generate an address discharge. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

The triggering pulse TP is supplied to the scan / hold electrode 14 at the beginning of the sustain period SPD to start the sustain discharge in the discharge cells 11 in which wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy are alternately supplied to the sustain electrode 16 and the scan / sustain electrode 14 to maintain the sustain discharge during the sustain period SPD.

The erase period EPD supplies the erase pulse EP to the sustain electrode 16 after the sustain period SPD to stop the discharge that was held. In this case, the erasing pulse EP has a lamp wave shape in which the light emission size is small, and has a short pulse width of about 1 ms for erasing the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

Such a three-electrode PDP should be operated without any abnormality, but erroneous discharge is generated in the process of displaying gradation at a low temperature substantially below 0 ° C.

Typically, the capacitance is given by the following equation.

Here, C is the capacitance, ε is the dielectric constant, A is the area of the electrode caused by the discharge, d is the distance between the electrodes causing the discharge.

As given in Equation 1, the capacitance depends on the values of ε, A, d. Since the area of the electrode and the distance between the electrodes are fixed constants, the change in capacitance is affected by ε. Therefore, the change in capacitance as the temperature changes means that ε changes. Accordingly, misdischarge at low temperature is generated as ε changes.

In detail, as shown in FIG. 4A, an opposite discharge occurs between the scan / sustain electrode 14 and the address electrode 22 during the address discharge period, and the scan / hold electrode during the sustain discharge period as shown in FIG. 4B. A sustain discharge occurs between the 14 and the sustain electrode 16. Here, as shown in FIG. 5, the sustain discharge area between the scan / hold electrode 14 and the sustain electrode 16 is about 10 times larger than the discharge area between the scan / hold electrode 14 and the address electrode 22. Big. Since the sustain discharge area is relatively larger than the address discharge area, the capacitance during the sustain discharge period is greatly influenced by the sustain discharge area regardless of?. On the other hand, since the address discharge area is relatively smaller than the sustain discharge area, the capacitance in the address discharge period depends on? Rather than the discharge area.

In the case of sustain discharge, as shown in FIG. 6A, it can be seen that the change in the amount of charge according to the voltage at room temperature and low temperature is almost similar. In the sustain discharge, the capacitance is dependent on the sustain discharge area irrespective of [epsilon], so that the capacitance is hardly changed with temperature change as shown in FIG. 6B. At this time, the current decreases by about 2 to 3% at low temperatures compared to room temperature, but it can be seen that erroneous discharge hardly occurs during maintenance discharge. Here, normal temperature is 21.5 degreeC, and low temperature is -10--5 degreeC.

However, in the case of the address discharge, as shown in FIG. 7A, it can be seen that the charge amount according to the voltage is different at room temperature and low temperature. In the address discharge, since the capacitance is dependent on ε, as shown in FIG. 7B, the capacitance changes significantly with temperature. Accordingly, the current is reduced by about 23% at low temperatures compared to room temperature, and there is a problem in that mis-discharge occurs during the low-temperature maintenance discharge period.

Accordingly, it is an object of the present invention to provide a plasma display panel and a driving method thereof capable of minimizing the occurrence of false discharge.

1 is a perspective view showing a discharge cell of a conventional three-electrode AC surface discharge PDP.

FIG. 2 is a sectional view of the PDP shown in FIG. 1. FIG.

3 is a driving waveform diagram of the discharge cell shown in FIG.

4A and 4B are sectional views showing the address discharge and the sustain discharge of the PDP shown in FIG.

FIG. 5 is a diagram comparing discharge areas of the address discharge and sustain discharge shown in FIG. 4; FIG.

6A and 6B are graphs showing changes in voltage versus capacitance in sustain discharge according to temperature change.

7A and 7B are graphs showing a change in voltage vs. capacitance in an address discharge according to temperature change.

8 is a cross-sectional view illustrating a PDP according to an embodiment of the present invention.

9 is a plan view of the PDP shown in FIG. 8;

10 is a cross-sectional view illustrating a PDP according to another embodiment of the present invention.

FIG. 11 is a plan view of the PDP shown in FIG. 10; FIG.

FIG. 12 is a drive waveform diagram of the PDP shown in FIG. 8; FIG.

<Description of Symbols for Main Parts of Drawings>

10, 40: upper substrate 12, 42: lower substrate

14, 44 scan / sustain electrode 16, 46: sustain electrode

18, 48: upper dielectric layer 20, 50: protective film

22, 52, 60: address electrode 24, 54: lower dielectric layer

26, 56: partition 28: phosphor layer

In order to achieve the above object, the plasma display panel according to the present invention is a scan / sustain electrode and the sustain electrode formed side by side on the first substrate for the sustain discharge, and causing the address discharge with the scan / sustain electrode and the second substrate And an address electrode formed to be orthogonal to and formed to have an electrode width wider than that of the other portions intersecting the scan / hold electrode.

In the method of driving a plasma display panel according to the present invention, a plasma display is driven by being divided into a reset period for initializing a plurality of discharge cells, an address period for selecting the discharge cells, and a sustain period for maintaining the discharge of the selected discharge cells. The panel includes shifting at least one of the driving voltage of the reset period and the driving voltage of the address period higher than a predetermined voltage level.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 12.

8 is a cross-sectional view illustrating a PDP according to an embodiment of the present invention, and FIG. 9 is a plan view illustrating the PDP shown in FIG. 8.

8 and 9, the PDP according to the present invention is formed such that the width of the address electrode 52 at the portion intersecting the scan / sustain electrode 44 protrudes.

An upper plate having the sustain electrode pairs 44 and 46, the upper dielectric layer 48, and the passivation layer 50 sequentially formed on the upper substrate 40, and the address electrode 52 sequentially formed on the lower substrate 42. ), A lower plate having a lower dielectric layer 54, a partition wall 56, and a phosphor layer (not shown). The upper substrate 40 and the lower substrate 42 are spaced apart in parallel by the partition wall 56. Each of the sustain electrode pairs 44 and 46 has a relatively wide width and transparent electrodes 44A and 46A made of transparent electrode material (ITO) for transmitting visible light, and a relatively narrow width and transparent electrodes 44A and 46A. In order to compensate for the resistive components of the metal electrodes 44B and 46B. The sustain electrode pairs 44 and 46 are composed of scan / sustain electrodes and sustain electrodes. The scan signal for panel scanning and the sustain signal for discharge sustaining are mainly supplied to the scan / hold electrode 44, and the sustain signal is mainly supplied to the sustain electrode 46. Charges are accumulated in the upper dielectric layer 48 and the lower dielectric layer 54. The passivation layer 50 prevents damage to the upper dielectric layer 48 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 50, magnesium oxide (MgO) is usually used. The address electrode 52 is formed to cross the sustain electrode pairs 44 and 46. The address electrode 52 is supplied with a data signal for selecting cells to be displayed. The address electrode 52 is formed such that the width of the portion of the sustain electrode pairs 44 and 46 that intersects the scan / sustain electrode 44 is about 20 μm wide. As the area of the address electrode 52 increases, the discharge area between the scan / hold electrode 44 and the address electrode 52 increases during address discharge compared to the conventional one, and thus the effect of ε, which has a significant effect on capacitance, is reduced. Will be. Accordingly, since the value of the capacitance becomes almost constant according to the temperature change, occurrence of erroneous discharge is reduced at low temperatures. In addition, as the discharge area of the address discharge is increased, the miss of selective writing is also significantly reduced.

The partition wall 56 is formed in parallel with the address electrode 52 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells. The phosphor layer is applied to the surfaces of the lower dielectric layer 54 and the partition wall 56 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

10 is a cross-sectional view illustrating a PDP according to another embodiment of the present invention, and FIG. 11 is a plan view illustrating the PDP illustrated in FIG. 10.

Referring to FIGS. 10 and 11, the PDP according to the present invention is formed such that the width of the address electrode 60 protrudes from the gap between the scan / sustain electrode 44 and the sustain electrode pairs 44 and 46. .

An upper plate having the sustain electrode pairs 44 and 46, the upper dielectric layer 48, and the passivation layer 50 sequentially formed on the upper substrate 40, and the address electrode 52 sequentially formed on the lower substrate 42. ), A lower plate having a lower dielectric layer 54, a partition wall 56, and a phosphor layer (not shown). The upper substrate 40 and the lower substrate 42 are spaced apart in parallel by the partition wall 56. Each of the sustain electrode pairs 44 and 46 has a relatively wide width and transparent electrodes 44A and 46A made of transparent electrode material (ITO) for transmitting visible light, and a relatively narrow width and transparent electrodes 44A and 46A. In order to compensate for the resistive components of the metal electrodes 44B and 46B. The sustain electrode pairs 44 and 46 are composed of scan / sustain electrodes and sustain electrodes. The scan signal for panel scanning and the sustain signal for discharge sustaining are mainly supplied to the scan / hold electrode 44, and the sustain signal is mainly supplied to the sustain electrode 46. Charges are accumulated in the upper dielectric layer 48 and the lower dielectric layer 54. The passivation layer 50 prevents damage to the upper dielectric layer 48 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 50, magnesium oxide (MgO) is usually used. The address electrode 60 is formed to cross the sustain electrode pairs 44 and 46. The address electrode 60 is supplied with a data signal for selecting cells to be displayed. The address electrode 60 is formed such that the width of the portion of the sustain electrode pairs 44 and 46 that intersects the gap between the scan / sustain electrode 44 and the sustain electrode pairs 44 and 46 is about 20 μm wide. As the area of the address electrode 60 increases, the discharge area between the scan / hold electrode 44 and the address electrode 60 increases during the address discharge according to the present invention as compared with the conventional one, thus having a significant effect on the capacitance. The effect of is reduced. Accordingly, since the value of the capacitance becomes almost constant according to the temperature change, occurrence of erroneous discharge is reduced at low temperatures.

The partition wall 56 is formed in parallel with the address electrode 60 to prevent ultraviolet rays generated by the discharge from leaking to the adjacent cells. The phosphor layer is applied to the surfaces of the lower dielectric layer 54 and the partition wall 56 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

FIG. 12 is a driving waveform diagram for driving the PDP according to the present invention shown in FIG. 8 during one subfield period, wherein Y, Z, and X are scan / sustain electrodes 44, sustain electrodes 46, and addresses. The drive waveform supplied to each of the electrodes 52 is shown.

In the reset period RPD, the reset pulse RP is supplied to the scan / sustain electrode 44. The reset pulse RP has a ramp ramp waveform in which the voltage increases when set-up, and a ramp ramp waveform in which the voltage decreases during set-down. During setup, a reset discharge is generated between the scan / hold electrode 44 and the sustain electrode 46 to form wall charges in the upper dielectric layer 48. Subsequently, unnecessary charged particles are partially erased by the decreasing voltage during set down, and the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, a positive DC voltage Vs is supplied to the sustain electrode 46 in the set down period of the reset pulse RP. Since the reset pulse RP is supplied in a slowly decreasing form with respect to the positive DC voltage Vs, the scan / hold electrode 44 is negatively negative relative to the sustain electrode 46 during set down. This reduces the wall charges generated during the setup period, i.e. by inverting the polarity. The reset pulse RP of the falling ramp waveform during set down is made larger than the potential of the scaffold SP during the address discharge period. As a result, a large amount of wall charges are accumulated around the scan / sustain electrode 44 and a large discharge voltage difference between the scan / sustain electrode 44 and the address electrode 52 that causes the next address discharge increases, thereby increasing the amount of discharge in the discharge space. Allow charged particles to be produced. Therefore, it is possible to minimize the erroneous discharge generated in the address period APD under the influence of [epsilon].

On the other hand, in the address period APD, the scan pulse SP is supplied to the scan / sustain electrode 44 and the data pulse DP is supplied to the address electrode 52 to generate address discharge. Here, the data pulse DP of a higher voltage than the conventional one is supplied to the address electrode 52 to increase the discharge voltage difference between the scan / sustain electrode 44 and the address electrode 52 so that a large number of charged particles in the discharge space can be obtained. To be created. Therefore, it is possible to minimize the erroneous discharge generated in the address period APD under the influence of [epsilon]. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

In addition, during the address period APD, the DC voltage Vs of a higher voltage than the conventional one is supplied to the sustain electrode 44. This causes discharge between the scan / sustain electrode 44 and the sustain electrode 44 to help address discharge between the scan / sustain electrode 44 and the address electrode 52 so that many charged particles are generated in the discharge space. do. Accordingly, it is possible to minimize erroneous discharge generated in the address period APD under the influence of ε.

The triggering pulse TP is supplied to the scan / sustain electrode 44 at the beginning of the sustain period SPD to start the sustain discharge in the discharge cells in which the wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy are alternately supplied to the sustain electrode 46 and the scan / sustain electrode 44 to maintain the sustain discharge during the sustain period SPD.

The erase period EPD supplies the erase pulse EP to the sustain electrode 46 after the sustain period SPD to stop the discharge that was held. In this case, the erasing pulse EP has a lamp wave shape in which the light emission size is small, and has a short pulse width of about 1 ms for erasing the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

As described above, the plasma display panel according to the present invention has a wide width of the address electrode at the portion intersecting the scan / sustain electrode, thereby minimizing the occurrence of erroneous discharge due to temperature change during address discharge. Furthermore, the plasma display panel according to the present invention will significantly reduce the miss of selective writing by increasing the discharge area of the address discharge.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A scan / hold electrode and a sustain electrode formed side by side on the first substrate for sustain discharge; And an address electrode formed at orthogonal to the second substrate and causing an address discharge with the scan / sustain electrode, wherein an electrode having an electrode width wider than that of other portions is formed at an intersection with the scan / hold electrode. . The method of claim 1, And an electrode width of the address electrode intersecting the scan / sustain electrode is about 20 [mu] m wider than other portions. The method of claim 1, And a wide electrode width of the address electrode crossing the gap between the scan / sustain electrode and the sustain electrode. The method of claim 3, wherein And an electrode width of the address electrode crossing the gap between the scan / sustain electrode and the sustain electrode is about 20 μm wider than other portions. A plasma display panel which is driven by being divided into a reset period for initializing a plurality of discharge cells, an address period for selecting the discharge cells, and a sustain period for maintaining discharge of the selected discharge cells. And shifting at least one of the driving voltage of the reset period and the driving voltage of the address period higher than a predetermined voltage level. The method of claim 5, Sequentially supplying a ramp ramp waveform and a ramp ramp waveform to the scan / hold electrode during the reset period; Supplying a scan pulse to the scan / sustain electrode during the address period, supplying a data pulse to the address electrode and supplying a positive DC voltage to the sustain electrode; And alternately supplying a sustain pulse to the scan / sustain electrode and the sustain electrode during the sustain period and supplying an erase lamp signal to at least one of the scan / sustain electrode and the sustain electrode to cancel discharge. A driving method of a plasma display panel, characterized in that. The method of claim 5, And the potential of the falling ramp wave is greater than the potential of the scan pulse. The method of claim 5, And a positive DC voltage is supplied to the sustain electrode during the reset period. The method of claim 8, And the positive DC voltage supplied in said address period is greater than the positive DC voltage supplied in said reset period.