KR20030003352A - Capacitor in semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to improve a characteristic of a leakage current by easily forming a dense thin film having a high dielectric constant. CONSTITUTION: A Ru layer(20) of 10-1000 angstrom in thickness is deposited on a predetermined underlying layer. A WNx layer(21) of 10-1000 angstrom in thickness is deposited on the Ru layer to form a conductive layer for a lower electrode. A WO3 dielectric thin film(22) is formed on the conductive layer for the lower electrode. A conductive layer for an upper electrode(23) is formed on the WO3 dielectric thin film. The WO3 dielectric thin film is 10-500 angstrom in thickness.

Description

Capacitor in semiconductor device and method for fabricating the same

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the degree of integration of DRAM (Dynamic Random Access Memory) among semiconductor memory devices increases, the area of a memory cell storing one bit, which is a basic unit of memory information, decreases. However, it is not possible to reduce the area of the capacitor in proportion to the shrinking of the cell, which is necessary for sensing signal margin, sensing speed, and durability against soft errors caused by α-particles. This is because a certain charging capacity is required per unit cell. Therefore, the method for maintaining the capacity of the memory capacitor in a limited cell area more than the appropriate value is the first method of reducing the thickness of the dielectric, such as C = ε As / d (ε: dielectric constant, As: surface area, d: dielectric thickness), The second method is to increase the effective area of the capacitor, and the third method is to use materials with high dielectric constant.

Among them, the first method is to minimize the distance (d) between the electrodes by thinning the dielectric, and the second method is a simple stack structure, a concave structure, a cylinder structure, A method of increasing the effective surface area of a capacitor using a three-dimensional structure such as a multilayer pin structure is used.

However, there is a limit in increasing the capacity of a capacitor by manufacturing the capacitor electrode in a complicated three-dimensional shape. In other words, if the height of the capacitor electrode is too high, the surface step becomes severe and irregularities are formed on the surface of the semiconductor substrate. As a result, when forming and processing a thin film on an uneven surface with irregularities, it is not only difficult to process the micropattern, but also the thickness of the thin film deposited on the flat top surface and the thin film deposited on the recess is different. Deteriorate characteristics. In severe cases, disconnection of the thin film occurs at the stepped edges, which adversely affects the reliability of the semiconductor device. In addition, since a thick insulating film must be formed to planarize the memory surface, the depth of the contact hole becomes deep, which makes it difficult to form the contact hole and fill the conductive material into the contact hole.

In the third method, a dielectric film used in a conventional capacitor was almost mainstream of a thin film of NO- or Ni-ride-Oxide (NOO) using Si ₃ N ₄ having a dielectric constant almost doubled from SiO ₂ . However, because SiO ₂ , Nitride-Oxide (NO), and Oxide-Nitride-Oxide (ONO) thin films have a low dielectric constant, there is no room for high capacitance even if the thickness of the dielectric thin film is reduced or the surface area is increased. The situation led to the introduction of new materials.

After all, in high-integration DRAM, materials that replace conventional dielectric thin films are (Ba, Sr) TiO ₃ (hereinafter referred to as BST), (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), (Pb, La) (Zr, Ti Dielectric thin films such as O ₃ (hereinafter referred to as PLZT), SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as SBT), TaON, and Ta ₂ O ₅ have been introduced.

In the capacitor using the high dielectric film, it is difficult to use polysilicon as an electrode material. Therefore, a noble metal or an oxide thereof, such as Pt, Ir, Ru, RuO ₂ , IrO _2, etc., is used instead of polysilicon. Or a conductive compound such as TiN. That is, in the case of tantalum oxide (Ta2O5), a MIS (Metal / Insulator / Silicon) structure or a MIM (Metal / Insulator / Metal) structure should be introduced, and in the case of using BST, a MIM (Metal / Insulator / Metal) structure is introduced. shall. As described above, when the capacitor electrode is formed of metal, it is possible to prevent the reaction between the metal and the polysilicon used as the conductive plug or the substrate silicon, to secure ohmic contact characteristics, and to diffuse the oxygen used as the source when depositing the dielectric film. Barrier layer (barrier layer) is essentially formed to prevent. As the barrier layer, TiN, TaN, TiSiN, TaAlN, or the like is used.

Here, currently used Ta ₂ O ₅ , Al ₂ O ₅ and the like has a dielectric constant of about 8 to 50, and is not suitable for applying to more integrated semiconductor devices, and the high dielectric constant (Ba, Sr) TiO _3, etc. is difficult to control the composition. It is difficult and has many problems to apply.

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor and a method for manufacturing a semiconductor device in which a high dielectric constant and easy formation of a compact thin film have improved leakage current characteristics.

1 to 6 are process cross-sectional views showing a manufacturing method of a capacitor according to a preferred embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing

16: polysilicon plug 17: TiSi

18: TiN 19: interlayer insulating layer

20: WNx21: Ru

22: WO ₃ 23: upper electrode

In order to achieve the above object, the capacitor of the semiconductor device of the present invention is a lower electrode; A WO ₃ dielectric thin film provided on the lower electrode; And an upper electrode provided on the WO ₃ dielectric thin film.

In addition, the capacitor manufacturing method of the semiconductor device of the present invention comprises the steps of forming a conductive film for the lower electrode on a predetermined lower layer; Forming a WO ₃ dielectric thin film on the conductive film for the lower electrode; And forming a conductive film for the upper electrode on the WO ₃ dielectric thin film.

In forming the capacitor of the semiconductor device, the present invention uses a double structure of the Ru lower electrode and the WNx thereon, and subsequently a high-density WO3 (dielectric constant of 100 to 300) to form a dense thin film using CVD or ALD. It is a method of forming and improving the electric charge of a semiconductor element. In other words, it is a method of improving the capacitor charge of a semiconductor device by using a Ru bottom electrode capable of a three-dimensional structure as a capacitor and a double structure of WNx thereon, and subsequently forming a dense thin film using WO ₃ using CVD or ALD. WO ₃ thin film has a high dielectric constant of 100 ~ 300, easy to form a thin film is easy to control the composition, the film can be formed by using the CVD or ALD method can improve the film leakage characteristics.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1 to 6 are process cross-sectional views showing a preferred embodiment according to the present invention.

First, referring to FIG. 1, a first interlayer insulating layer 13, a bit line pattern 14, and a first interlayer may be formed on a substrate 10 having a predetermined process including a predetermined separator 11 and a gate pattern 12. It is formed by depositing the two interlayer insulating layer 15. The first interlayer insulating layer 13 and the second interlayer insulating layer 14 are etched to form a contact hole, and a polysilicon plug 16 recessed in the contact hole is formed.

Next, referring to FIG. 2, Ti-silicide (TiSi) 17 is formed on the recessed polysilicon 16 as an adhesive layer for ohmic contact.

Next, referring to FIG. 3, TiN 18 is formed by depositing a diffusion barrier layer on the adhesive layer.

Subsequently, referring to FIG. 4, the interlayer insulating layer 19 may include a plasma-enhanced tetra ethyl orthosilicate (PE-TEOS), high density plasma (HDP) oxide, boro-phospho-silicate glass (BPSG), or phospho silicate glass (PSG). To form.

Next, referring to FIG. 5, the interlayer insulating layer 19 is etched to form a hole, and a lower electrode is formed to have a Ru (21) / WN (20) structure inside the hole. At this time, it is insulated from the neighboring capacitor electrode using etch back or chemical mechanical polishing.

Wherein the thickness of the Ru thin film 20 is formed in the range of 10 ~ 1000Å, WNx thin film 21 is also in the range of 10 ~ 1000Å, chemical vapor deposition (Chemical vapor deposition), or plasma enhanced chemical vapor deposition (Plasma enhanced) Deposition is carried out using chemical vapor deposition or atomic layer deposition.

Here, when the deposition of the WNx 21 using chemical vapor deposition, the reaction source is one selected from O 2, N 2 O, N 2, Ar, Ne, Kr, Xe or He, or a mixed gas thereof.

Subsequently, WO ₃ (22) (ε _r = 100 to 300) as a dielectric is deposited by forming a dense thin film at a temperature in the range of 200 to 700 ° C. in the range of 10 to 500 kPa by chemical vapor deposition or atomic layer deposition. Here, chemical vapor deposition uses O ₂ , N ₂ O, N ₂ , Ar, Ne, Kr, Xe, or He as a reaction source in the formation of the thin film of WO ₃ (22), or a mixed gas thereof, and atomic layer deposition. When using the method, a purge gas may be N ₂ , O ₂ , Ar, Ne, Kr or He, or a mixture thereof.

Next, referring to FIG. 6, the capacitor is formed by depositing the Pt, Ru, TiN, W, Ir, IrOx, or RuOx in the range of 10 to 1000 kW as the upper electrode 23.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

In the present invention, when forming a capacitor of a semiconductor device, by forming a lower electrode of double Ru / WNx and forming a dense thin film dielectric with WO ₃ having a high dielectric constant (ε _r = 100 to 300), a stable semiconductor device can be produced. Can be.

Claims (9)

Lower electrode; A WO ₃ dielectric thin film provided on the lower electrode; And And a top electrode provided on the WO ₃ dielectric thin film. The method of claim 1, The lower electrode is a capacitor of the semiconductor device, characterized in that it comprises a Ru film. The method of claim 2, And the lower electrode includes the Ru film and a WNx film provided thereon. Forming a conductive film for the lower electrode on the predetermined lower layer; Forming a WO ₃ dielectric thin film on the conductive film for the lower electrode; And Forming a conductive film for the upper electrode on the WO ₃ dielectric thin film capacitor manufacturing method of a semiconductor device. The method of claim 4, wherein Forming the conductive film for the lower electrode, Depositing a Ru film having a thickness of 10 to 1000 Å on the lower layer; And depositing a WNx film having a thickness of 10 to 1000 Å on the Ru film. The method according to claim 4 or 5, The WO ₃ film is a capacitor manufacturing method of a semiconductor device, characterized in that the thickness of 10 ~ 500Å. The method of claim 4, wherein Capacitor manufacturing method of the semiconductor device characterized in that the upper extremity of the WO ₃ film dielectric chemical vapor deposition or atomic layer deposition deposited using any of them. The method of claim 7, wherein When depositing the WO3 dielectric thin film by the chemical vapor deposition method, at least one selected from among O2, N2O, N2, Ar, Ne, Kr, Xe, He as a reaction source capacitor manufacturing method of a semiconductor device . The method of claim 8, The WO3 dielectric film is a capacitor manufacturing method of the semiconductor device, characterized in that for depositing at a temperature of 200 ~ 700 ℃.