KR20030003207A - Memory cell for the memory device and its fabricating method - Google Patents

Abstract

PURPOSE: A memory cell for memory device and its fabricating method are provided to solve difficult problems of a DRAM fabricating process by reducing the height of a capacitor, simultaneously and access a cell like a NOR type in the data storage function of page unit that NAND type flash memory is a disadvantage and then being capable of reducing unit cell area and improving reliability than the NOR type. CONSTITUTION: A memory cell includes a semiconductor substrate(100) of a handle wafer, a semiconductor device layer(10b) and a wall layer(10a) for protecting its device, and an isolation region(11b) having an active and field region on the device(10b). A drain and source electrode(30a,30b) are formed to connect a drain/source region(12a,12b) through the fourth insulating layer(20). A tunneling capacitor(40) comprises a bottom electrode(40a), a tunneling oxide(40b), a floating electrode(40c), an interlayer dielectric(40d), and a top electrode(40e).

Description

Cell structure for a memory semiconductor device and a fabrication method therefor {Memory cell for the memory device and its fabricating method}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, a cell operation by replacing a capacitor used in a conventional DRAM cell structure with a tunneling capacitor structure currently applied to a flash memory. The present invention relates to a semiconductor device and a manufacturing method thereof for a new memory having the same advantages as DRAM but capable of permanently preserving data.

As the memory size of conventional memory becomes smaller as DRAM, the height of a capacitor having a stack structure as shown in 40-1 of FIG. 1 increases gradually to maintain a capacity of 30fF to 25fF per unit capacitor. The height of is about 1.8μm. This height is going to be higher as the allowable unit area is smaller, which makes the process increasingly difficult. In addition, in order to maintain the stored charge in the conventional DRAM operation, a constant voltage must always be applied around the capacitor, and the stored data is periodically refreshed to solve the problem of data loss due to loss of stored charge. Should give. This is a chronic problem of DRAM, which always consumes more power than nonvolatile memory.

On the other hand, in the case of NAND type in flash memory, there is an advantage that the degree of integration can be increased. However, as the operation voltage becomes smaller due to a smaller operation voltage, the data of the non-selected memory cell is interfered by interfering with the next cell that is not selected during operation. Has a vulnerability that is lost. In addition, as the gate structure of the unit cell gradually increases in height, process limitations are also given. In addition, NOR type uses hot-electron to input data compared to NAND type. In this case, data input time is longer because data is input in some limited areas and weak reliability that damages gate oxide caused by high-energy electrons. . Moreover, as a structural problem, there is a further inferior limitation in miniaturization by requiring an extra gate area. That is, the gate length is always longer than that of DRAM or NAND Flash memory due to the basic structure problem, and thus the limit of integration is greater than these. The structure of the unit cell is not symmetrical, and basically due to the longer gate length problem, the center of the process is shifted toward minimizing the size of the contact.

Referring to FIG. 1, in the structure of a DRAM according to a conventional embodiment, cell regions 10a and b are formed in a surface layer of a semiconductor substrate 100, and drains 12a and 12b are formed in the device layer region 10b. The source 12b region is formed.

In addition, a layer of interlayer insulating film 20 is formed on the entire surface of the semiconductor substrate 100, and is electrically connected to the drain region 12a and the source region 12b through the interlayer insulating film 20. The drain electrode 30a and the source electrode 30b are formed so that they may be connected.

Next, another interlayer insulating film 20a is formed on the interlayer insulating film 20 including the drain electrode 30a and the source electrode 30b, and penetrates the interlayer insulating film 20a to be electrically connected to the source region 12b. The lower electrode is connected to the formed contact plug 30b so as to be connected.

The tunneling capacitor 40 is formed on the lower electrode 40a of the capacitor.

In this case, the capacitor 40-1 includes a capacitor lower electrode 40a and an oxide 40b, and a capacitor upper electrode 40e.

Then, another interlayer insulating film 20b is formed on the capacitor upper electrode 40e.

The plate 50 is formed to penetrate the interlayer insulating film 40e and to be electrically connected to the capacitor upper electrode 40e.

As described above, the conventional semiconductor memory device has a problem that the height of the capacitor 40-1 is gradually increased, which makes it difficult to implement a highly integrated memory.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems. Basically, it is a non-volatile memory in operation and at the same time, it selects a unit cell to freely input or output data and facilitate miniaturization, and at the same time, the structure of the capacitor is placed on the gator. It can solve the problem of reducing the size of the cell by not only being limited but also utilizing the entire cell area. The margin in this area also reduces inter-cell interference and facilitates driving at lower voltages. In addition, since the direct tunnel or Fowler-Nordheim method of inputting or outputting charge through the entire area of the lower oxide (40a in FIG. 6H) is used, the reliability is higher than that of the hot-electron using the local area. can do. In conclusion, the memory of the present invention aims to develop a new memory that overcomes the disadvantages of the conventional memory and overcomes limitations of high reliability, low power consumption, high speed operation, and process.

1 is a cross-sectional view illustrating a structure of a semiconductor memory device according to a conventional embodiment;

2 is an equivalent circuit of a semiconductor memory device according to a conventional embodiment;

3 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention;

4 is a cross-sectional view taken along line AA ′ of FIG. 3;

5 is a cross-sectional view taken along line BB ′ of FIG. 3;

6A through 6I are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

7 is an equivalent circuit of a unit cell according to an embodiment of the present invention;

8 is a graph illustrating a charge characteristic curve of a unit cell according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100: semiconductor substrates 10a and b are device layers and well regions

11a and b are device isolation regions 12a are drain regions

12b is a source region 13 is a gate oxide film

14 Gate electrode 20, 20a, 20b interlayer insulating film

30a drain electrode 30b source electrode contact plug

40, Tunneling capacitor 40-1 Capacitor 40a Lower electrode 40b Tunneling oxide 40c Floating electrode 40d Interlayer oxide 40e Upper electrode 50 Control plate electrode

According to the present invention for achieving the above object, a method of manufacturing a semiconductor memory device comprises the steps of forming a semiconductor device layer on a semiconductor substrate; Forming a first insulating film comprising an oxide film and a nitride film formed on the device layer; Etching the first insulating film to isolate the devices from each other so as to expose regions used for device isolation; Forming an oxide film for device isolation in the device layer exposed for device isolation; Removing the formed first insulating layer for etching to expose the semiconductor surface, which is an element layer, and an oxide layer for isolating the device at the same time; Forming a second insulating film for the gate oxide film on the surface of the oxide layer for isolation of the device including the semiconductor device layer; Forming a first gate metal for the gate control on the formed gate oxide film; Forming a third oxide used for gate formation on the formed first gate metal; The third oxide is etched to form a gate formed on the semiconductor device layer and may serve as a gate, and the surface of the semiconductor device layer in a region other than the third insulator is exposed by using the etched third oxide. Etching; Removing residual third oxide used as an etch mask during etching after the gate is physically formed; Forming a fourth insulating film on the semiconductor surface including the gate and the oxide for isolating the semiconductor device; Etching a fourth insulating film to expose a portion of the semiconductor device layer to form a drain and a source, respectively; Implanting predetermined impurity ions into the drain contact hole and the source contact hole to form a drain region and a source region in the device layer, respectively; The device layer between the drain region and the source region is used as a channel region, and simultaneously forms electrodes in the drain and the source to be electrically connected to the drain region through the drain contact hole so as to be electrically connected to an external circuit. Forming a second metal line for; Forming a fifth insulating film on the exposed fourth insulating film including the formed second metal line; Etching the fifth insulating layer to form a lower electrode of a via plug and tunneling capacitor to be electrically connected to a plug formed in a source contact hole; Forming a tunneling capacitor on the formed lower electrode.

In a preferred embodiment of the method, the device layer is either an n-type semiconductor or a p-type semiconductor.

In a preferred embodiment of the present invention, the semiconductor substrate and the device layer is any one of a silicon and GaAs film, and a semiconductor film and a conductive film of the same germanium.

In a preferred embodiment of this method, the predetermined impurity ions are any one of As, P, B and BF2.

In a preferred embodiment of the method, the drain and source electrode materials are any one of tungsten (W) and aluminum (Al), polysilicon (Poly-Si), and platinum (Pt), respectively.

In a preferred embodiment of the method, the contact plug makes ohmic contact with the drain and source region.

In a preferred embodiment of the method, the tunneling capacitor makes ohmic contact with the source region via the contact plug.

In a preferred embodiment of the method, the forming of the tunneling capacitor may include a tunneling capacitor lower electrode film, an electron passing oxide film, a floating electrode, an interlayer insulating film, and a tunneling capacitor upper electrode on the fifth insulating layer including the source electrode. Sequentially forming the films; Forming an electrode pattern by etching the tunneling capacitor lower electrode film, the tunneling oxide film for electron passing, the floating electrode, the interlayer insulating film, and the tunneling capacitor upper electrode film.

In a preferred embodiment of the method, the electron passing oxide film is a film formed of at least one of SiO 2, SiON, TiO 2, and Al 2 O 3.

In a preferred embodiment of the method, the floating electrode is a film formed of one of tungsten (W), polysilicon (Poly-Si), aluminum (Al), platinum (Pt), and copper (Cu).

In a preferred embodiment of this method, the interlayer insulating film is a film formed of one of oxide film and nitride film (SiO 2 / Si 3 N 4), oxide film and alumina (SiO 2 / Al 2 O 3), BST, PZT, and BSTO.

In a preferred embodiment of the method, the forming of the tunneling capacitor further includes forming a passivation layer on the tunneling capacitor upper electrode layer and on the side surface.

In a preferred embodiment of the method, the method of manufacturing a semiconductor memory device comprises: forming a sixth insulating layer on a fifth insulating layer including the tunneling capacitor; Forming a via such that a top surface of the tunneling capacitor is exposed; Forming a control plate line to be electrically connected with the tunneling capacitor through the via.

(action)

The semiconductor memory device and other manufacturing methods used in the present invention enable the operation of the semiconductor memory device at a low voltage and at the same time preserve the stored data permanently, thereby structurally preventing power consumption and controlling the operation of each cell. . This enables memory cell arrays having a 1T / 1C structure.

(Example)

4 to 5, a novel semiconductor memory device and a method of fabricating the same according to an embodiment of the present invention connect the tunneling capacitor of the invention to the source of the MOS transistor, so that each of the DRAMs, like the conventional DRAM, can be connected to each other. At the same time, the cells can be freely accessed and data can be driven at the same lower operating voltage, which is permanently preserved, such as current flash memory.

In the following, an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6. Referring to FIG. 3, in the layout of a 1T / 1C cell according to an exemplary embodiment of the present invention, reference numeral “10a” denotes an active line (hereinafter referred to as “AL”), which represents a well region protecting a device layer. And the channel region 10b of the access transistor star, among which reference numerals 12a and 12b denote drain electrodes and source electrodes, respectively, and reference numeral 40 denotes a tunneling capacitor. In addition, reference numeral 50 denotes a control plate line (hereinafter referred to as 'CG').

4 is a cross-sectional view taken along line AA ′ of FIG. 3, and FIG. 5 is a cross-sectional view taken along line BB ′ of FIG. 3.

4 to 5, a memory cell having a 1T / 1C structure according to an embodiment of the present invention includes a semiconductor wafer 100 that is a handle wafer and a semiconductor device layer 10b. And a device isolation region 11b formed by defining an active region and a field region in the well layer 10a protecting the device layer and the device layer 10b.

In this case, B and P are injected into a silicon bulk, which is the substrate 100, to form the wells 10a and 10b in the bulk and to form the device layer 10b, wherein the device layer is (10b). Is formed to be p-type in the case of n-MOSFET, and is formed to be n-type in case of p-MOSFET.

As the substrate 100, a semiconductor film or a conductive film such as a silicon film and a GaAs film is used, and the device layer 10b is generally formed to a thickness of about 1000 mW.

The active region of the device layer 10b is used as the channel region 10b, the drain region 12a, the source region 12b, and the device isolation region 11a.

Next, it includes a drain region 12a and a source region 12b formed in the active region, but formed in the device layer 10b at a distance from each other.

At this time, the drain region 12a and the source region 12b are n-type impurity regions in the case of the n-MOSFET, and p-type impurity regions in the case of the p-MOSFET.

The semiconductor memory device may be formed such that the drain region 12a and the source region 12b are electrically connected to each other through the fourth insulating layer 20 formed on the substrate and the fourth insulating layer 20. A drain electrode 30a and a source electrode 30b are included.

In this case, the fourth insulating layer 20 is made of BPSG (BoroPhosphoSilicate Glass) or the like, and the drain electrode 30a and the source electrode 30b are made of aluminum, tungsten, polysilicon, or the like.

A contact plug 30a and a fourth insulating layer formed through the fourth insulating layer 20 including the drain electrode 12a to electrically connect the drain region 12a and the source region 12b of the device layer, respectively. And a contact plug 30b formed to penetrate 20 and electrically contact the source region 12b of the device layer.

The contact plugs 30a and 30b and the drain 12a and source 12b regions of the device layer respectively make ohmic contacts.

In this case, the fifth insulating layer 20a is formed of an insulating film such as USG or TEOS, and the contact plugs 30a and 30b are formed of a polysilicon film or a metal film.

By etching the fifth insulating layer formed on the contact plug 30c to form a via to expose the contact plug 30b of the source, the lower electrode is electrically connected to the source contact plugs 30b and 30c and the lower electrode of the tunneling capacitor. To form.

In addition, forming the tunneling capacitor 40 on the formed lower electrode.

The tunneling capacitor 40 is in ohmic contact with the source region 12a through the contact plug 30b.

The tunneling capacitor 40 includes a tunneling capacitor lower electrode 40a and a tunneling oxide film 40b, a floating electrode 40c, an interlayer insulating film 40d, and a tunneling capacitor upper electrode 40e.

In this case, in the tunneling capacitor, the tunneling oxide 40a and the interlayer insulating film 40d each apply at least one or more of SiO 2, SiON, and HfO 2 or include at least one or more of SiO 2 / Si 3 N 4, PZT, Y1, and BST.

Next, a sixth insulating layer 20b formed on the fifth insulating layer 20a including the tunneling capacitor is formed, and is electrically connected to the tunneling capacitor 20b through the fifth insulating layer 20b. The control plate metal line 50 is formed to be.

6A through 6I are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

6A to 6I will be described with reference to the cross-sectional view of FIG. 4.

Referring to FIG. 6A, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention first prepares a silicon wafer substrate 100.

In this case, the silicon wafer substrate includes a semiconductor substrate 100, a semiconductor well layer 10a, and an element layer 10b.

The device layer 10b is generally formed to a thickness of about 0.5 μm, in the case of an n-MOSFET, p-type, and in the case of a p-MOSFET.

The substrate 100 is formed of a semiconductor film or a conductive film such as a silicon film and a GaAs film.

Active and field regions are defined on the device layer 10b to form device isolation regions 11a and 11b.

At this time, the element layer 10b of the active region is used as the channel region 10c.

In this case, device isolation may use a conventional LOCOS type or a trench type. The oxide used here is HDP, which is used to fill the thermal oxide or the trench.

On the device layer 10b, a gate oxide and a gay metal for the gate cone are formed.

At this time, the gate material used is polysilicon, tungsten silicide (WSi2), which is an alloy of tungsten and silicon, or tisilicide (TiSi2), which is an alloy of titanium and silicon.

A third insulating layer 15 is formed on the gate metal for gate formation.

In FIG. 6B, the third insulator formed on the gate metal is etched to expose the gate metal, and then the gate metal is etched using the third insulator to expose the surface of the device layer.

In FIG. 6C, the fourth insulating layer 20 is etched to expose the upper surface of the device layer 10b of the active region to form the drain contact hole 30a and the source contact hole 30b. The n-type impurity ions or the p-type impurity ions 16 are implanted into the drain contact hole 30a and the source contact hole 30b.

As or P is used as the n-type impurity ion, and B or BF2 is used as the p-type impurity ion.

In FIG. 6D, a plug 30c is formed to form a metal line at the same time as the formed drain contact region, the source contact region, the drain contact hole 30a, and the source contact hole 30b. At this time, in order to condense the formed metal 30c and activate the ions implanted in the contact regions 30a and 30b, a thermal thermal annealing (RTA) or a furnace annealing process is performed to respectively form the device layer 10b. The metal line 30c is concentrated at the same time as the drain region 12a and the source region 12b are formed.

In FIG. 6E, the formed contact and metal line plug 30c forms a pattern for the metal line for electrical connection between the drain contact and the external circuit, and the contact pad for electrical connection between the source and the tunneling capacitor. do.

The contact holes 30a and 30b of the drain and source are filled with a polysilicon film or a metal film to form a contact plug 30c.

In FIG. 6F, the fifth insulator 20a is formed on the fourth insulator 20 including the metal 30c to etch the fifth insulator to electrically connect the source contact hole 30b with the via 30d. ).

The formed via 30d is formed of polysilicon and a metal film and used simultaneously as a lower electrode of the tunneling capacitor.

In FIG. 6G, the material for forming the tunneling capacitor 40 is stacked by stacking the material of the tunneling capacitor on the fifth insulator 20a including the formed via 30d.

In this case, a material such as SiO 2, HfO 2, and Al 2 O 3 is used as the tunneling oxide material, and materials such as BST, PZT, TiO 2, and SiON / Si 3 N 4 are used as the interlayer oxide material.

In FIG. 6H, the stacked tunneling capacitor 40 is etched to expose the fifth insulator 20b. That is, the material of the tunneling capacitor is etched to form the shape of the tunneling capacitor.

Finally, as shown in FIG. 6I, a sixth insulator for tunneling capacitor protection and electrical insulation is formed on the fifth insulator 20a including the formed tunneling capacitor to form the tunneling capacitor control plate line 50. As a result, a memory cell element having a 1T / 1C structure as in 6i is completed.

The sixth insulating layer is formed of an insulating film such as USG or TEOS, and the plate line 50 is formed of Al, Cu, or the like.

7 is an equivalent circuit of a unit cell according to an embodiment of the present invention.

Referring to FIG. 7, an equivalent circuit of a unit cell of a memory according to an embodiment of the present invention includes a stacking tunneling capacitor 40 having a stack structure, for example, a MOSFET and a tunneling capacitor for charge storage.

At this time, the drain of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is connected to the bit line (BL), the source is connected to the lower electrode of the capacitor and the gate is connected to the wordline (WL) like the conventional DRAM. The difference from the conventional DRAM structure in the present invention is that the tunneling capacitor control metal line (PL, 50) is in the form of a patterned line. Conventional memory is not a line, but the plate is tied together by one electrode.

Thus, the PL is connected to the upper electrode of the tunneling capacitor.

The cell operation of the 1T / 1C memory as described above is as follows. Here, as the IT, an n-MOSFET will be described as an example.

First, the standby state of the cell leaves all electrodes in the ground (L) state. BL, WL, and PL mean bitline, wordline, and plateline, respectively. Write, Read, and Erase mean data write, read, and erase, respectively. Finally, in all operating areas, the active area is always fixed to ground.

Referring to Table 1, the operation of the memory cell is performed by voltages applied to BL, WL, and PL, respectively. For example, when writing data "1" (hereinafter, referred to as 'D1'), a high voltage (H) is applied to the PL, a low voltage (L) is applied to the BL, and the gate of the access transistor is applied. Applies a high voltage (H).

On the other hand, to read the written data, the plate line PL is set to ground or low voltage (L), the high voltage (H) is applied to the gate control metal, and the low voltage (L) is applied to the BL. Is authorized. In this case, a current is generated while the electric charge that has been induced in the metal np junction formed between the source region 12b and the well region 10b is rearranged. On the other hand, when reading data, the active regions 10a and 10b are connected to ground to support driving of the cell.

Consequently, depending on the amount of charge accumulated in the nonvolatile tunneling capacitor, the charges induced in the junction capacitor composed of the metal np junction region formed between the source region 12b and the element layer 10b flow out into the BL for a moment. Current is formed and this current is sensed and operated.

In the case of data " 0 ", the current accumulated in the junction capacitor is insignificant or absent so that the current hardly flows.

8 is a graph showing a charge characteristic curve of an applied voltage of a unit cell according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the voltage versus charge characteristic curve of the unit cell according to the embodiment of the present invention maintains D1 and D0 according to the characteristics of the charge in the floating electrode 40b, respectively. By controlling the amount of charge stored, it is possible to store multiple data in one cell. The operation of the composite bit cell is possible.

In this case, the abscissa represents a voltage applied to both ends of the capacitor, and the ordinate represents a stored charge.

It solves the process problem by drastically lowering the height of the capacitor which causes the process problem in the DRAM manufacturing process, and accessing arbitrary cells like the NOR type to the data storage function of the page unit, which is a disadvantage of NAND type Flash Memory. In addition, compared to the NOR type, it has the advantage of improving reliability and reducing unit cell area.

This has the advantages in process and reliability and at the same time improves dramatically. Lower driving voltages allow lower voltages and faster driving speeds. A memory implementation that can reduce power consumption is possible.

In addition, it is also advantageous that high-speed operation is possible by utilizing the charges induced in the junction, and a complex data memory capable of storing two or more pieces of data in one cell by controlling the amount of accumulated charges can be implemented.

Claims (20)

Forming a semiconductor substrate and a semiconductor device layer, and a well layer between the semiconductor substrate and the device layer; Forming a first insulating film comprising an oxide film and a nitride film formed on the device layer; Etching the first insulating film to isolate the devices from each other so as to expose regions used for device isolation; Forming an oxide film for device isolation in the device layer exposed for device isolation; Removing the formed first insulating layer for the device isolation to visually expose the semiconductor surface, which is a device layer, and the oxide film for device isolation; Forming a second insulating film for the gate oxide film over the oxide region for device isolation including the semiconductor device layer; Forming a first gate metal on the formed gate oxide layer for a gate control; Forming a third oxide used for gate formation on the formed first gate metal; Etching the formed third oxide to form a gate formed on the semiconductor device layer to serve as a gate, and etching the third oxide to expose a surface used for the semiconductor device layer by using the etched third oxide; Removing residual third oxide used during etching after the gate is physically formed; Forming a fourth insulating film on the semiconductor surface including the gate and the oxide for isolating the semiconductor device; Etching a fourth insulating film to expose a portion of the semiconductor device layer to form a drain and a source, respectively; Implanting predetermined impurity ions into the drain contact hole and the source contact hole to form a drain region and a source region in the device layer, respectively; A device layer between the drain region and the source region is used as a channel region, and forming a drain electrode and a source electrode respectively to be electrically connected to the drain region and the source region through the drain contact hole and the source contact hole, respectively; Forming a fifth insulating film on the exposed fourth insulating film including the formed second metal line; Etching the fifth insulating layer to simultaneously form a via plug and a lower electrode of the tunneling capacitor to be electrically connected to a source plug formed in a source contact hole; Forming a tunneling capacitor on the formed lower electrode. The method of claim 1, wherein the device layer is any one of an n-type semiconductor layer and a p-type semiconductor layer. The method of manufacturing a semiconductor memory device according to claim 1, wherein the semiconductor substrate and the element layer are any one of a semiconductor film and a conductive film such as a silicon film, a GaAs film, a Germanium, an InP, and a Gap film. The method of manufacturing a semiconductor memory device according to claim 1, wherein the structure of the transistor star, which is an element formed in the semiconductor element layer, is one of MOSFET, JFET, MESFET, and BJT structure. The method of claim 1, wherein the impurity ions are any one of materials capable of forming a conductive layer in an element layer including As, P, B, and BF 2. The semiconductor memory of claim 1, wherein the drain electrode and the source electrode material are any one of conductive materials including tungsten (W), aluminum (Al), silicon (Si), and copper (Cu), respectively. Method of manufacturing the device. The method of claim 1, wherein the contact plug makes ohmic contact with the drain region and the source region. The method of claim 1, wherein the tunneling capacitor is in ohmic contact with a source region through the contact plug. The method of claim 1, wherein the forming of the tunneling capacitor comprises sequentially forming a tunneling capacitor lower electrode film, a tunneling oxide film, a floating electrode, an interlayer oxide, and a tunneling capacitor upper electrode film on the fifth insulating layer including via contact holes. Steps; Etching the tunneling capacitor upper electrode film, the interlayer insulating film, the floating electrode, the tunneling oxide film, and the tunneling capacitor lower electrode film to form an electrode pattern. The method of claim 9, wherein the tunneling oxide comprises at least one of SiO 2, Al 2 O 3, SiO x N y, and HfxOy. The method of claim 9, wherein the interlayer insulating film includes at least one of SiO 2, Si 3 N 4, PZT, BST, TiOX, Al 2 O 3, SiO x N y, and HfO 2. 10. The method of claim 9, wherein the lower electrode, the floating electrode, and the upper electrode is metal (Pt), copper (Cu), aluminum (Al), silicon (Si), iridium oxide (IrO2), iridium (Ir), tungsten ( W), a method for manufacturing a semiconductor memory device, which is a film formed of at least one of tie silicide (TiSi2) and cobalt silicide (CoSi2) The method of claim 9, wherein the forming of the tunneling capacitor further comprises forming a barrier film on the tunneling capacitor lower electrode layer and the tunneling oxide. 10. The method of claim 9, further comprising forming a barrier film between the tunneling oxide and the floating electrode. 10. The method of claim 9, further comprising forming a barrier film between the floating electrode and the interlayer oxide. 10. The method of claim 9, further comprising forming a barrier film between the interlayer oxide and the upper electrode. The semiconductor memory device of claim 9, wherein the forming of the tunneling capacitor further comprises forming a barrier layer on the upper surface of the tunneling capacitor upper electrode layer and on a side of the tunneling capacitor 40 formed after etching to form the tunneling capacitor. Manufacturing method. The method of claim 1, further comprising: forming a sixth insulating layer on the fifth insulating layer including the tunneling capacitor; Forming a via such that the top surface of the tunneling capacitor is partially exposed; Forming a metal line, which is a plate line, to be electrically connected to the tunneling capacitor through the via. 19. The method of claim 18, further comprising: etching to expose the front surface of the upper surface of the tunneling capacitor; And forming a plate line on the sixth insulator including the upper electrode of the tunneling capacitor to form a plate line electrically connected to the upper electrode. The semiconductor memory device of claim 1, wherein a lower electrode of the tunneling capacitor is electrically connected to a source contact plug, and includes a tunneling capacitor formed to overlap a portion of the fifth insulator layer on both sides of the contact plug.