KR20030002882A - Method for forming bitline plug in semiconductor device - Google Patents
Method for forming bitline plug in semiconductor device Download PDFInfo
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- KR20030002882A KR20030002882A KR1020010038710A KR20010038710A KR20030002882A KR 20030002882 A KR20030002882 A KR 20030002882A KR 1020010038710 A KR1020010038710 A KR 1020010038710A KR 20010038710 A KR20010038710 A KR 20010038710A KR 20030002882 A KR20030002882 A KR 20030002882A
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- South Korea
- Prior art keywords
- forming
- bit line
- tungsten silicide
- tungsten
- contact hole
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010937 tungsten Substances 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 229910007991 Si-N Inorganic materials 0.000 description 7
- 229910006294 Si—N Inorganic materials 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 비트라인 콘택의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line contact.
최근에 COB(Capacitor Over Bitline) 구조의 DRAM에서 텅스텐 비트라인이 적용됨에 따라 Ti/TiN/W에 의한 플러깅 기술에 대한 관심이 많아지고 있다. 그러나, 기가셀(giga cell) 이상의 콘택에서는 물리적기상증착법(Physical Vapor Deposition; PVD)에 한계가 있으며 현재 TiCl4계 CVD Ti와 TiN 기술은 Cl에 의한 실리콘 손실, Cl 불순물에 대한 부담이 있다.Recently, as tungsten bitlines are applied to DRAMs having a capacitor over bitline (COB) structure, interest in plugging technology using Ti / TiN / W is increasing. However, there are limitations on physical vapor deposition (PVD) in contacts over giga cells, and TiCl 4 based CVD Ti and TiN technologies are burdened by Cl loss and Cl impurities.
도 1a 내지 도 1b는 종래기술에 따른 비트라인 콘택의 형성 방법을 도시한 도면이다.1A to 1B illustrate a method of forming a bit line contact according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 층간절연막(12)을 증착한 후, 층간절연막(12)을 선택적으로 식각하여 콘택홀을 형성하고, 콘택홀을 포함한 층간절연막(12)상에 CVD-TiN(13)을 증착한다. 이 때, CVD-TiN(13)은 콘택홀에 충분히 매립되는 두께로 증착되며, CVD-TiN(13) 증착과 동시에 반도체기판(11)의 실리콘과 반응하여 반도체기판(11) 표면에 티타늄실리사이드(14)가 형성된다.As shown in FIG. 1A, after the interlayer insulating film 12 is deposited on the semiconductor substrate 11, the interlayer insulating film 12 is selectively etched to form a contact hole, and the interlayer insulating film 12 including the contact hole is formed. CVD-TiN 13 is deposited on it. At this time, the CVD-TiN 13 is deposited to a thickness sufficiently filled in the contact hole, and simultaneously with the deposition of the CVD-TiN 13, the CVD-TiN 13 reacts with silicon of the semiconductor substrate 11 to form a titanium silicide ( 14) is formed.
도 1b에 도시된 바와 같이, CVD-TiN(13)을 화학적기계적연마 또는 에치백하여 층간절연막(13)상의 CVD-TiN(13)을 제거하므로써 콘택홀에 매립되는 TiN 플러그(15)를 형성한다.As shown in FIG. 1B, the CVD-TiN 13 is chemically mechanically polished or etched back to remove the CVD-TiN 13 on the interlayer insulating film 13, thereby forming a TiN plug 15 embedded in the contact hole. .
계속해서, TiN 플러그(14)상에 비트라인용 텅스텐(16)을 증착한다.Subsequently, tungsten 16 for bit lines is deposited on the TiN plug 14.
그러나, TiCl4CVD-TiN을 이용하여 비트라인콘택을 플러깅하는 경우, TiN막 자체가 70μΩ·cm 이상의 높은 비저항을 보여 비트라인의 콘택 저항을 증가시키는 문제점이 있다.However, when plugging the bit line contact using TiCl 4 CVD-TiN, the TiN film itself has a high specific resistance of 70 μΩ · cm or more, thereby increasing the contact resistance of the bit line.
또한, TiN막 자체의 스트레스로 인하여 700Å 이상의 두께로 증착하면 스트레스 극복 현상으로 TiN막에 크랙이 발생하는데 이를 방지하기 위해서는 전체 두께를 나누어 증착하거나 다른 방법에 의해 증착해야만 하는 번거로움이 있다.In addition, when the TiN film is deposited with a thickness of 700 GPa or more due to the stress of the TiN film itself, cracks are generated in the TiN film due to the stress overcoming phenomenon. In order to prevent this, the entire thickness is deposited or deposited by another method.
그리고, TiCl4를 이용한 CVD 공정의 경우, 그 산출량(Throughput)이 20wfs/hr미만으로서 PVD 공정에 비해 매우 낮으며, 더욱이 스트레스에 의한 크랙을 방지하기 위해 두께를 나누어 증착하는 경우보다 산출량의 현저한 감소를 나타낸다.In the case of the CVD process using TiCl 4 , the throughput is less than 20 wfs / hr, which is much lower than that of the PVD process. Furthermore, in order to prevent cracking due to stress, the yield is significantly reduced compared with the deposition by dividing thickness. Indicates.
한편, 물리적기상증착법(PVD)에 의한 경우, Ti/TiN/RTP/TiN/W은 콘택홀 크기가 작아짐에 따라 그 자체의 단차피복성의 한계와 복잡한 공정으로 많은 어려움이 있다.On the other hand, in the case of the physical vapor deposition method (PVD), Ti / TiN / RTP / TiN / W has a lot of difficulties due to its own step coverage and complex process as the contact hole size is reduced.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 콘택 매립 불량을 방지하고 콘택 저항 증가를 억제하는데 적합한 비트라인 콘택의 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method for forming a bit line contact, which is suitable for preventing poor contact filling and suppressing an increase in contact resistance.
도 1a 내지 도 1b는 종래기술에 따른 비트라인 플러그의 형성 방법을 도시한 공정 단면도,1A to 1B are cross-sectional views illustrating a method of forming a bit line plug according to the prior art;
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 비트라인 플러그의 형성 방법을 도시한 공정 단면도,2A through 2C are cross-sectional views illustrating a method of forming a bit line plug according to an exemplary embodiment of the present invention;
도 3a 내지 도 3b는 본 발명의 다른 실시예에 따른 비트라인 플러그의 형성 방법을 도시한 공정 단면도.3A to 3B are cross-sectional views illustrating a method of forming a bit line plug according to another exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 소스/드레인21: semiconductor substrate 22: source / drain
23 : 층간절연막 24a : 실리콘부화막23 interlayer insulating film 24a silicon encapsulation film
24b : 텅스텐실리사이드 24c : 텅스텐실리사이드 플러그24b: tungsten silicide 24c: tungsten silicide plug
25 : W-Si-N 26 : 텅스텐25: W-Si-N 26: Tungsten
상기의 목적을 달성하기 위한 본 발명의 비트라인 플러그의 형성 방법은 트랜지스터의 소스/드레인이 형성된 반도체기판상에 층간절연막을 형성하는단계, 상기 층간절연막을 선택적으로 식각하여 상기 소스/드레인을 노출시키는 콘택홀을 형성하는 단계, 상기 콘택홀내에 텅스텐실리사이드를 플러깅시키는 단계, 상기 플러깅된 텅스텐실리사이드의 표면에 확산배리어막을 형성하는 단계, 및 상기 확산배리어막상에 텅스텐을 증착하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a bit line plug according to an embodiment of the present invention includes forming an interlayer insulating film on a semiconductor substrate on which a source / drain of a transistor is formed, and selectively etching the interlayer insulating film to expose the source / drain. Forming a contact hole, plugging tungsten silicide into the contact hole, forming a diffusion barrier film on the surface of the plugged tungsten silicide, and depositing tungsten on the diffusion barrier film. It is done.
바람직하게, 상기 텅스텐실리사이드를 플러깅시키는 단계는, 화학기상증착장치내에서 SiH4계 가스를 이용하여 상기 콘택홀의 측벽 및 소스/드레인상에 실리콘부화막을 증착하는 단계, 및 동일 장치에서 연속적으로 상기 실리콘부화막상에 DCS를 이용하여 상기 텅스텐실리사이드를 증착하는 단계를 포함하여 이루어짐을 특징으로 한다.Preferably, plugging the tungsten silicide comprises depositing a silicon enrichment film on the sidewall and source / drain of the contact hole using a SiH 4 -based gas in a chemical vapor deposition apparatus, and continuously in the same apparatus. And depositing the tungsten silicide using DCS on the incubation layer.
바람직하게, 상기 확산배리어막을 형성하는 단계는, N2또는 NH3분위기의 500℃ 이상의 고온에서 열처리하여 이루어지거나, 또는 400℃ 이상의 온도에서 N2또는 NH3플라즈마 처리하여 이루어짐을 특징으로 한다.Preferably, the forming of the diffusion barrier film may be performed by heat treatment at a high temperature of 500 ° C. or higher in an N 2 or NH 3 atmosphere, or by N 2 or NH 3 plasma treatment at a temperature of 400 ° C. or higher.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 비트라인 콘택의 형성 방법을 도시한 공정 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming a bit line contact according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)에 워드라인(도시 생략) 및 소스/드레인(22)을 구비하는 트랜지스터를 형성한 후, 반도체기판(21)상에 층간절연막(23)을 증착한다. 여기서, 트랜지스터 형성후, 캐패시터를 형성한다.As shown in FIG. 2A, after forming a transistor having a word line (not shown) and a source / drain 22 on the semiconductor substrate 21, an interlayer insulating film 23 is deposited on the semiconductor substrate 21. do. Here, after the transistor is formed, a capacitor is formed.
다음으로, 층간절연막(23)을 선택적으로 식각하여 소스/드레인(22)의 표면을 노출시키는 콘택홀을 형성한 후, 노출된 소스/드레인(22)의 표면에 콘택되고 콘택홀에 매립될 두께로 층간절연막(23)상에 화학기상증착법(CVD)을 통해 텅스텐실리사이드(24b)를 증착한다.Next, after the interlayer insulating layer 23 is selectively etched to form a contact hole exposing the surface of the source / drain 22, the thickness to be contacted to the exposed surface of the source / drain 22 and to be filled in the contact hole. The tungsten silicide 24b is deposited on the interlayer insulating film 23 by chemical vapor deposition (CVD).
이 때, 텅스텐실리사이드(24b)의 화학기상증착시, 초기 SiH4계 가스를 이용하여 실리콘부화막(Si-rich layer)(24a)을 증착한 후, 연속하여 DCS를 이용하여 텅스텐실리사이드(24b)를 증착한다. 여기서, 실리콘부화막(24a)을 형성하는 이유는 텅스텐실리사이드(24b)와 층간절연막(산화막)(23)의 접착성을 증가시키기 위함이다.At this time, during the chemical vapor deposition of the tungsten silicide 24b, a silicon-rich layer 24a is deposited using an initial SiH 4 -based gas, and then tungsten silicide 24b is continuously formed using DCS. Deposit. The reason for forming the silicon encapsulation film 24a is to increase the adhesion between the tungsten silicide 24b and the interlayer insulating film (oxide film) 23.
도 2b에 도시된 바와 같이, 층간절연막(23)의 표면이 노출될때까지 화학적기계적연마 또는 에치백을 실시하여 콘택홀에 완전 매립되는 텅스텐실리사이드 플러그(24c)를 형성한다.As shown in FIG. 2B, the tungsten silicide plug 24c completely embedded in the contact hole is formed by performing chemical mechanical polishing or etch back until the surface of the interlayer insulating film 23 is exposed.
이 때, 콘택홀의 측벽에는 실리콘부화막(24a)이 잔류한다.At this time, the silicon encapsulation film 24a remains on the sidewall of the contact hole.
도 2c에 도시된 바와 같이, N2또는 NH3분위기의 500℃ 이상의 고온 열처리 또는 400℃ 이상의 온도에서 N2또는 NH3플라즈마를 텅스텐실리사이드 플러그(24c)의 표면에 밤바드먼트(Bombardment)해주므로써 텅스텐실리사이드 플러그(24c) 및 층간절연막(23)의 표면에 W-Si-N(25)을 형성시킨다.As shown in FIG. 2C, by applying a N 2 or NH 3 plasma to the surface of the tungsten silicide plug 24c at a high temperature heat treatment of 500 ° C. or higher in an N 2 or NH 3 atmosphere or at a temperature of 400 ° C. or higher. W-Si-N 25 is formed on the surfaces of the tungsten silicide plug 24c and the interlayer insulating film 23.
다음으로, W-Si-N(25)상에 비트라인을 위한 텅스텐(26)을 증착한다. 이 때, 텅스텐(26)은 화학기상증착법(CVD) 또는 물리적기상증착법(PVD)으로 증착된다.Next, tungsten 26 for the bit line is deposited on the W-Si-N 25. At this time, tungsten 26 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
이와 같이, 텅스텐실리사이드 플러그(24c)의 표면에 W-Si-N(25)을 형성시키므로써 후속 열공정동안 텅스텐(26)과 텅스텐실리사이드 플러그(24c)의 상호 확산을 방지한다.As such, the formation of W-Si-N 25 on the surface of the tungsten silicide plug 24c prevents the interdiffusion of tungsten 26 and tungsten silicide plug 24c during subsequent thermal processing.
한편, TiCl4CVD-TiN의 경우 비저항값이 250μΩ·cm 인 반면, 텅스텐실리사이드의 경우는 80μΩ·cm 이므로 비트라인 플러그의 콘택저항을 낮출 수 있다.Meanwhile, in the case of TiCl 4 CVD-TiN, the specific resistance value is 250 μΩ · cm, whereas in the case of tungsten silicide, the contact resistance of the bit line plug can be lowered.
도 3a 내지 도 3b는 본 발명의 다른 실시예에 따른 비트라인 플러그의 형성 방법을 도시한 도면이다.3A to 3B illustrate a method of forming a bit line plug according to another exemplary embodiment of the present invention.
도 3a에 도시된 바와 같이, 반도체기판(21)에 워드라인(도시 생략) 및 소스/드레인(22)을 구비하는 트랜지스터를 형성한 후, 반도체기판(21)상에 층간절연막(23)을 증착한다. 여기서, 트랜지스터 형성후, 캐패시터를 형성한다.As shown in FIG. 3A, after forming a transistor including a word line (not shown) and a source / drain 22 on the semiconductor substrate 21, an interlayer insulating film 23 is deposited on the semiconductor substrate 21. do. Here, after the transistor is formed, a capacitor is formed.
다음으로, 층간절연막(23)을 선택적으로 식각하여 소스/드레인(22)의 표면을 노출시키는 콘택홀을 형성한 후, 노출된 소스/드레인(22)의 표면에 콘택되고 콘택홀을 따라 층간절연막(23)상에 화학기상증착법(CVD)을 통해 텅스텐실리사이드(24b)를 증착한다.Next, the interlayer insulating layer 23 is selectively etched to form a contact hole exposing the surface of the source / drain 22, and then contacted to the exposed surface of the source / drain 22 and along the contact hole. Tungsten silicide 24b is deposited on (23) by chemical vapor deposition (CVD).
이 때, 텅스텐실리사이드(24b)의 화학기상증착시, 초기 SiH4계 가스를 이용하여 실리콘부화막(Si-rich layer)(24a)을 증착한 후, 연속하여 DCS를 이용하여 텅스텐실리사이드(24b)를 증착한다. 여기서, 실리콘부화막(24a)을 형성하는 이유는 텅스텐실리사이드(24b)와 층간절연막(산화막)(23)의 접착성을 증가시키기 위함이다.At this time, during the chemical vapor deposition of the tungsten silicide 24b, a silicon-rich layer 24a is deposited using an initial SiH 4 -based gas, and then tungsten silicide 24b is continuously formed using DCS. Deposit. The reason for forming the silicon encapsulation film 24a is to increase the adhesion between the tungsten silicide 24b and the interlayer insulating film (oxide film) 23.
도 3b에 도시된 바와 같이, 층간절연막(23)의 표면이 노출될때까지 화학적기계적연마 또는 에치백을 실시하여 콘택홀의 측벽을 따라 콘택홀내에만 텅스텐실리사이드(24b)를 잔류시킨다.As shown in FIG. 3B, chemical mechanical polishing or etch back is performed until the surface of the interlayer insulating film 23 is exposed to leave tungsten silicide 24b only in the contact hole along the sidewall of the contact hole.
이 때, 콘택홀의 측벽에는 실리콘부화막(24a)이 잔류한다.At this time, the silicon encapsulation film 24a remains on the sidewall of the contact hole.
계속해서, N2또는 NH3분위기의 500℃ 이상의 고온 열처리 또는 400℃ 이상의 온도에서 N2또는 NH3플라즈마를 텅스텐실리사이드(24b)의 표면에 밤바드먼트(Bombardment)해주므로써 텅스텐실리사이드(24b) 및 층간절연막(23)의 표면에 W-Si-N(25)을 형성시킨다.Subsequently, N 2 or night Bard garment tungsten silicide (24b) meurosseo give (Bombardment) of N 2 or NH 3 plasma at least 500 ℃ high temperature heat treatment or at least 400 ℃ temperature of the NH 3 atmosphere to the surface of the tungsten silicide (24b) and W-Si-N 25 is formed on the surface of the interlayer insulating film 23.
다음으로, W-Si-N(25)상에 비트라인을 위한 텅스텐(26)을 증착한다. 이 때, 텅스텐(26)은 화학기상증착법(CVD) 또는 물리적기상증착법(PVD)으로 증착된다.Next, tungsten 26 for the bit line is deposited on the W-Si-N 25. At this time, tungsten 26 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
이와 같이, 텅스텐실리사이드(24b)의 표면에 W-Si-N(25)을 형성시키므로써 후속 열공정동안 텅스텐(26)과 텅스텐실리사이드(24b)의 상호 확산을 방지한다.As such, the formation of W-Si-N 25 on the surface of tungsten silicide 24b prevents the interdiffusion of tungsten 26 and tungsten silicide 24b during subsequent thermal processes.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 비저항값이 낮은 텅스텐실리사이드를 플러그로 이용하므로써 미세한 콘택홀에 충분히 매립시킴과 동시에 비트라인의 콘택저항을 감소시킬 수 있는 효과가 있다.As described above, the present invention has the effect of sufficiently filling the minute contact hole and reducing the contact resistance of the bit line by using tungsten silicide having a low specific resistance as a plug.
또한, CVD-TiN을 이용하지 않으면서도 우수한 열적 안정성을 갖는 텅스텐실리사이드를 이용하므로써 크랙과 같은 결함이 억제되고, 플러깅 공정이 용이하여 산출량이 개선되는 효과가 있다.In addition, by using tungsten silicide having excellent thermal stability without using CVD-TiN, defects such as cracks are suppressed, and the plugging process is easy, so that the yield is improved.
Claims (7)
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| KR1020010038710A KR20030002882A (en) | 2001-06-30 | 2001-06-30 | Method for forming bitline plug in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020010038710A KR20030002882A (en) | 2001-06-30 | 2001-06-30 | Method for forming bitline plug in semiconductor device |
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