KR20030002807A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20030002807A KR20030002807A KR1020010038527A KR20010038527A KR20030002807A KR 20030002807 A KR20030002807 A KR 20030002807A KR 1020010038527 A KR1020010038527 A KR 1020010038527A KR 20010038527 A KR20010038527 A KR 20010038527A KR 20030002807 A KR20030002807 A KR 20030002807A
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- South Korea
- Prior art keywords
- gate
- insulating film
- insulation layer
- forming
- buffer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 150000004767 nitrides Chemical class 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 17
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- 238000004519 manufacturing process Methods 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- -1 LDD nitride Chemical class 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 실리콘기판표면의 결함을 감소시키고 게이트 숄더부(shoulder region)의 마진을 확보하여 반도체소자의 전기적 특성을 개선시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to manufacturing a semiconductor device capable of improving electrical characteristics of a semiconductor device by reducing defects on a surface of a silicon substrate and securing a margin of a gate shoulder region. It is about a method.
종래기술에 따른 반도체소자의 제조방법을 도 1 내지 도 6을 참조하여 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to the prior art will be described with reference to FIGS. 1 to 6.
도 1 내지 도 6은 종래기술에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
종래기술에 따른 반도체소자의 제조방법은, 도 1에 도시된 바와같이, 먼저 실리콘기판(1)상에 소자형성영역을 한정하는 소자분리막(3)을 형성한다.In the method of manufacturing a semiconductor device according to the prior art, as shown in FIG. 1, first, an element isolation film 3 defining an element formation region is formed on a silicon substrate 1.
그다음, 도면에 도시하지 않았지만, 소자분리막(3)이 형성된 실리콘기판(1)상에 게이트절연막(미도시)과 게이트물질층(미도시) 및 하드마스크용 절연막(미도시)을 순차적으로 증착하고, 상기 하드마스크용 절연막(미도시)상에 게이트 형성영역을 한정하는 제1감광막패턴(미도시)을 형성한다.Next, although not shown in the drawing, a gate insulating film (not shown), a gate material layer (not shown), and an insulating film for a hard mask (not shown) are sequentially deposited on the silicon substrate 1 on which the device isolation film 3 is formed. A first photoresist layer pattern (not shown) defining a gate formation region is formed on the hard mask insulating layer (not shown).
이어서, 도 1에 도시된 바와같이, 상기 제1감광막패턴(미도시)을 마스크로 상기 절연막과 게이트물질층 및 게이트산화막을 순차적으로 패터닝하여 게이트산화막패턴(5)과 게이트(7) 및 절연막패턴(9)을 형성한다.Subsequently, as shown in FIG. 1, the insulating film, the gate material layer, and the gate oxide film are sequentially patterned using the first photoresist film pattern (not shown) as a mask to form the gate oxide film pattern 5, the gate 7, and the insulating film pattern. (9) is formed.
그다음, 도 2에 도시된 바와같이, 상기 제1감광막패턴(미도시)을 제거하고, 상기 전체 구조의 상면에 버퍼질화막(11)을 증착한다음 상기 버퍼질화막(11)상에 게이트 LDD용 산화막(12)을 증착한다.Next, as shown in FIG. 2, the first photoresist pattern (not shown) is removed, a buffer nitride film 11 is deposited on the top surface of the entire structure, and then an oxide film for gate LDD is formed on the buffer nitride film 11. (12) is deposited.
이어서, 도 3에 도시된 바와같이, 상기 게이트 LDD용 산화막(12)중에서 셀주변부에 있는 산화막부분을 제외한 셀영역에 있는 산화막부분을 습식식각에 의해 완전히 제거한다. 이때, 상기 셀주변부에 진행되는 공정들에 대해서는 생략하기로 한다.Next, as shown in FIG. 3, the oxide film portion in the cell region other than the oxide film portion in the cell periphery portion of the gate LDD oxide film 12 is completely removed by wet etching. In this case, the processes performed in the cell peripheral portion will be omitted.
그다음, 도 4에 도시된 바와같이, 상기 전체 구조의 상면에 상기 게이트 LDD용 질화막(미도시)을 증착하고, 상기 질화막(미도시)과 버퍼질화막(11)을 에치백하여 상기 하드마스크용 절연막패턴(9)과 게이트패턴(7) 및 게이트산화막패턴(5)의 측면에 제1스페이서(13)를 형성한다.Next, as shown in FIG. 4, the gate LDD nitride film (not shown) is deposited on the top surface of the entire structure, and the nitride film (not shown) and the buffer nitride film 11 are etched back to form an insulating film for the hard mask. The first spacer 13 is formed on side surfaces of the pattern 9, the gate pattern 7, and the gate oxide layer pattern 5.
이어서, 도 5에 도시된 바와같이, 상기 스페이서(13)를 포함한 상기 전체 구조의 상면에 층간산화막(15)을 증착하고, 그 위에 제2감광막패턴(미도시)을 형성한다.Subsequently, as shown in FIG. 5, an interlayer oxide film 15 is deposited on the upper surface of the entire structure including the spacer 13, and a second photoresist film pattern (not shown) is formed thereon.
그다음, 상기 제2감광막패턴(미도시)을 마스크로 상기 층간산화막(15)과 상기 스페이서(13) 및 하드마스크용 질화막(9)을 선택적으로 제거하여 스토리지노드 콘택홀(17a)과 비트라인콘택홀(17b)을 형성한다.Next, the interlayer oxide layer 15, the spacer 13, and the hard mask nitride layer 9 are selectively removed using the second photoresist layer pattern (not shown) as a mask to form the storage node contact hole 17a and the bit line contact. The hole 17b is formed.
이어서, 상기 스토리지노드 콘택홀(17a)과 비트라인콘택홀(17b)을 포함한 전체 구조의 상면에 스페이서용 질화막(미도시)을 증착하고, 이를 에치백하여 상기 스토리지노드 콘택홀(17a)과 비트라인콘택홀(17b)의 측벽에 제2스페이서(19)를 형성한다.Subsequently, a spacer nitride layer (not shown) is deposited on the upper surface of the entire structure including the storage node contact hole 17a and the bit line contact hole 17b, and then etched back to form the spacer node contact hole 17a and the bit. The second spacer 19 is formed on the sidewall of the line contact hole 17b.
그다음, 도 6에 도시된 바와같이, 상기 제2스페이서(19)를 포함한 전체 구조의 상면에 폴리실리콘층(미도시)을 증착하고, 상기 폴리실리콘층(미도시)을 에치백하여 상기 스토리지노드 콘택홀(17a)과 비트라인콘택홀(17b)내에 스토리지노드콘택부(21a)와 비트라인콘택부(22b)를 각각 형성한다.Next, as shown in FIG. 6, a polysilicon layer (not shown) is deposited on the upper surface of the entire structure including the second spacer 19, and the polysilicon layer (not shown) is etched back to the storage node. The storage node contact portion 21a and the bit line contact portion 22b are formed in the contact hole 17a and the bit line contact hole 17b, respectively.
그러나, 상기와 같은 종래기술에 따른 반도체소자의 제조방법에 있어서는 다음과 같은 문제점이 있다.However, there is a problem in the method of manufacturing a semiconductor device according to the prior art as described above.
종래기술에 따른 반도체소자의 제조방법에 있어서는, 게이트 LDD용 질화막스페이서의 형성 및 스토리지노드 콘택을 형성하기 위한 식각공정이 서로 이원화되어 있어 실리콘기판 표면의 손실이 증가하게 되고, 게이트 숄더부분(should region)의 마진이 감소하게 된다.In the method of manufacturing a semiconductor device according to the related art, the etching process for forming the gate LDD nitride film spacer and the forming of the storage node contact is dualized with each other to increase the loss of the silicon substrate surface and to form the gate shoulder region. ) Margins will decrease.
따라서, 실리콘기판의 표면의 손실이 증가되므로 인해 전계 발생이 커지게 되므로써 반도체소자의 리프레쉬 특성이 저하된다.Therefore, the loss of the surface of the silicon substrate is increased, so that the generation of the electric field is increased, thereby reducing the refresh characteristics of the semiconductor device.
또한, 게이트 숄더부분의 마진이 감소되므로 인해 게이트 캡질화막의 두께가 증가하게 되고 스토리지노드 콘택시의 식각 마진이 감소하게 된다.In addition, since the margin of the gate shoulder portion is reduced, the thickness of the gate cap nitride layer is increased and the etching margin of the storage node contact is reduced.
따라서, 게이트 숄더부의 마진을 확보하기 위해서는 추가로 스페이서용 질화막을 증착해야기 때문에 스토리지노드 콘택홀의 확보마진이 감소하는 문제점이 있다.Therefore, in order to secure the margin of the gate shoulder portion, the nitride layer for spacers must be additionally deposited, thereby securing a margin of securing the storage node contact hole.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 실리콘기판 표면의 결함을 감소시키고 게이트 숄더부(shoulder region)의 마진을 확보하여 반도체소자의 전기적 특성을 개선시킬 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, a semiconductor device that can improve the electrical characteristics of the semiconductor device by reducing the defects on the surface of the silicon substrate and ensuring the margin of the gate shoulder region (shoulder region) The purpose is to provide a method of manufacturing.
또한, 본 발명의 다른 목적은 게이트 LDD용 절연막 식각 및 콘택형성시의 실리콘기판 표면의 손실을 감소시키고 게이트 숄더부의 절연막의 손실을 감소시켜 반도체소자의 리프레쉬 특성을 개선시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.In addition, another object of the present invention is to reduce the loss of the surface of the silicon substrate during the etching and contact formation of the insulating film for the gate LDD and to reduce the loss of the insulating film of the gate shoulder portion, thereby improving the refresh characteristics of the semiconductor device. In providing.
도 1 내지 6는 종래 기술에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.1 to 6 are process cross-sectional views for explaining a method of manufacturing a semiconductor device according to the prior art.
도 7 내지 도 13는 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.7 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 실리콘기판 33 : 소자분리막31 silicon substrate 33 device isolation film
35 : 게이트산화막 37 : 게이트35: gate oxide film 37: gate
39 : 캡질화막 41 : 버퍼질화막39: cap nitride film 41: buffer nitride film
43 : 희생산화막 45 : 제1스페이서43: sacrificial oxide film 45: the first spacer
47 : 제2스페이서 49a : 스토리지노드콘택홀47: second spacer 49a: storage node contact hole
49b : 비트라인콘택홀 51a : 스토리지노드콘택부49b: bit line contact hole 51a: storage node contact portion
51b : 비트라인콘택부51b: bit line contact portion
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은, 실리콘기판상에 게이트를 형성하는 단계; 상기 게이트를 포함한 실리콘기판상에 버퍼절연막을 형성하는 단계; 상기 버퍼절연막상에 상기 게이트를 매립하는 희생절연막을 형성하는 단계; 상기 희생절연막을 상기 버퍼절연막이 노출될때까지 선택적으로 제거하여 상기 게이트상측의 버퍼절연막부분과 게이트사이에만 남도록 하는 단계; 상기 게이트상측의 버퍼절연막부분에 남아 있는 희생절연막부분의 측면에 절연막스페이서를 형성하는 단계; 상기 선택적으로 패터닝된 희생절연막을 제거하고, 상기 절연막스페이서를 포함한 전체 구조의 상면에 절연막을 형성하는 단계; 상기 절연막과 버퍼절연막의 일부분을 에치백하여 스토리지노드콘택홀과 비트라인 콘택홀을 형성하는 단계; 및 상기 스토리지노드 콘택홀 및 비트라인 콘택홀내에 각각 스토리지노드콘택부와 비트라인콘택부를 형성하는 단계를 포함하여 이루어지는 것을 특징으로한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a gate on a silicon substrate; Forming a buffer insulating film on the silicon substrate including the gate; Forming a sacrificial insulating film filling the gate on the buffer insulating film; Selectively removing the sacrificial insulating film until the buffer insulating film is exposed so as to remain only between the buffer insulating film portion on the gate and the gate; Forming an insulating film spacer on the side of the sacrificial insulating film portion remaining in the buffer insulating film portion on the gate; Removing the selectively patterned sacrificial insulating film and forming an insulating film on an upper surface of the entire structure including the insulating film spacer; Etching back a portion of the insulating layer and the buffer insulating layer to form a storage node contact hole and a bit line contact hole; And forming a storage node contact portion and a bit line contact portion in the storage node contact hole and the bit line contact hole, respectively.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 7 내지 도 13은 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한공정단면도이다.7 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명의 일실시예에 따른 반도체소자의 제조방법은, 도 7에 도시된 바와같이, 먼저 실리콘기판(31)상에 소자형성영역을 한정하는 소자분리막(33)을 형성한다.In the method of manufacturing a semiconductor device according to an embodiment of the present invention, as shown in FIG. 7, first, an isolation layer 33 defining an element formation region is formed on a silicon substrate 31.
그다음, 도면에 도시하지 않았지만, 소자분리막(33)이 형성된 실리콘기판(31)상에 게이트절연막(미도시)과 게이트물질층(미도시) 및 캡절연막(미도시)을 순차적으로 증착하고, 상기 캡절연막(미도시)상에 게이트 형성영역을 한정하는 제1감광막패턴(미도시)을 형성한다.Next, although not shown in the drawings, a gate insulating film (not shown), a gate material layer (not shown), and a cap insulating film (not shown) are sequentially deposited on the silicon substrate 31 on which the device isolation film 33 is formed. A first photoresist pattern (not shown) defining a gate formation region is formed on the cap insulation layer (not shown).
이어서, 도 7에 도시된 바와같이, 상기 제1감광막패턴(미도시)을 마스크로 상기 절연막과 게이트물질층 및 게이트산화막을 순차적으로 패터닝하여 게이트산화막패턴(35)과 게이트(37) 및 캡절연막패턴(39)을 형성한다.Subsequently, as shown in FIG. 7, the insulating film, the gate material layer, and the gate oxide film are sequentially patterned using the first photoresist film pattern (not shown) as a mask to form the gate oxide film pattern 35, the gate 37, and the cap insulating film. The pattern 39 is formed.
그다음, 도 8에 도시된 바와같이, 상기 제1감광막패턴(미도시)을 제거하고, 상기 전체 구조의 상면에 버퍼질화막(41)을 증착한다음 상기 버퍼질화막(41)상에 게이트 LDD용 산화막(미도시)와 층간산화막(미도시)을 순차적으로 증착한다. 이때, 셀주변부에 진행되는 공정들에 대해서는 생략한다.Next, as shown in FIG. 8, the first photoresist film pattern (not shown) is removed, a buffer nitride film 41 is deposited on the upper surface of the entire structure, and then an oxide film for gate LDD is formed on the buffer nitride film 41. (Not shown) and an interlayer oxide film (not shown) are sequentially deposited. In this case, the processes performed in the cell peripheral portion will be omitted.
이어서, 도 9에 도시된 바와같이, 상기 층간절연막(미도시)를 포함한 상기 전체 구조의 상면에 제2감광막패턴(미도시)을 형성한다.Subsequently, as shown in FIG. 9, a second photoresist layer pattern (not shown) is formed on an upper surface of the entire structure including the interlayer insulating layer (not shown).
그다음, 상기 제2감광막패턴(미도시)을 마스크로 상기 층간산화막(미도시)과 상기 게이트 LDD용 산화막(미도시)을 상기 버퍼질화막(41)의 상면이 노출될 때까지 선택적으로 제거하여 상기 게이트 상측의 버퍼질화막(41) 부분 및 게이트들사이에만 남는 희생산화막패턴(43)을 형성한다. 이때, 상기 버퍼질화막(41)은 식각방지막 역활을 한다.Then, using the second photoresist pattern (not shown) as a mask, the interlayer oxide layer (not shown) and the gate LDD oxide layer (not shown) are selectively removed until the top surface of the buffer nitride layer 41 is exposed. A sacrificial oxide film pattern 43 remaining only between portions of the buffer nitride film 41 and the gates above the gate is formed. In this case, the buffer nitride layer 41 serves as an etch stop layer.
이어서, 도 10에 도시된 바와같이, 제2감광막패턴(미도시)을 제거하고, 상기 선택적으로 제거되고 남은 희생산화막패턴(43)을 포함한 전체 구조의 상면에 제1 스페이서용 질화막(미도시)을 에치백하여 상기 희생산화막패턴(43)측벽에 제1스페이서(45)를 형성한다.Next, as shown in FIG. 10, the second photoresist layer pattern (not shown) is removed, and the nitride film for the first spacer (not shown) is formed on the upper surface of the entire structure including the selectively removed remaining sacrificial oxide pattern 43. The first spacers 45 are formed on the sidewalls of the sacrificial oxide pattern 43 by etching back.
그다음, 도 11에 도시된 바와같이, 상기 희생산화막패턴(43)을 습식식각에 의해 완전히 제거한다.Next, as shown in FIG. 11, the sacrificial oxide film pattern 43 is completely removed by wet etching.
이어서, 도 12에 도시된 바와같이, 상기 희생산화막패턴(43)이 제거되고 남은 전체 구조의 상면에 제2스페이서용 질화막(미도시)을 증착하고, 상기 제2스페이서용 질화막(미도시)과 함께 상기 실리콘기판(31)상의 버퍼질화막(41)부분을 에치백하여 상기 제1스페이서(45)와 버퍼질화막(41)의 측면에 제2스페이서(47)을 형성한다. 이때, 상기 에치백 공정을 통해 상기 실리콘기판(31)상에 하부전극 콘택홀(39a)과 비트라인 콘택홀(49a)이 동시에 형성된다. 또한, 상기 제2스페이서(47) 형성시에, 상기 게이트상측의 버퍼질화막(41)상의 제1스페이서(45)사이에도 질화막 (47)이 채워진다. 이때, 상기 질화막(47)은 상기 게이트상측의 버퍼질화막(41)상의 제1스페이서(45)의 갭을 매립하는 정도의 두께로 증착한다.Next, as shown in FIG. 12, a second spacer nitride film (not shown) is deposited on the upper surface of the entire structure after the sacrificial oxide film pattern 43 is removed, and the nitride film for the second spacer (not shown) is formed. A portion of the buffer nitride film 41 on the silicon substrate 31 is etched back to form a second spacer 47 on the side of the first spacer 45 and the buffer nitride film 41. In this case, a lower electrode contact hole 39a and a bit line contact hole 49a are simultaneously formed on the silicon substrate 31 through the etch back process. In the formation of the second spacer 47, the nitride film 47 is also filled between the first spacers 45 on the buffer nitride film 41 on the gate side. In this case, the nitride film 47 is deposited to a thickness such that the gap of the first spacer 45 on the buffer nitride film 41 on the gate side is filled.
그다음, 도 13에 도시된 바와같이, 상기 하부전극 콘택홀(39a)과 비트라인 콘택홀(49a)을 포함한 전체 구조의 상면에 폴리실리콘층(미도시)을 증착하고, 상기도전물질층(미도시)을 전면식각 또는 CMP공정에 의해 선택적으로 제거하여 상기 하부전극 콘택홀(39a)과 비트라인 콘택홀(49a)내에 하부전극 콘택부 (51a) 와 비트라인콘택부(51b)를 각각 형성한다. 이때, 상기 전면 식각 또는 CMP공정시에 제2스페이서(47)와 제1스페이서(47)의 일부분이 제거된다.Next, as shown in FIG. 13, a polysilicon layer (not shown) is deposited on the upper surface of the entire structure including the lower electrode contact hole 39a and the bit line contact hole 49a, and the conductive material layer (not shown). C) is selectively removed by a front surface etch or a CMP process to form the lower electrode contact portion 51a and the bit line contact portion 51b in the lower electrode contact hole 39a and the bit line contact hole 49a, respectively. . At this time, a part of the second spacer 47 and the first spacer 47 is removed during the entire surface etching or CMP process.
이어서, 도면에는 도시하지 않았지만, 상기 하부전극콘택부(51a)와 비트라인콘택부(51b)와 각각 연결되는 하부전극과 비트라인을 형성하여 반도체소자를 완성한다.Subsequently, although not shown in the drawing, a lower electrode and a bit line connected to the lower electrode contact portion 51a and the bit line contact portion 51b are formed to complete the semiconductor device.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method according to the present invention has the following effects.
본 발명에 따른 반도체소자의 제조방법에 있어서는, 도 12에 도시된 바와같이, 게이트 LDD 용 스페이서 형성과 하부전극 콘택 형성을 일원화하므로써 실리콘기판의 손실을 감소시킬 수 있다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 12, the loss of the silicon substrate can be reduced by unifying the gate LDD spacer formation and the lower electrode contact formation.
따라서, 실리콘기판의 손실이 감소되어 게이트 숄드부의 마진이 증가되고, 게이트 숄더부의 전계가 감소되어 반도체소자의 리프레시 특성을 개선시킬 수 있다.Therefore, the loss of the silicon substrate is reduced, the margin of the gate shoulder portion is increased, and the electric field of the gate shoulder portion is reduced, thereby improving the refresh characteristics of the semiconductor device.
또한, 게이트 숄더부의 마진이 확보되기 때문에 별도로 게이트 숄더부의 마진을 확보하기 위해 스페이서 형성용 질화막을 증착할 필요가 없으므로 제조공정을 단순화시킬 수 있다.In addition, since the margin of the gate shoulder portion is secured, it is not necessary to deposit a nitride film for spacer formation to secure the margin of the gate shoulder portion, thereby simplifying the manufacturing process.
따라서, 스페이서 형성용 질화막을 증착할 필요가 없으므로 인해 하부전극콘택부의 마진을 충분히 확보할 수 있다.Therefore, it is not necessary to deposit a nitride film for spacer formation, thereby sufficiently securing the margin of the lower electrode contact portion.
그리고, 제1스페이서용 질화막과 게이트 LDD용 질화막이 모두 비트라인콘택부와 하부전극콘택부간의 분리에 효과적으로 이용되므로써 이들 상호간의 단락 마진을 충분히 확보할 수 있다.In addition, since both the first spacer nitride film and the gate LDD nitride film are effectively used for separation between the bit line contact portion and the lower electrode contact portion, short-circuit margins between them can be sufficiently secured.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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| KR100378689B1 (en) * | 1996-06-29 | 2004-09-04 | 주식회사 하이닉스반도체 | Method for forming contact of semiconductor device |
| KR100367501B1 (en) * | 1998-12-30 | 2003-04-23 | 주식회사 하이닉스반도체 | Method for forming self-align contact of semiconductor device |
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| KR100640639B1 (en) * | 2005-04-19 | 2006-10-31 | 삼성전자주식회사 | Semiconductor device having fine contact and method of manufacturing the same |
| US7855408B2 (en) | 2005-04-19 | 2010-12-21 | Samsung Electronics Co., Ltd. | Semiconductor device having fine contacts |
| US8242018B2 (en) | 2005-04-19 | 2012-08-14 | Samsung Electronics Co., Ltd. | Semiconductor device having fine contacts and method of fabricating the same |
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