KR20030002796A - Method for manufacturing reticle and forming overlay pattern - Google Patents
Method for manufacturing reticle and forming overlay pattern Download PDFInfo
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- KR20030002796A KR20030002796A KR1020010038505A KR20010038505A KR20030002796A KR 20030002796 A KR20030002796 A KR 20030002796A KR 1020010038505 A KR1020010038505 A KR 1020010038505A KR 20010038505 A KR20010038505 A KR 20010038505A KR 20030002796 A KR20030002796 A KR 20030002796A
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- reticle
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 정확한 오버레이 측정을 가능하게 하는 레티클 제조방법 및 이를 이용한 오버레이 패턴 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a reticle manufacturing method for enabling accurate overlay measurement and an overlay pattern forming method using the same.
일반적으로 사진공정에서 하지층과 상부층의 정렬도를 측정하기 위하여 오버레이 패턴(overlay pattern)을 형성하게 된다. 그러나, 사진공정 전에 실시하는 화학-물리적 연마(Chemical-Mechanical Polishing; CMP)와 같은 평탄화공정의 불균일로 인해 오버레이 패턴이 형성될 지역의 포토레지스트의 두께가 전체적으로 고르지 못하게 된다. 이를 도면을 참조하여 설명한다.In general, an overlay pattern is formed to measure the degree of alignment between the underlying layer and the upper layer in the photographic process. However, unevenness of the planarization process, such as chemical-mechanical polishing (CMP), which is performed before the photographing process, causes the overall thickness of the photoresist in the area where the overlay pattern is to be formed to be uneven. This will be described with reference to the drawings.
도 1a는 트랜지스터와 같은 소자(도시되지 않음)가 형성되어 있는 반도체기판(2) 상에 절연막(4)을 형성한 다음 CMP 공정을 실시하여 평탄화한 상태의 단면도이다. 도면 좌측은 셀이 형성되는 영역을 나타내고, 우측은 사진공정에서 하지층과 상부층의 정렬도를 측정하기 위하여 형성된 오버레이 패턴이 형성된 영역을 나타낸다. CMP가 불균일하게 이루어져 절연막(4)에 단차가 형성되어 있음을 알 수 있다.FIG. 1A is a cross-sectional view of a flattened state by forming an insulating film 4 on a semiconductor substrate 2 on which a device such as a transistor (not shown) is formed, and then performing a CMP process. The left side of the figure shows an area where cells are formed, and the right side shows an area on which an overlay pattern is formed to measure the degree of alignment between the base layer and the top layer in the photographic process. It can be seen that the CMP is nonuniform and a step is formed in the insulating film 4.
도 1b는 사진공정을 진행하기 위하여 포토레지스트(6)을 도포한 상태를 도시한 것으로, 절연막(4)의 단차에 의해 셀 영역에 비해 오버레이 패턴 영역에 포토레지스트(6)가 얇게 도포되었음을 알 수 있다.FIG. 1B illustrates a state in which the photoresist 6 is applied to proceed the photolithography process, and it can be seen that the photoresist 6 is thinly applied to the overlay pattern region compared to the cell region by the step of the insulating film 4. have.
이러한 상태에서 셀 영역 및 오버레이 패턴 영역에 동일한 에너지로 노광하면, 오버레이 패턴 영역의 포토레지스트가 상대적으로 얇기 때문에 과도노광(over expose)이 되어, 도 2a와 같은 박스 형태의 오버레이 패턴이 도 2b와 같이 라운딩되어 형성된다.In such a state, if the cell region and the overlay pattern region are exposed to the same energy, the photoresist of the overlay pattern region is relatively thin, resulting in over-exposure. Thus, a box-shaped overlay pattern as shown in FIG. It is rounded and formed.
도 2a는 레티클(reticle) 상의 오버레이 패턴을 나타낸 것으로, "10"은 크롬(Cr)이 코팅된 영역을 나타내고, "15"는 크롬(Cr)이 없는 영역을 나타낸다.2A shows an overlay pattern on a reticle, where "10" represents a region coated with chromium (Cr) and "15" represents an area without chromium (Cr).
도 2b는 상기 레티클을 이용한 사진공정을 진행하여 반도체기판 상에 오버레이 패턴(10a)을 형성한 상태를 도시한 것으로, 과도노광에 의해 오버레이 패턴이 라운드형으로 형성되었다.2B illustrates a state in which the overlay pattern 10a is formed on a semiconductor substrate by performing a photo process using the reticle, and the overlay pattern is formed in a round shape by overexposure.
오버레이 측정장비에서는 내부 박스(inner box)와 외부 박스(outer box)의 일정 면적을 스캐닝하여 오버레이 값을 측정하게 된다. 그러나, 종래의 방법에 의하면, 내부 박스와 외부 박스의 패턴이 일치하지 않아 오버레이 측정 에러를 유발하거나, 측정 문턱 면적(threshold area)(점선 부분)이 다르기 때문에 측정값 자체에 대한 신뢰성에 문제가 발생한다.In the overlay measuring device, an overlay value is measured by scanning a predetermined area of an inner box and an outer box. However, according to the conventional method, the pattern of the inner box and the outer box does not match, causing an overlay measurement error or a problem in reliability of the measured value itself due to different measurement threshold areas (dashed lines). do.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 본 발명이 이루고자 하는 기술적 과제는, 사진공정에서 오버레이 패턴이 라운딩되는 것을 방지하여 오버레이 정확도를 향상시킬 수 있는 레티클의 제조방법 및 오버레이 패턴 형성방법을 제공하는 데 있다.The present invention is to solve the problems of the prior art as described above, the technical problem to be achieved by the present invention, the manufacturing method and overlay pattern of the reticle to improve the overlay accuracy by preventing the overlay pattern is rounded in the photo process It is to provide a formation method.
도 1a는 CMP 공정이 불균일하게 이루어진 상태를 도시한 단면도이고, 도 1b는 포토레지스트가 도포된 상태를 도시한 단면도이다.FIG. 1A is a cross-sectional view showing a state in which a CMP process is unevenly formed, and FIG. 1B is a cross-sectional view showing a state in which a photoresist is applied.
도 2a 및 도 2b는 종래의 레티클 및 오버레이 패턴 형성방법을 설명하기 위한 도면들이다.2A and 2B are diagrams for describing a conventional reticle and overlay pattern forming method.
도 3a 및 도 3b는 본 발명에 의한 레티클 및 오버레이 패턴 형성방법을 설명하기 위한 도면들이다.3A and 3B are views for explaining a method of forming a reticle and an overlay pattern according to the present invention.
도 4는 본 발명의 오버레이 패턴을 이용한 오버레이 측정방법을 나타낸 것이다.4 illustrates an overlay measurement method using an overlay pattern of the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
2 : 기판 4 : 절연막2: substrate 4: insulating film
6 : 포토레지스트 10a,20a : 오버레이 패턴6: photoresist 10a, 20a: overlay pattern
10,20 : 크롬이 코딩된 영역10,20: Chrome coded area
15,25 : 크롬이 코팅되지 않은 영역15,25: chromium-free area
상기 과제를 이루기 위하여 본 발명에 의한 레티클 제조방법은, 차광물질이 코팅된 차광영역과, 상기 차광물질이 코팅되지 않은 투광영역으로 이루어진 오버레이 패턴을 구비하는 레티클의 제조방법에 있어서, 상기 차광영역을 복수개 형성하되, 바둑판 모양으로 배열하는 것을 특징으로 한다.In order to achieve the above object, the reticle manufacturing method according to the present invention, in the manufacturing method of the reticle having an overlay pattern consisting of a light shielding region coated with a light shielding material, and a light transmitting region not coated with the light shielding material, Form a plurality, characterized in that arranged in a checkered shape.
상기 과제를 이루기 위하여 본 발명에 의한 오버레이 패턴 형성방법은, 차광물질이 코팅된 차광영역과, 상기 차광물질이 배열되지 않은 투광영역이 바둑판 형태로 복수개 배열된 레티클을 이용하여 오버레이 패턴을 형성한다.In order to achieve the above object, in the overlay pattern forming method according to the present invention, an overlay pattern is formed using a light shielding region coated with a light shielding material and a reticle having a plurality of light transmitting regions in which the light shielding material is not arranged in a checkerboard shape.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 및 도 3b는 본 발명에 의한 레티클 및 오버레이 패턴 형성방법을 설명하기 위한 도면들이다.3A and 3B are views for explaining a method of forming a reticle and an overlay pattern according to the present invention.
먼저, 도 3a는 레티클 상의 오버레이 패턴을 도시한 것으로, "20"은 크롬(Cr)이 코팅된 영역을 나타내고, "25"는 크롬이 코팅되지 않은 영역을 나타낸다. 종래의 내부 박스 영역은 크롬(Cr)이 코팅되지 않았으며, 크롬(Cr)이 코팅된 영역과 그렇지 않은 영역이 바둑판 형태로 배열되어 있다. 이렇게 레티클 상에 오버레이 패턴을 형성할 때 크롬(Cr) 코팅된 차광영역을 복수 개로 하여 바둑판 형태로 배열하면, CMP 공정에서 균일도가 불량하여 하지층에 단차가 있더라도 노광공정에서 패턴이 라운딩되는 현상을 방지할 수 있다.First, FIG. 3A illustrates an overlay pattern on a reticle, where “20” represents a region coated with chromium (Cr) and “25” represents an area not coated with chromium. The conventional inner box area is not coated with chromium (Cr), and the areas coated with chromium (Cr) and other areas are arranged in a checkerboard shape. When the overlay pattern is formed on the reticle, if the chromium (Cr) coated light shielding area is arranged in the form of a checker board, the pattern is rounded in the exposure process even if there is a step in the underlying layer due to poor uniformity in the CMP process. You can prevent it.
도 3b는 본 발명의 오버레이 패턴이 형성된 레이클을 이용하여 반도체기판 상에 형성된 오버레이 패턴(20a)을 나타낸 것으로, 패턴의 라운딩 없이 정확하게 오버레이 패턴(20a)이 형성되었음을 알 수 있다.3B illustrates an overlay pattern 20a formed on a semiconductor substrate by using a rattle on which an overlay pattern of the present invention is formed, and it can be seen that the overlay pattern 20a is accurately formed without rounding the pattern.
도 4는 본 발명의 오버레이 패턴을 이용한 오버레이 측정방법을 나타낸 것으로, 외부 박스(B)와 내부 박스(A)에서의 오버레이를 측정할 때 문턱 면적(threshold area)의 차이에 의한 측정불량을 방지할 수 있으며, 정확한 오버레이 측정이 가능하여 미스얼라인(misalign)에 의한 소자의 단락 등을 방지할 수 있다.4 illustrates an overlay measurement method using the overlay pattern of the present invention, which prevents a measurement failure due to a difference in a threshold area when measuring an overlay in an outer box B and an inner box A. Referring to FIG. In addition, accurate overlay measurement can be prevented, such as shorting of the device due to misalignment.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
상술한 본 발명에 의한 레티클 제조방법 및 오버레이 패턴 형성방법에 의하면, 크롬(Cr) 코팅영역을 복수 개로 하여 바둑판 형태로 배열하면, CMP 공정에서 균일도가 불량하여 하지층에 단차가 있더라도 노광공정에서 패턴이 라운딩되는 현상을 방지할 수 있다. 따라서, 사진공정 후 오버레이를 측정할 때 문턱 면적(threshold area)의 차이에 의한 측정불량을 방지할 수 있으며, 정확한 오버레이 측정이 가능하여 미스얼라인(misalign)에 의한 소자의 단락 등을 방지할 수 있다.According to the reticle manufacturing method and the overlay pattern forming method according to the present invention described above, when a plurality of chromium (Cr) coating areas are arranged in the form of a checkerboard, the pattern in the exposure process even if there is a step in the underlying layer due to poor uniformity in the CMP process This rounding phenomenon can be prevented. Therefore, when measuring the overlay after the photo process, it is possible to prevent the measurement failure due to the difference of the threshold area, and to accurately measure the overlay to prevent the short circuit of the device due to misalignment. have.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010038505A KR20030002796A (en) | 2001-06-29 | 2001-06-29 | Method for manufacturing reticle and forming overlay pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010038505A KR20030002796A (en) | 2001-06-29 | 2001-06-29 | Method for manufacturing reticle and forming overlay pattern |
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| Publication Number | Publication Date |
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| KR20030002796A true KR20030002796A (en) | 2003-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020010038505A KR20030002796A (en) | 2001-06-29 | 2001-06-29 | Method for manufacturing reticle and forming overlay pattern |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105759564A (en) * | 2016-03-17 | 2016-07-13 | 京东方科技集团股份有限公司 | Mask and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5533634A (en) * | 1994-09-01 | 1996-07-09 | United Microelectronics Corporation | Quantum chromeless lithography |
| KR19980025509A (en) * | 1996-10-02 | 1998-07-15 | 김영환 | How to check the optimal focus of the exposure equipment |
| KR0158904B1 (en) * | 1994-12-02 | 1999-02-01 | 김주용 | Contact mask |
| KR20010058603A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method for forming semiconductor device capable of improving reliability of overlay accuracy measurement |
| JP2001296650A (en) * | 2000-04-17 | 2001-10-26 | Nec Corp | Reticle |
-
2001
- 2001-06-29 KR KR1020010038505A patent/KR20030002796A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5533634A (en) * | 1994-09-01 | 1996-07-09 | United Microelectronics Corporation | Quantum chromeless lithography |
| KR0158904B1 (en) * | 1994-12-02 | 1999-02-01 | 김주용 | Contact mask |
| KR19980025509A (en) * | 1996-10-02 | 1998-07-15 | 김영환 | How to check the optimal focus of the exposure equipment |
| KR20010058603A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method for forming semiconductor device capable of improving reliability of overlay accuracy measurement |
| JP2001296650A (en) * | 2000-04-17 | 2001-10-26 | Nec Corp | Reticle |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105759564A (en) * | 2016-03-17 | 2016-07-13 | 京东方科技集团股份有限公司 | Mask and manufacturing method thereof |
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