KR20030002710A - Method for manufacturing a flash memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a flash memory device is provided to increase a coupling ratio of a gate and improve a programming/erasing characteristic of the memory device by improving the profile of an isolation layer while preventing a moat from being generated in the edge of the isolation layer. CONSTITUTION: A pad oxide layer is formed on a semiconductor substrate(300). A well ion implantation process and a threshold voltage control ion implantation process are performed. After the pad oxide layer is removed, a tunnel oxide layer(320), the first polysilicon layer, a buffer oxide layer and a pad nitride layer are sequentially formed. A trench is formed in a predetermined region for the isolation layer. A sacrificial oxide layer is formed on the resultant structure. A high temperature thermal oxide process is performed to form a thermal oxide in the buffer oxide layer on the sidewall of the trench and the tunnel oxide layer such that the thermal oxide is thicker as compared with other regions. A high density plasma(HDP) oxide layer(360) is formed to completely fill the inside of the trench. The HDP oxide layer is planarized to expose the pad nitride layer. The pad nitride layer and the buffer oxide layer are sequentially eliminated. The second polysilicon layer is formed on the resultant structure and is etched to expose the upper portion of the HDP oxide layer. A dielectric layer and the third polysilicon layer(380) are sequentially formed.

Description

Method for manufacturing a flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device in which the profile of the device isolation film is improved and the damage near the edge of the device isolation film is reduced.

Typical flash memory devices consist of a drain, a source, a floating gate and a control gate. The principle of storing or erasing data in a flash memory device will be briefly described. A predetermined voltage is applied to a drain, a source, and a control gate of a flash memory device, and according to the applied voltage, FN tunneling or a hot carrier is performed. ) Is generated and electrons are injected into the floating gate or electrons are emitted from the floating gate. Data is stored or erased as electrons are injected into or floating from the floating gate. Currently used methods for storing electrons in the floating gate or emitting electrons from the floating gate include hot electron injection and F-N tunneling. Dual hot electron injection methods are used for data programming. Factors affecting data programming characteristics include gate length and tunnel oxide thickness of a flash memory device. The FN tunneling method is used for the data erase operation, and the factor influencing the data erase operation is the gate coupling ratio, which is the ratio of the capacitance between the floating gate and the control gate to the total capacitance of the memory cell. The higher the gate coupling ratio, the better the erase characteristics of the memory device.

The formula for calculating the gate coupling ratio is shown in Equation 1 below, see FIG. 1.

kg = Cg / Ct,

Here, kg is a gate coupling ratio, and the kg value of most flash memory devices has a value of about 0.50 to 0.60.

Ct is the total capacitance, where Ct = Cg + Cd + Cs + Cb + Cf,

Cg is a capacitance mainly due to the ONO layer, and the capacitance between the control gate and the floating gate,

Cd is the overlap capacitance of the floating gate and drain junction,

Cs is the overlap capacitance of the floating gate and source junction,

Cb is the capacitance of the tunnel oxide film between the floating gate and the substrate,

Cf is the capacitance by free charge.

The reason why the gate coupling ratio is important in the erase operation of the memory cell is that the voltage VG applied to the control gate is represented by the voltage VFG, where VFG = kg * VG, applied to the floating gate. Since F-N tunneling is a method in which electrons are transferred by the voltage difference between the control gate and the substrate, the F-N tunneling is actually dependent on the bias voltage applied to the floating gate. Therefore, factors affecting the gate coupling ratio are the thickness of the ONO layer and the area of the ONO layer surrounding the substrate and the floating gate. This value is most affected by the capacitance of the ONO layer. In the conventional flash memory device, since the pad nitride is about 1,200 microns in thickness, there is almost no step between the field region and the active region after the nitride film removing process (approximately 700 microseconds), so the area of the ONO layer formed on the upper portion of the device isolation layer is not big. This causes a problem in the data erasing operation because the capacitance Cg of the ONO layer is small and thus the gate coupling ratio is small. When NSLOCOS is used, the kg value is about 0.60, but when STI is applied, kg is about 0.55. 2 is a cross-sectional view of a flash memory device according to the prior art. Referring to FIG. 2, a moat (denoted as “A”) in which the field region (element isolation layer) 100 and the gate oxide layer 120 at the boundary of the active region 110 slightly sinks is generated. Such a moot also reduces the gate coupling ratio. Because the area of the active region in contact with the tunnel oxide is increased by the moat portion, the Cs value and the Cd value are increased to lower the gate coupling ratio. Therefore, there is a need for a method of forming an isolation layer that can form a level difference in the field region and the active region so as to increase the area of the ONO layer and prevent the occurrence of the moat.

In order to overcome the above problems, an object of the present invention is to improve the profile of the device isolation film by increasing the thickness of the pad nitride and forming a thermal oxide on the sidewalls of the trench when forming the device isolation film of the flash memory device, the edge of the device isolation film It is to prevent the generation of the moiety in the (edge) portion, to increase the gate coupling ratio, and consequently to improve the program and erase characteristics of the memory device.

1 is a diagram of visually distinguishing capacitance in each layer region of a flash memory device;

2 is a cross-sectional view of a flash memory device of the prior art for showing the moat generated in the device isolation film.

3A to 3E are cross-sectional views sequentially illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

300: semiconductor substrate 320: tunnel oxide film

330a and 330b: first and second polysilicon layers 340: buffer oxide film

350: pad nitride film 360: HDP oxide film

370: ONO layer 380: third polysilicon layer

A method of manufacturing a flash memory device of the present invention includes the steps of forming a pad oxide film on a semiconductor substrate; Performing well ion implantation and threshold voltage adjusting ion implantation; Removing the pad oxide layer and sequentially forming a tunnel oxide layer, a first polysilicon layer, a buffer oxide layer, and a pad nitride layer; Forming a trench in a predetermined region where an isolation layer is to be formed; Forming a sacrificial oxide layer on the trench sidewalls; Performing a high temperature thermal oxidation process to form a thick thermal oxide in the buffer oxide and tunnel oxide portions of the sidewalls of the trench, compared to other regions; Forming an HDP oxide film to completely fill the inside of the trench; Planarizing the HDP oxide film to expose the pad nitride film; Sequentially removing the pad nitride film and the buffer oxide film; Forming a second polysilicon layer on the entire structure; And etching the second polysilicon layer to expose the upper portion of the HDP oxide layer, and then sequentially forming a dielectric layer and a third polysilicon layer.

An embodiment of the present invention will now be described in detail with reference to FIGS. 3A-1E.

First, referring to FIG. 3A, a pad oxide film (not shown) is formed on the semiconductor substrate 300. The pad oxide 310 is preferably about 50 GPa thick. Well ion implantation and threshold voltage regulation ion implantation are performed on the pad oxide film. Thereafter, all of the pad oxide film is etched and removed, and then, the tunnel oxide film 320 is formed to a thickness of about 80 kPa to about 100 kPa by an oxidation process. After that, the first polysilicon layer 330 is formed to a thickness of about 300 to 600 kPa, and the buffer oxide film 340 is formed thereon to a thickness of about 50 to 100 kPa. Subsequently, the pad nitride film 350 is formed on the buffer oxide film 340 to a thickness of approximately 3,600 kPa. In the conventional method, the field region becomes lower than the active region after the process of forming the pad nitride film to a thickness of approximately 1,200 GPa and subsequent planarization and removal of the pad nitride film. In the present invention, in order to prevent this, the thickness of the pad nitride film 350 is greatly increased to 3,600 Å so that the field area is formed higher than the active area even after the nitride film etching process, so that the area of the subsequent ONO layer is deposited.

Referring to FIG. 3B, a photoresist layer is coated, exposed, and developed to form a trench in a region where the device isolation layer is to be formed, thereby forming a photoresist pattern. The trench is etched to the lower semiconductor substrate using this photoresist pattern as a mask. The photoresist pattern is then removed and a sacrificial oxide film (not shown) is formed over the entire structure. Subsequently, a high temperature thermal oxidation process is applied to form an oxide film having a thickness of 100 GPa to 200 GPa on the trench sidewall. At this time, a portion of the trench sidewall contacting the buffer oxide layer 340 and the tunnel oxide layer 320 is formed with a thermal oxide thicker than the other portion. The thick oxide formed in this way prevents the moat from being generated at the edge of the device isolation film to be formed later. Thereafter, the HDP oxide layer 360 is formed to a thickness of about 6,000 to 10,000 Å so as to completely fill the inside of the trench. The HDP oxide layer 360 is planarized by a CMP process to expose the lower pad nitride layer 350. This HDP oxide film 360 is later used as the device isolation film.

Referring to FIG. 3C, the pad nitride film 350 is removed, and the buffer oxide film 340 is removed by a cleaning process using BOE. Then, the first polysilicon layer 330a is exposed.

Referring to FIG. 3D, a second polysilicon layer 330b is formed on the first polysilicon layer. A double layer of the first polysilicon layer 330a and the second polysilicon layer 330b is used together as a floating gate. At this time, the thickness of the second polysilicon layer 330b is appropriately about 300 kPa to 600 kPa. Then, a photoresist layer is deposited, exposed to light, and developed to expose the upper portion of the HDP oxide film (device isolation film) 360 to form a photoresist pattern. Using the photoresist pattern as a mask, the second polysilicon layer and the first polysilicon layer on the HDP oxide film 360 are etched, and then the photoresist pattern is removed.

Referring to FIG. 3E, a triple layer 370 of ONO is deposited on the entire structure. Here, the triple layer 370 of ONO is formed with a thickness of approximately 40 kPa to 60 kPa, respectively. Then, the third polysilicon layer 380 is formed to a thickness of approximately 2,000 kPa to 5,000 kPa. The third polysilicon layer 380 is planarized by a CMP process.

According to the present invention, since the gate coupling ratio of the flash memory device can be increased to about 0.75, channel programming can be performed by FN tunneling, so that the program can be distributed in a desired state by using a desired program mode. . In addition, since the polysilicon layer is formed as a double layer, since the volume of the floating gate is large, random fail that may appear in the highly integrated device can be greatly reduced.

The invention is not limited to the embodiments illustrated above but may be variously applied or modified by those skilled in the art within the scope of the following claims.

As described above, according to the present invention, when forming a device isolation film of a flash memory device, a pad nitride film is formed thicker to form a device isolation film higher than an active region, thereby increasing the formation area of the ONO layer, and forming a thermal oxide on the sidewalls of the trench. As a result, the profile of the device isolation layer may be improved, and at the same time, the occurrence of the moor at the edge portion of the device isolation layer may be prevented, thereby increasing the gate coupling ratio and consequently improving the program and erase characteristics of the memory device.

Claims (12)

Forming a pad oxide film on the semiconductor substrate; Performing well ion implantation and threshold voltage adjusting ion implantation; Removing the pad oxide layer and sequentially forming a tunnel oxide layer, a first polysilicon layer, a buffer oxide layer, and a pad nitride layer; Forming a trench in a predetermined region where an isolation layer is to be formed; Forming a sacrificial oxide film over the entire structure; Performing a high temperature thermal oxidation process to form a thick thermal oxide in the buffer oxide and tunnel oxide portions of the sidewalls of the trench, compared to other regions; Forming an HDP oxide film to completely fill the inside of the trench; Planarizing the HDP oxide film to expose the pad nitride film; Sequentially removing the pad nitride film and the buffer oxide film; Forming a second polysilicon layer on the entire structure; And And etching the second polysilicon layer to expose an upper portion of the HDP oxide layer, and then sequentially forming a dielectric film and a third polysilicon layer. The method of manufacturing a flash memory device according to claim 1, wherein the pad oxide film is formed to a thickness of 50 kHz. The method of claim 1, wherein the tunnel oxide layer is formed to a thickness of 80 kV to 100 kV. The method of claim 1, wherein the first polysilicon layer is formed to a thickness of about 300 kPa to about 600 kPa. The method of claim 1, wherein the buffer oxide layer is formed to a thickness of about 50 μs to about 100 μs. The method of claim 1, wherein the pad nitride layer is formed to a thickness of about 3,000 to 4,000 μm. The method of claim 1, wherein the high temperature thermal oxidation process forms an oxide film having a thickness of about 100 μs to about 200 μs on a sidewall of the trench. The method of claim 1, wherein the HDP oxide layer is formed to a thickness of 6,000 kV to 10,000 kV. The method of claim 1, wherein the HDP oxide film is planarized by a CMP process. The method of claim 1, wherein the buffer oxide film is removed by a cleaning process using BOE. The method of claim 1, wherein the second polysilicon layer is formed to a thickness of about 300 kPa to about 600 kPa. The method of claim 1, wherein the third polysilicon layer is formed to a thickness of 2,000 kV to 5,000 kPa.