KR20030002080A - Method of realizing test pattern of semiconductor device - Google Patents

Abstract

PURPOSE: A test pattern embodiment method semiconductor devices is provided to estimate an SM(Stress Migration) of metallization by entirely eliminating an EM(ElectroMigration) using a current-tab. CONSTITUTION: A current-tab composed of a slot via(10) or contact array is provided with a via array. A metal interconnection(20) is formed on upper part of the current-tab so as to connect with the current-tab, thereby forming a test pattern of a stress migration. At this time, the length of the metal interconnection(20) is defined to a very short critical length without generating an EM(Elecromigration). Preferably, the length of the metal interconnection(20) is used of a bleach length. Also, the slot via(10) has a different aspect ratio between a width(X) and a length(Y).

Description

Method of realizing test pattern of semiconductor device

The present invention relates to a method of implementing a test pattern of a semiconductor device, and more particularly, to a technique of constructing a stress migration test pattern using a two-level metallization process using a via array.

In the metallization process, the tungsten (W) plug forming process is a very useful process, and many semiconductor manufacturers employ it in their products. However, an evaluation tool capable of verifying defects and failures resulting from the interface due to the difference between the Al wiring and the W property exists only by indirect measurement by an electromigration (EM) evaluation. Did not do it.

The prior art is described as follows. In general, there is no pattern to evaluate the stress migration (SM) by separating the contact interface of the tungsten plug of the contact or via and the aluminum wiring separately. In the case of SM for aluminum wiring, the SM can be applied to the SM by continuously applying a thermal cycle on a straight line as shown in FIG. 1 or by flowing a very low current at high temperature to monitor the resistance. Detects a failure

However, these methods are very time consuming and it is difficult to identify the correct SM by adding the EM effect in addition to the SM effect. Therefore, there are almost no patterns for extracting SM effects in a short time. As a result, in most cases, EM evaluation is performed to include SM effects in EM evaluation using EM evaluation patterns rather than accurate extraction of SM. However, the conventional EM evaluation pattern has a problem that the end of the aluminum pad is connected to the aluminum pad, so that the aluminum pad becomes an infinite supply source of aluminum to delay the generation of the SM effect.

The present invention is to solve the above problems, to configure the two or more vias or contact chains using a current-tab consisting of a slot via or a contact array (contact array) and the current tap By defining the metal wire connected to the wire as a very short critical length that does not generate EM, it completely excludes the effect of EM so that SM characteristics of tungsten / aluminium interface and aluminum or copper wire itself can be extracted. The purpose is to provide a test pattern implementation method.

1 is a plan view showing a conventional test pattern,

2 is a view showing the configuration of an SM test pattern according to the present invention;

3 is a plan view showing a current tap formed of a slot via according to the present invention;

4 is a plan view showing a current tap made of a conventional via;

* Explanation of symbols for main parts of the drawings

10: slot via 20: metal wiring

The present invention for achieving the above object is characterized in that the current tab is configured as a via array, and a metal wire of a predetermined length is formed on the current tab so as to be connected to the current tab to form a stress migration test pattern.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 shows a configuration of an SM test pattern according to the present invention. As shown, the present invention configures two or more vias (or contact chains) using current taps formed of slot vias 10 (or contact arrays), and connects the metal taps (copper and aluminum) to the current taps. (20) is defined as a very short critical length so that EM does not occur to completely exclude the EM effect. For example, the length of the metal wiring is preferably defined as 10㎛ using the length of the bleach (Blech).

In this way, if the test pattern is constructed using the EM's Blech theory, the SM due to the difference in the characteristics of the interface between the via and the metal wiring, which excludes the EM phenomenon, and the SM due to the metal wiring itself can be verified without the EM effect. Can be.

Each of the slot vias 10 configures an aspect ratio of width X and length Y differently. The reason for configuring the current tap using an array of slot vias having different aspect ratios of X and Y is that the following patterning problem occurs when using a conventional general via.

1) As chip size becomes smaller and design rules become smaller, the mask used in the lithography process is changing from the conventional binary method to using PSM (phase shift mask). In this case, when configuring multiple via arrays, the pattern between vias should be defined more than twice the via CD. Therefore, it becomes difficult to construct a dense via array (see FIG. 4B).

2) In the case of a wiring having a width substantially similar to or smaller than the CD of the via, there is a high possibility of leaving the via area due to lack of overlay margin (see FIG. 4A). However, if the CD of the via is increased, the X and Y both become larger and increase in size. Therefore, during the tungsten etchback process, there is a high possibility that all the tungsten in the wide via is lost. In addition, the test pattern should have a small overlap margin between the via and the metal wiring as much as possible. However, in the case of the conventional via, patterning is difficult due to the above problem.

However, when using an array of slot vias having different aspect ratios of X and Y as in the present invention, the above-described problems 1) and 2) can be solved simultaneously. As shown in Fig. 3, the spacing between the slot vias needs to be secured only by the width direction CD (X CD) of the slot via, so that a tight via array can be configured as much (see D in Fig. 3). In addition, since the width of the metal wiring is also much larger than the width of the metal wiring in the longitudinal CD (Y CD) of the slot via (see C of FIG. 3), the problem of overlap or alignment margin can also be solved.

The SM measurement method using the SM test pattern configured as described above is similar to the EM evaluation method, which continuously applies a constant DC current and temperature and observes a resistance change of the wiring by using a voltage measuring tap to generate a resistance change over a certain ratio. View the point of view as a failure time.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, even when a high current density is applied, only the SM effect due to the SM of the wiring and the delamination of the upper and lower interfaces of the via and the like can be monitored, and the SM evaluation that can take more than a year can be completed in a short time. have. In addition, by using Joule heating caused by the current density, it is possible to apply the temperature by Joule heating itself without applying a certain temperature to the specimen. In addition to the continuous temperature application, by periodically applying the current itself, SM evaluation by periodic heat treatment by periodic joule heating becomes possible.

Claims (5)

And forming a stress migration test pattern by forming a current tab in a via array and forming a metal wire having a predetermined length on the current tab so as to be connected to the current tab. The method of claim 1, And wherein the current tap is formed of a slot via or a contact array. The method of claim 2, And the slot vias have different width and length aspect ratios. The method of claim 1, And the metal wiring is formed to have a critical length at which EM does not occur. The method of claim 4, wherein The length of the metal wiring is a test pattern implementation method of a semiconductor device characterized in that it is defined as 10㎛ using the bleach length.