KR20030001873A - Method for forming trench in semiconductor device - Google Patents

Method for forming trench in semiconductor device Download PDF

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Publication number
KR20030001873A
KR20030001873A KR1020010037733A KR20010037733A KR20030001873A KR 20030001873 A KR20030001873 A KR 20030001873A KR 1020010037733 A KR1020010037733 A KR 1020010037733A KR 20010037733 A KR20010037733 A KR 20010037733A KR 20030001873 A KR20030001873 A KR 20030001873A
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South Korea
Prior art keywords
trench
film
forming
insulating film
contact hole
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KR1020010037733A
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Korean (ko)
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최익수
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주식회사 하이닉스반도체
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Priority to KR1020010037733A priority Critical patent/KR20030001873A/en
Publication of KR20030001873A publication Critical patent/KR20030001873A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

PURPOSE: A trench formation method of semiconductor devices is provided to prevent a fence and faceting by forming selectively a polymer film on a contact hole. CONSTITUTION: The first insulating layer(22), an etch stopper(24) and the second insulating layer(26) are sequentially stacked on a substrate(20). A contact hole(30) is formed by selectively etching the second insulating layer(26), the etch stopper(24) and the first insulating layer(22), and a polymer film is simultaneously formed on the exposed substrate(20) in the contact hole. A trench is formed by etching the second insulating layer(26). The polymer film is formed by mixed gases of C4F8, CH3F and Ar in HDP(High Density Plasma) CVD.

Description

반도체 소자의 트랜치 형성방법{METHOD FOR FORMING TRENCH IN SEMICONDUCTOR DEVICE}Trench Formation Method of Semiconductor Device {METHOD FOR FORMING TRENCH IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 트랜치 형성방법에 관한 것으로, 보다 구체적으로는 트랜치 형성시 발생되는 펜스(fence)의 발생을 억제할 수 있는 반도체 소자의 트랜치 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a trench in a semiconductor device, and more particularly, to a method for forming a trench in a semiconductor device capable of suppressing the occurrence of a fence generated during trench formation.

일반적으로 금속 라인을 형성하는 경우, 콘택과 충분한 오버레이 마진을 갖도록 디자인을 해야하지만, 패턴 사이즈가 감소함에 따라 이를 고려하기 어렵게 되었다. 또한, 노광장비의 한계때문에 성공적으로 공정을 수행하기가 어렵다.In general, when forming a metal line, it is necessary to design to have a contact and sufficient overlay margin, but this is difficult to consider as the pattern size decreases. In addition, due to the limitations of the exposure equipment, it is difficult to perform the process successfully.

이러한 노광장비의 한계를 극복하기 위한 기술로, 셀프 얼라인 콘택(SAC) 및 듀얼 다마신(DUAL DAMASCENE) 기술이 그 대안으로 대두되고 있다.As a technique for overcoming the limitations of the exposure equipment, self-aligned contact (SAC) and dual damascene (DUAL DAMASCENE) technologies are emerging as alternatives.

도 1a 내지 도 1c는 종래의 다마신 기술을 이용한 트랜치 형성방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a trench forming method using a conventional damascene technique.

도 1a에 도시된 바와같이, 금속라인(2)이 형성된 기판(1)상에 제1 절연막(3), 질화막(4) 및 제2 절연막(5)을 적층하여 형성한다. 이어서, 제2 절연막(5), 질화막(4), 및 제1 절연막(3)을 차례로 패터닝하여 콘택홀(6)을 형성한다.As shown in FIG. 1A, the first insulating film 3, the nitride film 4, and the second insulating film 5 are stacked on the substrate 1 on which the metal lines 2 are formed. Next, the second insulating film 5, the nitride film 4, and the first insulating film 3 are sequentially patterned to form the contact hole 6.

그 다음, 도 1b에 도시된 바와같이, 제2 절연막(5) 상부 및 콘택홀(6) 내에 기판(1) 또는 금속라인(2)의 어텍을 방지하기 위하여 유기성 반사방지막(O-BARC)(7)을 코팅한다. 반사방지막(7)은 플로잉(flowing)이 좋아 콘택홀 상부 부위에서의 코팅이 얇게 된다.Next, as shown in FIG. 1B, an organic anti-reflective coating (O-BARC) (to prevent attack of the substrate 1 or the metal line 2 in the upper portion of the second insulating film 5 and the contact hole 6). 7) coating. The anti-reflection film 7 has a good flow (flow), the thin coating on the upper portion of the contact hole.

그 다음, 도 1c에 도시된 바와같이, 반사방지막(7) 상에 트랜치 형성영역을한정하는 감광막 패턴(8)을 형성하고, 감광막 패턴(8)을 식각 마스크로 반사방지막(7)과 제2 절연막(5)을 차례로 식각하여 트랜치(10)를 형성한다.Next, as shown in FIG. 1C, a photoresist pattern 8 defining a trench formation region is formed on the antireflection film 7, and the antireflection film 7 and the second photoresist pattern 8 are etched using an etch mask. The insulating film 5 is sequentially etched to form the trench 10.

이후 도면에는 도시하지 않았지만, 감광막 패턴(8) 및 반사방지막(7)을 제거한 다음, 금속막을 트랜치(10)내에 갭필하여 금속배선 공정을 진행한다.Subsequently, although not shown in the drawing, the photoresist pattern 8 and the anti-reflection film 7 are removed, and then the metal film is gap-filled into the trench 10 to proceed with the metal wiring process.

그러나, 상기 트랜치(10) 형성시 제2 절연막(5)과 질화막(4)간의 식각 선택비를 높여주기 위한 조성으로 CH2F2또는 CHF3등의 가스를 사용하여 식각을 수행하는데, 이때 반사방지막(7)의 식각선택비가 높아 거의 식각이 않된다.However, when forming the trench 10, etching is performed using a gas such as CH 2 F 2 or CHF 3 to increase the etching selectivity between the second insulating film 5 and the nitride film 4. The etching selectivity of the protective film 7 is high, so that almost no etching is performed.

이는 CH2F2또는 CHF3등의 카본 계열에 의해 폴리머 부산물이 발생하고, 반사방지막(7)상에 상기 폴리머 부산물이 형성되어 도 1c에 도시된 바와같이 질화막(4)과 콘택홀(6)이 인접한 부근에서 뿔 모양의 펜스(fence)(15)를 이룬다. 이러한 펜스(15)의 영향으로 인해 후속 금속막 증착시 증착불량이 야기되어 콘택홀의 전기적 연결 불량이 발생하게 된다.The polymer by-products are generated by carbon series such as CH 2 F 2 or CHF 3 , and the polymer by-products are formed on the anti-reflection film 7, so that the nitride film 4 and the contact hole 6 are shown in FIG. 1C. In this adjacent vicinity, a horn shaped fence 15 is formed. Due to the influence of the fence 15, poor deposition occurs during subsequent metal film deposition, resulting in a poor electrical connection of the contact hole.

또한, 도면에는 도시하지 않았지만, 통상적인 식각인 경우 상기 반사방지막의 식각 속도가 절연막에 비해 매우 느리기 때문에 상기 제1 절연막의 모서리 부위가 과도하게 식각되어 퍼시팅(FACETING)이 발생하게 된다.In addition, although not shown in the drawing, since the etching rate of the anti-reflection film is very slow compared to the insulating film in the case of the conventional etching, the edge portion of the first insulating film is excessively etched to cause faceting.

따라서, 상기 문제점을 해결하기 위한 본 발명의 목적은, 트랜치 형성시 발생될 수 있는 펜스(fence)의 형성을 방지하여 안정된 금속라인을 형성할 수 있도록 하는 반도체 소자의 트랜치 형성방법을 제공하는 것이다Accordingly, an object of the present invention for solving the above problems is to provide a trench forming method of a semiconductor device to form a stable metal line by preventing the formation of a fence (fence) that can occur when forming the trench.

도 1a 내지 도 1c는 종래의 반도체 소자의 트랜치 형성방법을 설명하기 위한 제조공정도.1A to 1C are manufacturing process diagrams for explaining a trench forming method of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명의 반도체 소자의 트랜치 형성방법을 설명하기 위한 제조공정도.2A to 2C are manufacturing process diagrams for explaining the trench formation method of the semiconductor device of the present invention.

* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings

20 : 기판20: substrate

22 : 제1 절연막22: first insulating film

24 : 식각정지막24: etch stop film

26 : 제2 절연막26: second insulating film

28 : 감광막 패턴28 photosensitive film pattern

30 : 콘택홀30: contact hole

50 : 폴리머막50: polymer film

100 : 트랜치100: trench

상기 목적 달성을 위한 본 발명의 반도체 소자의 트랜치 형성방법은, 기판상에 제1 절연막, 식각정지막, 및 제2 절연막을 차례로 적층하여 형성하는 단계; 상기 제2 절연막, 식각정지막, 및 제1 절연막을 패터닝하여 상기 기판을 노출시키는 콘택홀을 형성하면서, 상기 콘택홀내의 노출된 기판상에 폴리머막을 형성하는 단계; 및 상기 제2 절연막을 패터닝하여 트랜치를 형성하는 단계를 포함하는 것을 특징으로 한다.A trench forming method of a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a first insulating film, an etch stop film, and a second insulating film on the substrate in order; Forming a polymer film on the exposed substrate in the contact hole while forming a contact hole for exposing the substrate by patterning the second insulating film, the etch stop film, and the first insulating film; And forming a trench by patterning the second insulating layer.

이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

도 2a 내지 도 2c는 본 발명의 반도체 소자의 트랜치 형성방법을 설명하기 위한 제조공정도이다.2A to 2C are manufacturing process diagrams for explaining the trench formation method of the semiconductor device of the present invention.

먼저, 도 2a에 도시된 바와같이, 기판(20)상에 제1 절연막(22), 식각정지막(24), 예컨대 질화막 및 제2 절연막(26)을 차례로 적층하여 형성한다. 그 다음, 제2 절연막(26)상에 기판(20)상의 콘택 영역을 한정하는 감광막 패턴(28)을 형성한다.First, as shown in FIG. 2A, a first insulating film 22, an etch stop film 24, for example, a nitride film and a second insulating film 26 are sequentially formed on the substrate 20. A photoresist pattern 28 is then formed on the second insulating film 26 to define the contact region on the substrate 20.

그 다음, 도 2b에 도시된 바와같이, 감광막 패턴(28)을 식각 마스크로 제2 절연막, 식각정지막(24), 및 제1 절연막(22)을 차례로 식각하여 기판(20)의 소정부분을 노출시키는 콘택홀(30)을 형성한다. 이때, 상기 콘택홀(30) 형성시 콘택홀 내의 노출된 기판(20)상에 폴리머막(50)이 형성되도록 하여, 후속 공정시 서브-어텍(SUB-ATTACK)을 방지하도록 한다.Next, as shown in FIG. 2B, the second insulating film, the etch stop film 24, and the first insulating film 22 are sequentially etched using the photoresist pattern 28 as an etch mask to remove a predetermined portion of the substrate 20. A contact hole 30 for exposing is formed. At this time, the polymer film 50 is formed on the exposed substrate 20 in the contact hole when the contact hole 30 is formed, thereby preventing the sub-attack (SUB-ATTACK) in the subsequent process.

이러한 폴리머막(50)은 고밀도 플라즈마 증착장비에서 C4F8, CH3F 및 Ar의 혼합가스에 의해 형성되거나, C2F6및 Ar의 혼합가스에 의해 형성되며, 바람직하게 500 ~ 10000Å의 두께로 형성된다.The polymer film 50 is formed by a mixed gas of C 4 F 8 , CH 3 F and Ar in a high density plasma deposition apparatus, or is formed by a mixed gas of C 2 F 6 and Ar, preferably 500 ~ 10000Å It is formed in thickness.

또한, 상기 폴리머막(50)은 고밀도 플라즈마 증착장비내에 구비되는 실리콘-루프(Si-ROOF)의 온도를 200 ~ 300℃로 설정하여, 상기 혼합가스 중 F 가스를 소모시킴으로써 생성되는 다량의 카본 계열의 가스를 이용하여 형성될 수도 있다. 이어서, 감광막 패턴(28)을 제거한다.In addition, the polymer film 50 is a silicon-loop (Si-ROOF) of the high-density plasma deposition equipment is set to a temperature of 200 ~ 300 ℃, a large amount of carbon-based produced by consuming F gas in the mixed gas It may be formed using a gas of. Next, the photosensitive film pattern 28 is removed.

그 다음, 도 2c에 도시된 바와같이, 제2 절연막(26)상에 트랜치 형성영역을 한정하는 감광막 패턴(미도시)을 형성한 다음, 상기 감광막 패턴을 식각 마스크로 제2 절연막(26)을 패터닝하여 트랜치(100)를 형성한다.Next, as shown in FIG. 2C, a photoresist pattern (not shown) defining a trench formation region is formed on the second insulating layer 26, and then the second insulating layer 26 is formed using the photoresist pattern as an etching mask. Patterning to form the trench (100).

이하, 도면에는 도시하지 않았지만, 상기 폴리머막(50)을 제거한 후, 트랜치(100) 내에 금속막을 갭필하여 금속라인 형성공정을 진행한다.Hereinafter, although not shown in the drawing, after the polymer film 50 is removed, a metal line is gap-filled in the trench 100 to form a metal line.

상술한 실시예에서는 기판(20)상에 폴리머막(50)을 형성하여 트랜치(100)를 형성하였지만, 기판(20)상에 금속라인을 형성한 후, 상기 금속라인 상에 폴리머막을 형성하여 트랜치를 형성할 수도 있다.In the above-described embodiment, the trench 100 is formed by forming the polymer film 50 on the substrate 20. However, after forming the metal line on the substrate 20, the trench is formed by forming the polymer film on the metal line. May be formed.

한편, 이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible in the technical field of the present invention that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상술한 본 발명의 반도체 소자의 트랜치 형성방법에 의하면, 트랜치 형성시 발생할 수 있는 서브-어텍(SUB-ATTACK) 방지를 위한 배리어로 반사방지막(O-BARC) 또는 포토레지스트막을 사용하지 않고, 콘택홀(30) 형성시 형성되는 식각 부산물인 폴리머막(50)을 선택적으로 콘택홀내의 기판(20)상에 형성함으로써 펜싱(fencing) 및 퍼시팅(FACETING) 현상을 방지할 수 있다. 이에 따라, 소자의 수율 및 신뢰성 향상에 기여할 수 있다.According to the trench forming method of the semiconductor device of the present invention described above, the contact hole is not used as a barrier for preventing the sub-attack (SUB-ATTACK) that may occur when forming the trench, and without using an anti-reflection film (O-BARC) or a photoresist film. Fencing and faceting may be prevented by selectively forming the polymer film 50, which is an etch byproduct formed at the time of formation, on the substrate 20 in the contact hole. This can contribute to the improvement of the yield and reliability of the device.

Claims (5)

기판상에 제1 절연막, 식각정지막, 및 제2 절연막을 차례로 적층하여 형성하는 단계;Sequentially stacking a first insulating film, an etch stop film, and a second insulating film on a substrate; 상기 제2 절연막, 식각정지막, 및 제1 절연막을 패터닝하여 상기 기판을 노출시키는 콘택홀을 형성하면서, 상기 콘택홀내의 노출된 기판상에 폴리머막을 형성하는 단계; 및Forming a polymer film on the exposed substrate in the contact hole while forming a contact hole for exposing the substrate by patterning the second insulating film, the etch stop film, and the first insulating film; And 상기 제2 절연막을 패터닝하여 트랜치를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 트랜치 형성방법.And forming a trench by patterning the second insulating film. 제 1항에 있어서,The method of claim 1, 상기 폴리머막은 500 ~ 10000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 트랜치 형성방법.The polymer film is a trench forming method of a semiconductor device, characterized in that formed to a thickness of 500 ~ 10000Å. 제 2항에 있어서,The method of claim 2, 상기 폴리머막은 고밀도 플라즈마 증착장비에서 C4F8, CH3F 및 Ar의 혼합가스에 의해 형성되는 것을 특징으로 하는 반도체 소자의 트랜치 형성방법.Wherein the polymer film is formed by a mixed gas of C 4 F 8 , CH 3 F and Ar in a high density plasma deposition apparatus. 제 2항에 있어서,The method of claim 2, 상기 폴리머막은 고밀도 플라즈마 증착장비에서 C2F6/Ar의 혼합가스에 의해 형성되는 것을 특징으로 하는 반도체 소자의 트랜치 형성방법.The polymer film is a trench forming method of a semiconductor device, characterized in that formed by a mixed gas of C 2 F 6 / Ar in a high density plasma deposition equipment. 제 3항 또는 제 4항에 있어서,The method according to claim 3 or 4, 상기 폴리머막은 상기 고밀도 플라즈마 증착장비의 실리콘-루프(Si- ROOF)의 온도를 200 ~ 300℃로 설정하여 다량의 카본 계열의 가스를 이용하여 형성하는 것을 더 포함하는 것을 특징으로 하는 반도체 소자의 트랜치 형성방법.The polymer film is a trench of a semiconductor device, characterized in that the silicon-loop (Si-ROOF) of the high-density plasma deposition apparatus is set to 200 ~ 300 ℃ by using a large amount of carbon-based gas trench Formation method.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8153527B2 (en) 2008-10-13 2012-04-10 Globalfoundries Singapore Pte. Ltd. Method for reducing sidewall etch residue

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8153527B2 (en) 2008-10-13 2012-04-10 Globalfoundries Singapore Pte. Ltd. Method for reducing sidewall etch residue

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