KR20030000890A - T1 CRC Calculation Module of the transmission system - Google Patents

Abstract

PURPOSE: A T1 CRC(Cyclic Redundancy Check) calculation module of a transmission system is provided to reset a calculation value of a current multi-frame signal at a bit right before the final bit of the multi-frame, and at the same time to output a CRC calculation value to the last frame of the multi-frame in clock cycle signals. CONSTITUTION: An F-bit value setting part(1) forcibly sets a first bit forming an F-bit in multi-frame data as '1(one)', and outputs an ESF(Extended Super Frame) multi-frame including the F-bit value. A main CRC calculator(2) performs a CRC operation for bit signals excepting a last bit of ESF multi-frame signals inputted from the F-bit value setting part(1), according to clock signals. A final CRC calculator(3) performs a CRC operation for the ESF multi-frame signals excepting the last bit outputted from the main CRC calculator(2) and the last bit, to output 6 bit values allocated with CRC bits. A CRC reset part(4) resets the multi-frame signals excepting the last bit outputted from the main CRC calculator(2) within clocks identical to the final CRC calculator(3). A CRC latch(5) latches the CRC-6 value calculated by the final CRC calculator(3). And a CRC data provider(6) inserts a CRC-6 value of a prior multi-frame latched by the CRC latch(5) in an F-bit of a next multi-frame.

Description

T1 CRC Calculation Module of the transmission system

The present invention relates to a T-one CAL calculation module of a transmission system. In particular, the T1 CAL calculation module resets the calculated value of a multi-frame signal currently input in the last bit of the last bit of the multi-frame and simultaneously performs the same clock period. By outputting the seed value to the last frame of the multiframe in the signal, it can be initialized at the same time as the seed calculation of the multiframe. Therefore, the T1 seed seed (T1) of the transmission system improves the processing efficiency of the seed calculation module. Calculation)

In general, a transmission technology is a technology used to exchange information converted into an electrical signal with a counterpart, and is classified into a subscriber transmission connecting a subscriber and an exchange and an inter-station transmission connecting an exchange period. In addition, various types of systems, such as an asynchronous wired transmission system, are currently developed and used in the transmission system for inter-transmission. Among these systems, wired transmission systems generally include network devices that process and transmit data in a bit-interleaving manner.

In addition, such network devices typically include a DS1 for multiplexing 24 channels of a DS0 block (not shown) connected to a subscriber in a bit-interleaving manner, a DS2 for multiplexing four signals of the DS1 in a bit-interleaving manner, It includes DS3, which multiplexes seven signals of DS2 by bit-interleaving. At this time, the processing speed of the DS1 is approximately 1.544Mbps, the processing speed of the DS2 is approximately 6.312Mbps, and the processing speed of the DS3 is approximately 44.736Mbps.

By the way, between the network devices such as DS1-DS3 is typically formed by the transmission frame in accordance with international standards, such as the ITU-T standard to perform data transmission, in this case, the structure of the transmission frame, in particular, T1 multi-frame (MULTIFRAME ) Includes SF frame and ESF [EXTENDET SUPER FRAME] frame. In addition, in order to multiplex the frame of the T1 structure as described above in the next step, that is, DS2, a T1 seed calculation module capable of detecting a transmission frame, for example, an ESF frame, is provided at the rear end of the DS1 and the front end of the DS2.

Herein, the ESF frame is composed of 193 bits including an F-bit (FAS BIT: FRAME ALIGHMENT SIGNAL) as shown in FIG. 1, and the frames of the 193 bits are gathered again to form a multiframe. The F-bit, which is the first bit of the ESF frame, consists of a total of 24 bits and contains information of each frame. Among the 24 F-bits, 6 bits are used to calculate the seed, and 24 frames are included. The sixth frame is the 2nd, 6th, 10th, 14th, 18th, and 22nd frames.

Therefore, the seed calculation module loads the seed value of the ESF multiframe using the seed bit, and checks the data loss in the transmission process by monitoring the seed bit at the receiving and transmitting end.

In this case, for the seed calculation, the T1 ESF multiframe uses seed 6 of the seed calculation module, and puts the 6-bit value calculated through this calculation into six F-bits allocated as seed bits. . This seed calculation includes all bits of 24 bits, and the F-bits are forced to "1".

Then, referring to FIG. 2 of the T1 seed calculation module of the conventional transmission system as described above, the first bit forming the F-bit among 24 frames composed of a total of 4452 (193 * 24) bits in synchronization with the clock is forced. Is set to " 1 " and the 4632 bits inputted from the F-bit value setting unit 70 and the F-bit value setting unit 70 for outputting 4632 bits of ESF multiframe including the F-bit value. The seed calculation unit 71 for seeding the ESF multiframe to the last bit and outputting six bit values C1-C6 assigned to the seed bits, and the last bit outputted from the seed calculator 71 When the CAL-6 (C1-C6) value calculated up to is outputted, the CAL bit reset unit 72 for resetting the multi-frame and the CAL bit reset unit 72 calculates to the last bit. Reset clock signal that compensates for one delay of data delay signal generated by reset A seed 73, a seed latch unit 74 for latching the seed 6 value calculated by the seed calculator 71, and the previous multiframe latched by the seed latch unit 74; The seed data providing unit 75 inserts the seed seed 6 value of the next multi-frame into the F-bit.

In addition, the components, including the seed calculator 71, include the exclusive OR gate 76 and the exclusive OR gate 77 according to the ITU-T G.704 standard as shown in FIG. Five D-flip flops 78A-E are continuously connected in series, and one end of the exclusive OR gate 77 is configured to be connected to the D-flip flops 78F.

On the other hand, looking at the operation of the conventional T1 seed seed calculation module as described above,

First, when a mapping from one level to another level of the optical transmission system is transmitted, a multiframe signal is transmitted. At this time, the multiframe signal checks data loss in the transmission process by executing a seed calculation operation in synchronization with a clock signal.

That is, when the multiframe is input to the exclusive OR gate 76 of the F-bit value setting unit 70 as shown in (b) of FIG. 4, the flip-flops of the F-bit value setting unit 70 ( 78A-F) and the exclusive OR gates 76 and 77 execute logic operations in synchronism with the clock signal as shown in FIG. 4A, so that the F-bits of 24 frames composed of a total of 2462 (193 * 24) bits are included. As shown in (c) of FIG. 4, the first bit forming the symbol is forcibly set to " 1 " and the 4632 bit ESF multiframe including the F-bit value is output to the seed calculator 71. FIG. Then, the seed calculation unit 71 performs seed calculation to the last bit of the 4632 bit ESF multiframe signal inputted from the F-bit value setting unit 70 according to the logic circuit shown in FIG. Only the six last bit values allocated as the seed bits are output to the seed bit reset unit 72. The seed reset unit 72 outputs this multiframe when the seed 6 value calculated up to the last bit output from the seed calculation unit 71 is output as shown in FIG. Resets the seeding of one multiframe seed.

At this time, when the seed bit reset unit 72 resets after calculating to the last bit, a data delay of one clock is generated as shown in "D" of FIG. 4 (d), and the reset clock corrector 73 This delay is compensated by stopping the delayed one clock signal.

At the same time as the seed calculation process, the seed 6 value calculated by the seed calculation unit 71 is latched by the seed latch unit 74 as shown in FIG. The seed data providing unit 75 inserts these values into the F-bits of the next multiframe from the seed MS-6 value of the previous multiframe latched by the seed latch unit 74.

Thus, the seed calculation module repeats the process to check for data loss during data transfer.

However, the conventional seed calculation module as described above performs the seed calculation to the last bit of the multiframe and then resets this value, thereby causing a disadvantage that the data is pushed back by one clock.

In addition, the conventional seed calculation module as described above has to add a separate additional component to compensate for the clock after the seed calculation, which causes a problem of significantly increasing the manufacturing cost of the seed seed calculation module. .

Accordingly, the present invention has been invented to solve the conventional problems as described above, and resets the calculated value of the multiframe signal currently input in the immediately preceding bit of the last bit of the multiframe in the T1 seed calculation module. T1 seed of the transmission system that improves the processing efficiency of the seed calculation module since it can be initialized simultaneously with the seed calculation of the multiframe by outputting the seed value to the last frame of the multiframe within the clock cycle signal. The purpose is to provide a calculation module.

Another object of the present invention is to provide a T-one seed seed calculation module of a transmission system in which the additional gate number necessary for calculating and resetting up to the last bit of a multiframe is not required, thereby reducing the manufacturing cost of seed seed calculation module. have.

The present invention for achieving the above object is an F-bit value that forcibly sets the first bit forming the F-bit of the multi-frame data to "1" and outputs an ESF multiframe including this F-bit value. A main seed calculator for executing seed calculation according to a clock signal of only the bit signals except the last bit among the ESF multi-frame signals inputted from the F-bit value setting section, and the main seed calculator A final seed calculator for outputting the six bit values allocated as the seed bits by seed-calculating the ESF multiframe signal and the last bit except for the last bit outputted by the seed bits, and the last bit outputted from the main seed calculator The T-One CAL system of the transmission system comprising a CAL bit reset unit for resetting all the excluded multi-frame signals within the same clock as the final CAL unit. Provide an acid module.

1 is an explanatory diagram for explaining the structure of a T1 ESF multiframe;

2 is a block diagram illustrating a conventional T1 seed seed calculation module.

3 is a block diagram illustrating the components of a T1 seed calculation module in accordance with the ITU-T G.704 standard;

4 is a timing diagram of a conventional T1 seed calculation module.

5 is a block diagram illustrating a T1 seed seed calculation module of the present invention.

6 is a timing diagram of a T1 seed calculation module of the present invention.

<Detailed Description of Codes>

1: F-bit value setting unit 2: Main seed calculator

3: final seed calculation unit 4: seed bit reset unit

5: seed latch unit 6: seed data providing unit

76: Exclusive OR gate 77: Exclusive OR gate

78A-F: D flip-flop

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The module of the present invention forcibly sets the first bit of the 24 frames consisting of a total of 4452 (193 * 24) bits to form "1" to "1" in synchronization with the clock as shown in FIG. F-bit value setting section 1 for outputting 4632 bits of ESF multiframe including the value, and the last bit of the last bit (4632 bits) of the ESF multiframe input from the F-bit value setting section 1; The main seed calculation unit (2) which executes seed calculation according to the clock signal only up to (4631 bits), and the immediately preceding bit (4631) of the last bit of the ESF multiframe outputted by the main seed calculation unit (2). Bit) and the last bit (4632 bits), the final seed calculator (3) for outputting the six bit values allocated to the seed bits by the seed calculation operation, and the last bit output from the main seed calculator (2) This multipre Seed bit reset unit 4 for resetting the seed, a seed latch unit 5 for latching the seed 6 value calculated by the final seed calculator 3, and the seed latch unit ( And a seed data providing unit (6) for inserting the seed-6 value of the previous multiframe latched by 5) into the F-bit of the next multiframe.

In addition, the components including the main seed calculator 2 may include an exclusive OR gate 76 and an exclusive OR gate 77 according to the ITU-T G.704 standard as shown in FIG. 3. Five D-flip flops 78A-E are continuously connected in series, and the D-flip flops 78F are connected to one end of the exclusive OR gate 77.

Next, the operation and effects of the apparatus of the present invention as described above will be described.

First, the apparatus of the present invention is transmitted as a multiframe signal when mapping a transmission signal from one level to another level of the transmission system, wherein the multiframe signal is transmitted to the system clock signal as shown in FIG. In synchronization, as shown in FIG. 6 (b), it is input to the exclusive OR gate 76 of the F-bit value setting section 1. Then, the flip-flops 78A-F and the exclusive OR gate 77 of the F-bit value setting unit 1 execute logic operations in synchronization with the input system clock signal, for a total of 4452 (193 * 24). The first bit forming the F-bit out of 24 frames composed of) bits is forcibly set to "1" as shown in (c) of FIG. 6, and a 4632-bit ESF multiframe including this F-bit value is the main seed. Output to the calculator 2.

At this time, the main seed calculator 2 performs seed seeding up to 4632 bits of ESF multiframe signal inputted from the F-bit value setting section 1 according to the logic circuit shown in FIG. Instead, the operation is executed up to 4631 bits except the last bit and output to the final seed calculator 3.

Then, the final seed calculator 3 calculates only the last 3 bits and 3632 bit signals inputted from the main seed calculator 2 and the last 6 bit values assigned to the seed bits are shown in FIG. As shown in FIG. 5, the seed latch unit 5 is input to the latch latch unit 5. At this time, the seed bit reset unit 4 also operates during the same clock period as the final seed calculator 3, except for the 4631 bits inputted from the main seed calculator 2, i.e., the last bit of the total 4632 bits. After receiving the calculated value, it resets the calculation of the multiframe in which the current CA calculation is performed.

That is, the seed calculation of the final seed calculation unit 3 and the reset function of the seed bit reset unit 4 are executed simultaneously, that is, within the same clock. Therefore, as in the conventional module, the one-clock delay caused by resetting the multiframe after the final seed calculation is not generated in the apparatus of the present invention.

Meanwhile, the seed C-6 value calculated by the final seed calculator 3 simultaneously with the seed seed calculation process is immediately latched to the next clock without any clock delay as shown in FIG. It is latched by the part 5. The seed data providing unit 6 inserts the seed values of the previous multiframe latched by the seed latch unit 5 directly into the F-bits of the next multiframe without clock delay. Given.

Thus, the seed calculation module repeats the process to check for data loss during data transfer.

As described above, the present invention resets the calculated value of the multiframe signal currently input in the immediately preceding bit of the last bit of the multiframe in the T1 seed calculation module and simultaneously the last frame of the multiframe within the same clock period signal. By outputting the seed value to the seed, it can be initialized at the same time as the seed calculation of the multi-frame has the advantage of improving the processing efficiency of the seed calculation module accordingly.

In addition, according to the present invention, since the additional number of gates required for calculating after the last bit of the multi-frame is not required, the manufacturing cost of the seed calculation module is also reduced.

Claims (2)

In the T-one CAL calculation module of the transmission system that checks the loss of the multi-frame data when transmitting the multi-frame data from the physical level of the transmission system to another level, An F-bit value setting unit forcibly setting the first bit forming the F-bit of the multiframe data to "1" and outputting an ESF multiframe including the F-bit value, and setting the F-bit value A main seed calculation unit that performs seed calculation only according to a clock signal of the bit signals except the last bit among the ESF multi-frame signals input from the subfield, and an ESF multi part except the last bit output by the main seed calculation unit. The final seed calculation unit performs a seed operation on the frame signal and the last bit to output the six bit values allocated to the seed bits, and the final seed includes a multiframe signal from which the last bit outputted from the main seed calculator is excluded. A T-one seed seed calculation module for a transmission system comprising a seed seed reset unit for resetting both the seed calculator and the same clock. The seed seeding unit of claim 1, wherein the seed seeding unit includes a seed seed latch unit for latching a seed 6 value calculated by the seed seed calculating unit and a previous multiframe seed seed latched by the seed seed latch unit. A T1 seed CA calculation module of a transmission system, characterized in that a seed data providing unit for inserting a -6 value into an F-bit of a next multiframe is connected.