KR100243695B1 - A frame offset signal generator using a reset signal - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an apparatus for generating a frame offset signal using a reset signal.

2. The technical gist of the invention to solve

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame offset signal generator of a synchronous optical transmission system capable of generating a frame offset signal having a stable predetermined period and also widening a timing margin in the system.

3. Summary of the Solution of the Invention

The present invention provides a mask signal generating means for outputting a mask signal; Frame offset signal generating means for outputting a frame offset signal and an output reset signal, respectively; And selection signal generating means for receiving the mask signal and the frame offset signal and outputting the selection signal.

4. Important uses of the invention

The present invention is used to generate a frame offset signal having a stable period in a synchronous optical transmission system.

Description

Frame Offset Signal Generator Using Reset Signal

The present invention relates to an apparatus for generating a frame offset signal of a synchronous optical transmission system, and more particularly, to a frame offset signal having a stable period by absorbing instability of timing that may be generated during distribution of a reference frame signal and a reference clock to each unit in a synchronous optical transmission system. The present invention relates to a frame offset signal generator of a synchronous optical transmission system that can occur.

The 10Gbps synchronous optical transmission system multiplexes different slave signals (STM-1, STM-4, STM-16) configured for the synchronous transmission scheme into STM-64 (Synchronous Transport Module -64) signals, which are high-speed signals. It receives the STM-64 signal from the other station and demultiplexes it into several subordinate signals.

When multiplexing the multiple dependent signals into one STM-64 signal, all the dependent signals to be multiplexed must be present in the same bit position on the time axis to allow normal multiplexing. To this end, in a 10 Gbps synchronous optical transmission system, a reference frame signal and a reference clock are supplied to a slave unit and a high speed unit in a synchronous clock generator. The slave unit sends out data in accordance with this reference frame signal, and in the high-speed unit, normal multiplexing is performed by compensating for the time delay difference between data from several slave units so that the first bit of the frame in each signal is in the same position in time and then multiplexed. Each unit generates and uses a reference frame offset signal having an 8 kHz period after retiming the reference frame signal to the reference clock.

In the 10 Gbps synchronous optical transmission system, a 4 kHz or 8 kHz signal having a duty ratio of 50% is used as a reference frame signal. In this case, the phase relationship of the reference frame signal with respect to the reference clock must be exactly matched to enable normal retiming in the unit receiving the reference clock to generate a frame offset signal having a period of exactly 8 kHz. In addition, conventionally, in order to exactly match the phase of the reference frame signal and the reference clock, a method such as adjusting the cable length or the like or lowering the speed of the reference clock from the outside has been used.

A frame offset signal generator of a conventional synchronous optical transmission system will be described with reference to FIG. 1.

As shown in FIG. 1, the apparatus for generating a frame offset signal of a conventional synchronous optical transmission system includes a first D-flip flop having a reference clock input through a clock terminal and a reference frame signal input to an input terminal D. 11) and a second D-flip flop 12 having a reference clock inputted through a clock terminal and having an input terminal D connected to an output terminal Q of the first D-flip flop 11. An exclusive OR gate 13 connected with an input terminal connected to an output terminal Q of the first D flip-flop 11, and a type force terminal connected to an output terminal Q of the second D flip-flop 12; A third D- for outputting the frame offset signal FS through the output terminal Q by receiving the output signal of the exclusive OR gate 13 through the input terminal D according to the reference clock input through the clock terminal; And flip-flop 14.

Here, the first and second D flip-flops 11 and 12 constitute a 2-bit shift register, and the output of the exclusive OR gate 13 is retimed at the third D flip-flop 14.

The operation timing of the frame offset signal generator of the conventional synchronous optical transmission system having the above structure will be described with reference to FIGS. 2A and 2B.

FIG. 2A illustrates a timing diagram when a frame offset signal generator of a conventional synchronous optical transmission system generates a stable frame offset signal.

In FIG. 2A, (a1) is the timing of the reference clock, (b1) is the timing of the reference frame signal, (c1) is the timing of the signal output through the output terminal Q of the first D-flop flop 11, (d1) is the timing of the signal output through the output terminal Q of the second D flip-flop 12, (e1) is the output timing of the exclusive OR gate 13, and (f1) is the third D-flip This is the timing of the frame offset signal output through the output terminal Q of the flop 14.

As shown in FIG. 2A, when the phase relationship between the reference frame signal and the reference clock is stable, the frame offset signal FS also has a stable 8 kHz period.

2B illustrates a timing diagram when a frame offset signal generator of the conventional synchronous optical transmission system generates an unstable frame offset signal.

In FIG. 2B, (a2) is the timing of the reference clock, (b2) is the timing of the reference frame signal, (c2) is the timing of the signal output through the output terminal Q of the first D-flop flop 11, (d2) is the timing of the signal output through the output terminal Q of the second D flip-flop 12, (e2) is the output timing of the exclusive OR gate 13, and (f2) is the third D-flip The timing of the frame offset signal output through the output terminal Q of the flop 14 is shown, respectively.

As shown in FIG. 2B, if the phase relationship between the reference frame signal and the reference clock is unstable, a time difference of about 1 bit may occur every 8 kHz. Therefore, the FS does not have a stable 8 kHz period and a time difference of about one bit may occur. In this case, the unit cannot compose a frame of 8 kHz, so signal loss is inevitable.

As shown in FIG. 2B, when the frame offset signal generator of the conventional synchronous optical transmission system does not exactly match the phase relationship between the reference frame signal and the reference clock, it may not be possible to accurately retime the reference frame signal with the reference clock in each unit. As a result, there was still a problem that it became impossible to generate a frame offset signal having a period of exactly 8 kHz, causing a transmission error in the system.

Accordingly, the present invention has been made to solve the above problems, the reference frame signal and the reference clock is distributed to each unit in the synchronous optical transmission system, and the reference distribution for generating the frame offset signal of each predetermined period in the unit Since the phase shift between the frame signal and the reference clock should be small, even if the phase shift between the reference frame signal and the reference clock is large, a frame offset signal having a stable predetermined period can be generated through its own reset operation, and the reference frame signal and It is an object of the present invention to provide a frame offset signal generating apparatus using a reset signal that can widen a timing margin in a system when distributing a reference clock.

1 is a circuit diagram of a frame offset signal generator of a conventional synchronous optical transmission system.

2A and 2B are timing diagrams of a frame offset signal generator of a conventional synchronous optical transmission system.

3 is a circuit diagram of a frame offset signal generator using a reset signal according to an embodiment of the present invention.

4 is a timing diagram of a frame offset signal generator using the reset signal of the present invention.

Explanation of symbols on the main parts of the drawings

10: frame signal generator 20: mask signal generator

30: input reset signal generator 40: frame offset signal generator

50: selection signal generator 60: reset signal generator

Frame offset signal generating apparatus using a reset signal of the present invention for achieving the above object, the frame signal generating means for receiving a reference frame signal in accordance with the reference clock and outputs a frame signal; Mask signal generating means for receiving the frame signal output from the frame signal generating means and outputting a mask signal according to the reference clock; Input reset signal generating means for receiving the mask signal output from the mask signal generating means and outputting an input reset signal in accordance with the reference clock; Frame offset signal generating means for receiving a reset signal according to the reference clock and outputting a frame offset signal and an output reset signal, respectively; Selection signal generating means for receiving the mask signal and the frame offset signal according to the reference clock and outputting a selection signal; And reset signal generating means for receiving the input reset signal and the output reset signal according to the selection signal and outputting a reset signal for resetting the frame offset signal generating means.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

As shown in FIG. 3, the apparatus for generating a frame offset signal of a synchronous optical transmission system according to an embodiment of the present invention includes a frame signal generator 10 for receiving a reference frame signal and outputting a frame signal FS; A mask signal generator 20 for outputting a mask signal MASK, an input reset signal generator 30 for outputting an input reset signal RSTIN, a frame offset signal FSOUT and an output reset signal RSTOUT ), A reset signal (RESET) for resetting the frame offset signal generator (40) for outputting the selection signal, the selection signal generator (50) for outputting the selection signal (SEL), and the frame offset signal generator (40). ) Is provided with a reset signal generator (60).

As in FIG. 1, the frame signal generator 10 includes first to third D-flip flops 11, 12, and 14 and an exclusive OR gate 13.

The mask signal generator 20 receives a reference clock through a clock terminal, and the input terminal D is connected to the output terminal Q of the third D-flop flop 14 of the frame signal generator 10. A fifth D-flip connected to the fourth D-flip flop 21 and a clock terminal through an input terminal D and connected to an output terminal Q of the fourth D-flip flop 21; The flop 22 receives a reference clock through a clock terminal, and the input terminal D is connected to the sixth D-flop flop 23 connected to the output terminal Q of the fifth D-flop flop 22. The input terminals are respectively an output terminal Q of the third D flip-flop 14 of the frame signal generator 10, an output terminal Q of the fourth D flip-flop 21, and a fifth D flip-flop. A logic sum gate 24 connected to the output terminal Q of (22) and the output terminal Q of the sixth D-flop flop 23 is provided.

The input reset signal generator 30 receives a reference clock through a clock terminal, and the input terminal D is connected to an output terminal of the OR gate 24 of the mask signal generator 20. 31) and an eighth D-flip flop 32 which receives a reference clock through a clock terminal and whose input terminal D is connected to an output terminal Q of the seventh D-flip flop 31. An AND terminal and an input force terminal connected to an output terminal Q of the seventh D-flop flop 31 and an inverted output terminal / Q of the eighth D-flop flop 32, respectively; A ninth D flip-flop that receives a reference clock through a clock terminal, an input terminal D is connected to an output terminal of an AND gate 33, and outputs an input reset signal RSTIN through an output terminal Q. 34 is provided.

The frame offset signal generator 40 receives the reference clock through the clock terminal, receives the reset signal RESET from the reset signal generator 60 through the reset terminal RST, and receives the frame offset signal output terminal FSQ. The frame counter signal FSOUT is output to the outside through the frame counter, and the output counter output signal RSTOUT is output through the frame counter 41.

The selection signal generator 50 receives the reference clock through the clock terminal, receives the frame offset signal FSOUT through the enable terminal E, and the input terminal D of the mask signal generator 20. It is connected to the output terminal of the OR gate 24, and consists of a tenth D-flip flop 51 for outputting the selection signal SEL through the output terminal Q.

In the reset signal generator 60, the selection terminal S is connected to the output terminal Q of the tenth D-flip flop 51 of the selection signal generator 50, and the first input terminal I0 is input. The ninth D flip-flop 34 of the reset signal generator 30 is connected to the output terminal Q, and the second input terminal I1 is connected to the frame counter 41 of the frame offset signal generator 40. It is connected to the reset signal output terminal RSQ, and the output terminal Z is composed of a signal selector 61 connected to the reset terminal RST of the frame counter 41.

Meanwhile, the third D-flip flop 14 and the fourth to sixth D-flip flops 21, 22, and 23 are operated by 4-bit shift registers, and the seventh and eighth D-flip flops 31 and 32 are used. ) Operates as a 2-bit shift register.

The operation of the frame offset signal generator of the synchronous optical transmission system of the present invention having the above structure will be described in detail with reference to FIG. 4 as follows.

In FIG. 4, (a3) indicates the timing of the reference clock, (b3) indicates the timing of the frame signal FS output through the output terminal Q of the third D flip-flop 14, and (c3) indicates the fourth. The timing of the signal output through the output terminal Q of the D-flop flop 21, (d3) is the timing of the signal output through the output terminal Q of the fifth D-flop flop 22, (e3 ) Is the timing of the signal output through the output terminal Q of the sixth D-flop flop 23, (f3) is the mask signal MASK output from the OR gate 24 of the mask signal generator 20 Is the timing of the signal output through the output terminal Q of the eighth D-flip flop 32, and (h3) is the logical product gate 33 of the input reset signal generator 30. Timing of the output signal, (i3) is the timing of the signal output through the output terminal Q of the ninth D-flop flop 34, (j3) is the timing of the signal indicating the internal operation sequence of the frame counter 41 , (k3) is the output of the frame counter 41 The timing of the output reset signal output through the signal output terminal RSQ, l3 is the timing of the frame offset signal output through the frame offset signal output terminal FSQ of the frame counter 41, and m3 is the tenth. The timing of the selection signal SEL output through the output terminal Q of the D-flip flop 51 is shown.

Referring to FIG. 4, since the unstable region occurs when the frame signal FS is out of phase with the reference frame signal, the frame signal FS constitutes a 4-bit shift register to secure a stable region once. The D-flip-flops 14, 21, 22, and 23 are stored in the D-flip-flops 14, 21, 22, and 23, and are then ORed by ORing the signals output from the D-flip-flops 14, 21, 22, and 23, respectively. The mask signal MASK is output. The timing for making this mask signal MASK is the same as the process of (a3, (b3), (c3), (d3), (e3) and (f3) of FIG. 4, and an unstable state of one bit at each end is obtained. And the middle 4 bits have a stable state.The mask signal MASK is again stored in the seventh and eighth D-flip flops 31 and 32 constituting the 2-bit shift register, and then the AND gate 33 ) By AND multiplying the mask signal input through the seventh and eighth D- flip-flop (31, 32), respectively, and outputs the logical product value to the input terminal (D) of the ninth D-flop flop (34), The D-flip-flop 34 retimes a signal input through the input terminal D according to a reference clock input through the clock terminal to convert the input reset signal RSTIN into a signal selector of the reset signal generator 60. Output to the first input terminal I1 of 61. At this time, the mask signal MASK also has an unstable state, so the input reset signal RSTIN is also about one bit. Difference is generated. Therefore, the mask signals (MASK) is a reset signal input (RSTIN) occurs within the 4-bit segment that is stable at a high (HIGH). Of course, this timing is as shown in Fig.

The frame counter 41 of the frame offset signal generator 40 adjusts to the rising-edge of the reference clock while the reset signal RESET output from the reset signal generator 60 is high. Reset to " 0 " and generate a frame offset signal FSOUT and an output reset signal RSTOUT having an 8 kHz period from the reference clock. For example, when the reference clock is 19.44 MHz, the frame counter 41 operates in 2,430 digits, and "N" is 2,429 (2,430 in the internal operation sequence of the frame counter 41 shown in FIG. 4 (j3)). 1 = 2,429). In addition, if the reference clock is 77.76 MHz, the frame counter 41 operates in 9,720 binary, and "N" is 9,719 (9,720-1 = 9,719) in the internal operation order of the frame counter 41 in FIG. 4 (j3). Becomes

4 (k3) makes a bit high signal when the value of the frame counter 41 is "N", and the frame offset signal FSOUT is a bit high when the value of the counter is "0". HIGH) signal. It should be noted that both the output reset signal RSTOUT and the frame offset signal FSOUT are all generated within a 4-bit period in which the mask signal MASK is stable to HIGH. Therefore, initially assuming that the selection signal SEL is LOW, the frame counter 41 is first reset by the input reset signal RSTIN. Since the input reset signal RSTIN has an unstable region of about one bit, an error of about one bit also occurs in the operation sequence of the counter. After that, when the frame offset signal FSOUT is generated, the mask signal MASK is in a high state, and thus the selection signal SEL is changed to high. Therefore, at the next frame position, the frame counter 41 is not reset using the input reset signal RSTIN having an unstable state, but the output reset signal RSTOUT generated by dividing the reference clock by the frame counter 41 itself. Frame counter 41 is reset. As a result, even if the reference frame signal is not normally retimed to the reference clock, the period of the frame offset signal FSOU becomes exactly 8 kHz.

In conclusion of the present invention described above, the mask signal MASK and the input reset signal RSTIN serve only to roughly position the reference frame signal initially, and then the frame counter 41 resets itself. The frame offset signal FSOUT having a period of exactly 8 kHz within 1 to 2 bits with the reference frame signal is generated through comparison with the mask signal MASK. If the time difference between the frame offset signal FSOUT and the mask signal MASK exceeds the mask stable region, the frame counter 41 is reset again by the input reset signal RSTIN, and thus the frame offset which is the final signal of the present invention. The signal FSOUT may be generated within 1 to 2 bits of the reference frame signal and always generate a frame offset signal FSOUT having an accurate 8 kHz period regardless of the phase relationship between the reference frame signal and the reference clock.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the apparatus for generating a frame offset signal of the synchronous optical transmission system of the present invention can generate a stable 8 kHz frame offset signal in each unit even when a phase difference between the reference frame signal and the reference clock occurs. And widening the timing margin in the system at the time of reference clock distribution, thereby improving the operating conditions of the entire system.

Claims (6)

Frame signal generating means for receiving a reference frame signal according to a reference clock and outputting a frame signal; Mask signal generating means for receiving the frame signal output from the frame signal generating means and outputting a mask signal according to the reference clock; Input reset signal generating means for receiving a reset signal according to the reference clock and receiving the mask signal output from the mask signal generating means and outputting an input reset signal; Frame offset signal generating means for outputting a frame offset signal and an output reset signal in accordance with the reference clock; Selection signal generating means for receiving the mask signal and the frame offset signal according to the reference clock and outputting a selection signal; And Reset signal generation means for receiving the input reset signal and the output reset signal according to the selection signal and outputting a reset signal for resetting the frame offset signal generation means; Frame offset signal generator using a reset signal made of a. The method of claim 1, The mask signal generating means, A first D-flip-flop receiving the reference clock through a clock terminal, the input terminal of which is connected to an output terminal of the frame signal generating means; A second D flip-flop, which receives the reference clock through a clock terminal, and whose input terminal is connected to an output terminal of the second D flip-flop; A third D-flop flop that receives the reference clock through a clock terminal and whose input terminal is connected to an output terminal of the second D-flop flop; And Logic sum calculating means having input terminals connected to an output terminal of the frame signal generator, an output terminal of the first D-flop flop, an output terminal of the second D-flop flop, and an output terminal of the third D-flop flop Frame offset signal generator using a reset signal made of a. The method according to claim 1 or 2, The input reset signal generating means, A fourth D-flip-flop, which receives the reference clock through a clock terminal, and whose input terminal is connected to an output terminal of the mask signal generating means; A fifth D-flop flop receiving the reference clock through a clock terminal and having an input terminal connected to an output terminal of the fourth D-flop flop; Logical product calculating means, with input terminals connected to an output terminal of the fourth D-flop flop and an inverting output terminal of the fifth D-flop flop; And A third D flip-flop that receives the reference clock through a clock terminal, an input terminal of which is connected to an output terminal of the logical product calculating means, and outputs the input reset signal to the reset signal generating means through an output terminal; Frame offset signal generator using a reset signal made of a. The method of claim 3, wherein The frame offset signal generating means, The reference clock is input through a clock terminal, a reset terminal is connected to an output terminal of the reset signal generating means, outputs the frame offset signal through a frame offset signal output terminal, and resets the output through an output reset signal output terminal. Frame Counter to Output a Signal Frame offset signal generating device using a reset signal comprising a. The method of claim 4, wherein The selection signal generating means, The reference clock is input through a clock terminal, the frame offset signal is input through an enable terminal, an input terminal is connected to an output terminal of the mask signal generation unit, and the reset signal generating means transmits the selection signal through an output terminal. D-Flip Flop Output Frame offset signal generator using a reset signal made of a. The method of claim 1, The reset signal generating means, Receiving the selection signal through a selection terminal, receiving the input reset signal through a first input terminal, receiving the output reset signal through a second input terminal, and generating the frame offset signal generating means through an output terminal. A signal selector for outputting the reset signal for resetting Frame offset signal generating device using a reset signal comprising a.

Images