KR20020094505A - Nonvolatile Memory Device and Method Of Fabricating The Same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a method for fabricating the same are provided to form the non-volatile memory device of an SONOS(Silicon-Oxide-Nitride-Oxide-Semiconductor) structure by forming a tunnel oxide layer of uniform thickness on a lower part of a gate conductive layer pattern. CONSTITUTION: An isolation layer pattern(160) is formed on a semiconductor substrate(100) in order to define an active region. The isolation layer pattern(160) and the active region are covered by a tunnel oxide layer(110), a nitride layer(120), and a blocking oxide layer(130). A plurality of parallel gate conductive layers pattern(300) are formed on the blocking oxide layer(130). A sidewall of the gate conductive layer pattern(300) is covered by a sidewall thermal oxide layer(150). The tunnel oxide layer(110), the nitride layer(120), and the blocking oxide layer(130) are covered on a whole surface of the semiconductor substrate(100). The blocking oxide layer(130) between the gate conductive layer patterns(300) can be removed. The gate conductive layer patterns(300) is formed with a stacked polysilicon layer and a silicide layer.

Description

Nonvolatile Memory Device and Method for Fabrication thereof {Nonvolatile Memory Device and Method Of Fabricating The Same}

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device and a method for manufacturing the same.

The nonvolatile memory may be formed in various structures, one of which is a nonvolatile memory having a silicon-oxide-nitride-oxide-semiconductor (SONOS) structure.

1 is a cross-sectional view illustrating a nonvolatile memory device having a SONOS structure according to the prior art.

Referring to FIG. 1, an isolation layer pattern (not shown) defining an element active region is disposed on a semiconductor substrate 10. A gate pattern 90 in which the tunnel oxide film 20, the nitride film 30, the blocking oxide film 40, and the gate conductive film pattern 50 are sequentially stacked is disposed across the device active region. In addition, the device active region between the gate patterns 90 is exposed.

The charge in the nonvolatile memory of the SONOS structure is injected or discharged into the nitride film 30 through the tunnel oxide film 20 by the voltage difference between the gate conductive film pattern 50 and the semiconductor substrate 10. . The charge injected or discharged into the nitride film 30 changes the threshold voltage of the cell, which is the operation principle of the SONOS structure memory. The blocking oxide layer 40 prevents charge flow from the gate conductive layer pattern 50 to the nitride layer 30.

The non-volatile memory of the SONOS structure is characterized in that the insulating nitride film 30 is used as compared with a general flash memory constituting a floating gate of a conductive material. This eliminates the need for a floating gate forming process, which results in a lower vertical height and a simplified manufacturing process.

In order to cure the etching damage generated in the process of forming the gate pattern 90, a thermal oxidation process is performed to form a sidewall thermal oxide layer 60 on sidewalls of the gate conductive layer pattern 50. In this case, since the device active region between the gate patterns 90 and the sidewalls of the tunnel oxide film 20 are exposed, the edge of the tunnel oxide film 20 is thickened by bird's beak by the thermal oxidation process. The phenomenon occurs. This phenomenon deteriorates the operation speed and durability of the device and results in widening the cell threshold voltage distribution.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a nonvolatile memory device having a SONOS structure having a uniform tunnel oxide film under a gate conductive film pattern.

Another object of the present invention is to provide a method of forming a nonvolatile memory device having a SONOS structure in which a tunnel oxide layer under a gate conductive layer pattern has a uniform thickness.

1 is a cross-sectional view illustrating a nonvolatile memory device according to the prior art.

2 is a plan view of a general nonvolatile memory.

3A, 4A, 3B, and 4B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention.

5A, 6A, 5B, and 6B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention.

7 and 8 are perspective views illustrating a nonvolatile memory device according to the present invention.

In order to achieve the above technical problem, the present invention provides a nonvolatile memory device having a nitride film between the gate conductive film pattern. The nonvolatile memory device is formed on a semiconductor substrate to define a device isolation layer pattern defining a device active region, a gate conductive layer pattern crossing the upper portion of the device active region and the device isolation layer pattern, the gate conductive layer pattern and the device active region. It includes a tunnel oxide film, a nitride film and a blocking oxide film sequentially stacked between them. The device active region between the gate conductive layer patterns may be covered by at least the tunnel oxide layer and the nitride layer.

The device isolation layer pattern between the gate conductive layer patterns is covered by at least the tunnel oxide layer and the material layers extending from the nitride layer.

The gate conductive layer pattern may include a second conductive layer pattern crossing the device active region and the isolation layer pattern, and a first conductive layer pattern interposed between the second conductive layer pattern and the blocking oxide layer. In this case, the device isolation layer pattern is in direct contact with the second conductive layer pattern.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a nonvolatile memory device such that at least a nitride film remains between gate conductive film patterns. The manufacturing method includes forming a device isolation film pattern defining a device active region on a semiconductor substrate. A tunnel oxide film, a nitride film, and a blocking oxide film are sequentially formed on the entire surface of the semiconductor substrate including the device isolation layer pattern. A gate conductive film is formed on the entire surface of the semiconductor substrate including the blocking oxide film, and the gate conductive film is etched to form a gate conductive film pattern crossing the device active region.

The forming of the gate conductive layer pattern may include etching the tunnel oxide layer and the nitride layer between at least the gate conductive layer patterns. A sidewall thermal oxide layer may be further formed on sidewalls of the gate conductive layer pattern.

According to another aspect of the present invention, a method of manufacturing a nonvolatile memory device using a self-aligned trench technique is provided. The method includes laminating a tunnel oxide film, a nitride film, a blocking oxide film, a first conductive film and an abrasive blocking film on a semiconductor substrate, and subsequently etching these layers to form trench regions in the semiconductor substrate. An isolation layer pattern is formed in the trench region. The polishing blocking film is removed, and a second conductive film is formed on the entire surface of the resultant product. Thereafter, the second conductive film and the first conductive film are successively patterned to form a second conductive film pattern that crosses the device active region, and simultaneously between the second conductive film pattern and the blocking oxide film. 1 A conductive film pattern is formed.

The forming of the first and second conductive layer patterns may include etching the at least the tunnel oxide layer and the nitride layer to remain on the device active region between the second conductive layer patterns. A sidewall thermal oxide film may be further formed on sidewalls of the first and second conductive film patterns.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

2 is a plan view of a general flash memory.

Referring to FIG. 2, a device isolation layer pattern 160 defining a device active region 200 is disposed in one direction on a semiconductor substrate. A plurality of gate conductive film patterns 300 are disposed on the semiconductor substrate to vertically cross the device active region 200 and the device isolation layer pattern 160.

3A, 3B, 4A, and 4B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention. 3A and 4A are cross-sectional views taken along line 1-1 'of FIG. 2, and FIGS. 3B and 4B are cross-sectional views taken along line 2-2' of FIG.

Referring to FIGS. 3A and 3B, the device isolation layer pattern 160 defining the device active region is formed on the semiconductor substrate 100. The isolation layer pattern 160 is formed according to a conventional trench isolation method. The top surface of the device isolation layer pattern 160 may be higher than the top surface of the device active region, but the difference in height is preferably minimized.

The tunnel oxide layer 110, the nitride layer 120, the blocking oxide layer 130, and the gate conductive layer 140 are sequentially formed on the entire surface of the semiconductor substrate including the device isolation layer pattern 160. The tunnel oxide film 110 is formed of a silicon oxide film having a thickness of 20 to 60 microseconds, the nitride film 120 is formed of a silicon nitride film having a thickness of 60 to 100 microseconds, and the blocking oxide film 130 has a thickness of 40 to 120 microseconds. It is preferable to form with a silicon oxide film. In addition, the gate conductive layer 140 may be formed of a polysilicon layer and a silicide layer, which are sequentially stacked. In addition, a silicon nitride layer may be further stacked on the silicide layer.

Referring to FIGS. 4A and 4B, the gate conductive layer 140 is etched to form a gate conductive layer pattern 300 that crosses the device isolation layer pattern 160. The etching of the gate conductive layer 140 may be performed such that the blocking oxide layer 130 remains between the gate conductive layer patterns 300. In some cases, the blocking oxide film 130 may be etched, but in this case, the nitride film 120 must be etched to remain. To this end, the etching process is preferably carried out with a recipe having a high etching selectivity to silicon oxide.

The etching process for forming the gate conductive layer pattern 300 is preferably an anisotropic etching method. A thermal oxidation process is performed to cure damage occurring on sidewalls of the gate conductive film pattern 300 by the anisotropic etching process. As a result of the thermal oxidation process, the sidewall thermal oxide film 150 is formed on the sidewall of the gate conductive film pattern 300.

By the nitride layer 120, oxygen may no longer penetrate to the tunnel oxide layer 110 in the region between the gate conductive layer patterns 300. As a result, as in the prior art, the buzzing phenomenon in which the edge of the tunnel oxide film 20 becomes thick is prevented.

An impurity implantation process is performed on the semiconductor substrate on which the sidewall thermal oxide film 150 is formed using the gate conductive film pattern 300 as an ion implantation mask. As a result, the junction region 170 is formed in the device active region between the gate conductive layer patterns 300. In the prior art, the impurity implantation process is generally performed after the silicon oxide film is further formed on the semiconductor substrate to prevent a phenomenon such as channeling. However, in the present invention, the tunnel oxide film 110 and the nitride film 120 are performed. ) And the blocking oxide film 130 may serve to prevent the channeling.

5A and 6A are cross-sectional views taken along line 1-1 'of FIG. 2 of a nonvolatile memory device according to another embodiment of the present invention. 5B and 6B are cross-sectional views taken along line 2-2 'of FIG. 2 of a nonvolatile memory device according to another embodiment of the present invention.

5A and 5B, a tunnel oxide film 110, a nitride film 120, and a blocking oxide film 130 are sequentially stacked on the semiconductor substrate 100. The tunnel oxide film 110, the nitride film 120 and the blocking oxide film 130 are formed of the same method and material as in FIGS. 3A, 3B, 4A, and 4B. In addition, the first conductive layer 180 and the polishing blocking layer 190 are sequentially formed on the blocking oxide layer 130. Thereafter, the polishing blocking film 190, the first conductive film 180, the blocking oxide film 130, the nitride film 120, the tunnel oxide film 110 and the semiconductor substrate 100 are sequentially etched, A trench region defining an element active region is formed in the semiconductor substrate 100.

An isolation layer is formed on the entire surface of the semiconductor substrate on which the trench is formed. The device isolation layer is etched entirely to expose the polishing blocking layer 190, thereby forming the device isolation layer pattern 161. The device isolation layer pattern 161 fills the trench region and extends to an upper surface of the polishing blocking layer 190.

6A and 6B, after the exposed abrasive blocking film 190 is removed, a second conductive film is formed on the entire surface of the resultant. The second conductive layer and the first conductive layer 180 are sequentially etched to form a second conductive layer pattern 210 crossing the device active region and the device isolation layer pattern 161. Accordingly, an island-shaped first conductive film pattern 181 is formed between the second conductive film pattern 210 and the device active region. The first conductive layer pattern 181 and the second conductive layer pattern 210 constitute a gate conductive layer pattern 300. The etching process may also be performed such that the blocking oxide layer between the gate conductive layer patterns 300 remains. Or at least the nitride film 120 is to be left, and the method is the same as described with reference to FIGS. 3A, 3B, 4A, and 4B.

By performing a thermal oxidation process on the semiconductor substrate including the gate conductive layer pattern 300, the sidewall thermal oxide layer 151 is formed on the sidewall of the gate conductive layer pattern 300. Even in the thermal oxidation process, as described with reference to FIG. 4A, the buzzing phenomenon in which the edge of the tunnel oxide film 110 becomes thick is prevented by the nitride film 120.

As described with reference to FIG. 4A, an impurity implantation process is performed on the semiconductor substrate on which the sidewall thermal oxide film 151 is formed to form the junction region 170.

FIG. 7 is a perspective view illustrating a nonvolatile memory device manufactured according to the method described with reference to FIGS. 3A, 3B, 4A, and 4B.

Referring to FIG. 7, the device isolation layer pattern 160 defining the device active region is disposed in one direction on the semiconductor substrate 100. The device isolation layer pattern 160 and the device active region are covered by the tunnel oxide layer 110, the nitride layer 120, and the blocking oxide layer 130 which are sequentially stacked. A plurality of parallel gate conductive layer patterns 300 crossing the device active region and the device isolation layer pattern 160 are disposed on the blocking oxide layer 130. Sidewalls of the gate conductive layer pattern 300 are covered by the sidewall thermal oxide layer 150.

In the resultant product, the tunnel oxide film 110, the nitride film 120, and the blocking oxide film 130 cover the entire surface of the semiconductor substrate. However, the blocking oxide layer 130 may be removed between the gate conductive layer patterns 300, but at least the nitride layer 120 remains.

The gate conductive layer pattern 300 may be formed of a polysilicon layer and a silicide layer that are sequentially stacked. In addition, a silicon nitride layer may be further formed on the silicide layer.

8 is a perspective view illustrating a nonvolatile memory device manufactured according to the method described with reference to FIGS. 5A, 5B, 6A, and 6B.

Referring to FIG. 8, the device isolation layer pattern 161 defining the device active region is disposed in one direction on the semiconductor substrate 100. The device active region is covered with the tunnel oxide film 110, the nitride film 120, and the blocking oxide film 130 which are sequentially stacked. A second conductive layer pattern 210 crossing the device active region and the device isolation layer pattern 161 is disposed on the device isolation layer pattern 161.

A first conductive layer pattern 181 is disposed in an area where the second conductive layer pattern 210 and the device active region cross each other, and the first conductive layer pattern 181 is the second conductive layer pattern 210. And interposed between the blocking oxide film 130. In addition, the device isolation layer pattern 161 extends to at least an upper surface of the first conductive layer pattern 181. As a result, the second conductive layer pattern 210 covers upper surfaces of the first conductive layer pattern 181 and the device isolation layer pattern 161. Sidewall thermal oxide layers 151 are formed on sidewalls of the first conductive layer pattern 181 and the second conductive layer pattern 210.

The first conductive layer pattern 181 may be formed of polysilicon, and the second conductive layer pattern 210 may be formed of polysilicon and silicide that are sequentially stacked. In addition, the second conductive layer pattern 210 may further include a silicon nitride layer thereon. The first conductive layer pattern 181 and the second conductive layer pattern 210 constitute a gate conductive layer pattern 300.

When the result is compared with the structure described with reference to FIG. 7, the tunnel oxide layer 110, the nitride layer 120, and the blocking insulating layer 130 are sequentially stacked on the device active region. ) Is defined by the device isolation layer pattern 161 extending to the upper surface of the substrate. In addition, as in FIG. 7, the tunnel oxide film 110 is covered by the nitride film 120 and the blocking oxide film 130 or is covered only by the nitride film 120 between the second conductive film patterns 210. Has

The present invention provides a non-volatile memory device having a SONOS structure covered with a tunnel oxide film, a nitride film and a blocking oxide film, and a method of manufacturing the same, wherein the device active region is formed under the gate conductive film pattern in a thermal oxidation process performed after the gate pattern is formed. The thickening of the tunnel oxide film can be prevented. As a result, characteristics such as the operating speed of the device, the stability of the device, and the uniformity of the cell threshold voltage are improved.

Claims (8)

An isolation layer pattern formed in a predetermined region of the semiconductor substrate and defining an element active region; A plurality of parallel gate conductive layer patterns crossing the upper portion of the device active region and the device isolation layer pattern; And A tunnel oxide film, a nitride film, and a blocking oxide film sequentially stacked between the gate conductive film pattern and the device active region, wherein the device active region between the gate conductive film patterns includes at least the tunnel oxide film and the nitride film; A nonvolatile memory device, characterized in that it is covered by films. The method of claim 1, And the device isolation layer pattern between the gate conductive layer patterns is covered by at least the tunnel oxide layer and the nitride layer extended material layers. The method of claim 1, The gate conductive layer pattern includes a first conductive layer pattern and a second conductive layer pattern, wherein the second conductive layer pattern crosses the device active region and the device isolation layer pattern, and the first conductive layer pattern is the second conductive layer pattern. A nonvolatile memory device having an island shape interposed between a conductive film pattern and the blocking oxide film. The method of claim 3, wherein And the second conductive layer pattern is in direct contact with the device isolation layer pattern. Defining a device active region by forming a device isolation layer pattern in a predetermined region on the semiconductor substrate; Sequentially forming a tunnel oxide film, a nitride film, and a blocking oxide film on an entire surface of the semiconductor substrate including the device isolation film pattern; Forming a gate conductive film on the blocking oxide film; And Patterning the gate conductive layer to form a plurality of parallel gate conductive layer patterns crossing the device active region and the device isolation layer pattern, wherein the devices between the gate conductive layer patterns are patterned while the gate conductive layer is patterned. And at least the tunnel oxide film and the nitride film remaining on an active region and a device isolation layer pattern. The method of claim 5, After forming the gate conductive layer patterns, And thermally oxidizing the semiconductor substrate including the gate conductive layer patterns. Sequentially forming a tunnel oxide film, a nitride film, a blocking oxide film, a first conductive film, and an abrasive blocking film on a semiconductor substrate; Forming a trench region by continuously etching the polishing blocking film, the first conductive film, the blocking oxide film, the nitride film, the tunnel oxide film, and the semiconductor substrate; Forming an isolation pattern in the trench region; Removing the polishing blocking film; Forming a second conductive film on an entire surface of the resultant from which the polishing blocking film is removed; And The second conductive layer and the first conductive layer are successively patterned to form a second conductive layer pattern that crosses the device isolation layer pattern and the upper portion of the device active region, and simultaneously between the second conductive layer pattern and the blocking oxide layer. And forming a first conductive film pattern interposed therebetween, wherein at least the tunnel oxide film and the nitride film are formed on the device active region between the second conductive film patterns while the first and second conductive film patterns are formed. Non-volatile memory device manufacturing method characterized in that the remaining. The method of claim 7, wherein After the forming of the first and second conductive film patterns, And thermally oxidizing the semiconductor substrate having the first and second conductive film patterns.