US20040036110A1 - Semiconductor memory device and method for fabricating the same - Google Patents
Semiconductor memory device and method for fabricating the same Download PDFInfo
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- US20040036110A1 US20040036110A1 US10/648,515 US64851503A US2004036110A1 US 20040036110 A1 US20040036110 A1 US 20040036110A1 US 64851503 A US64851503 A US 64851503A US 2004036110 A1 US2004036110 A1 US 2004036110A1
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- gate electrodes
- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims description 66
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 43
- 229920005591 polysilicon Polymers 0.000 description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 28
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002179 total cell area Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Definitions
- the present invention relates to a semiconductor memory device and a method for fabricating the device, and more particularly relates to a nonvolatile semiconductor memory device of which the floating gate electrode is formed on a side face of the control gate electrode thereof and a method for fabricating the device.
- Flash EEPROM Electrically Erasable Programmable ROM
- Flash EEPROM Electrically Erasable Programmable ROM
- U.S. Pat. No. 5,780,341 disclosed a memory cell structure for a flash EEPROM semiconductor memory device, which includes: a step region formed in the drain region thereof; a floating gate electrode formed so as to overlap with the step region; and a control gate electrode adjacent to the floating gate electrode.
- a memory cell channel hot electrons are created by applying a voltage to the drain region and the control gate electrode. Then, a write operation is carried out by injecting the created hot electrons into the floating gate electrode located over the step region, i.e., in the direction in which the electrons move.
- FIGS. 10A, 10B and 10 C illustrate a structure for the known semiconductor memory device.
- FIG. 10A illustrates a planar layout of the device.
- FIG. 10B illustrates a cross-sectional structure for part of the device including an active region.
- FIG. 10C illustrates a cross-sectional structure for part of the device including an isolation film.
- multiple control gate electrodes 104 are formed over a semiconductor substrate 101 made of silicon with a gate insulating film 103 interposed between the electrodes 104 and the substrate 101 .
- Multiple shallow trench isolations (STIs) 102 are also formed on the substrate 101 so as to be spaced apart from each other in the direction in which the control gate electrodes 104 extend, i.e., in the width direction of the control gate electrodes 104 .
- Each of the STIs 102 crosses with associated ones of the control gate electrodes 104 .
- a floating gate electrode 106 is formed with an insulating film 105 , which will be a capacitance insulating film and a tunnel insulating film, interposed between the floating gate electrode 106 and the control gate electrode 104 .
- the floating gate electrode 106 is located in an active region between adjacent ones of the STIs 102 on the semiconductor substrate 101 .
- a step region 101 a exists in part of the active region under each floating gate electrode 106 . Also, a drain region 107 has been defined in another part of the active region closer to the floating gate electrode 106 and a source region 108 has been defined in still another part of the active region opposite to the floating gate electrode 106 .
- the drain region 107 extends continuously in the gate width direction of the control gate electrode 104 .
- the drain region 107 is shared between multiple cells and thus a drain line can be formed on the semiconductor substrate 101 . Accordingly, it is not necessary to form an additional drain line over the semiconductor substrate 101 with contacts interposed between the drain line and the substrate. Thus, the number of contacts needed can be reduced. As a result, the proportion of the contacts to the total cell area can be reduced, thus contributing to the downsizing of the device.
- FIGS. 11A through 17C illustrate respective process steps for fabricating the known semiconductor memory device.
- A illustrates a planar layout of the structure
- B illustrates a cross-sectional structure including an active region
- C illustrates a cross-sectional structure including STIs.
- multiple slip-shaped STIs 202 are formed on a semiconductor substrate 201 of silicon so as to be spaced apart from each other.
- the exposed surface of the semiconductor substrate 201 is thermally oxidized, thereby forming a first silicon dioxide film on the semiconductor substrate 201 .
- a first polysilicon film and a first insulating film 205 are deposited in this order on the first silicon dioxide film by a CVD process.
- a mask pattern 206 for forming control gate electrodes is defined by a photolithographic process, and the first insulating film 205 , the first polysilicon film and the first silicon dioxide film are dry-etched using the mask pattern 206 .
- control gate electrodes 204 are formed out of the first polysilicon film and control gate insulating films 203 are formed out of the first silicon dioxide film.
- a second insulating film is deposited over the semiconductor substrate 201 by a CVD process. Then, the second insulating film is dry-etched, thereby forming sidewall insulating films 207 out of the second insulating film on the side faces of the control gate electrodes 204 .
- a mask pattern 208 which has an opening over part of the active region of the semiconductor substrate 201 where the drain region will be defined, is defined over the substrate 201 for purpose of forming the step regions by a photolithographic process. Then, the step regions 201 a are defined in the drain forming region of the semiconductor substrate 201 by a dry etching process using the mask pattern 208 , first insulating films 205 and sidewall insulating films 207 as a mask.
- the sidewall insulating films 207 are removed by a wet etching process. Subsequently, the side faces of the control gate electrodes 204 and the step regions 201 a are thermally oxidized, thereby forming a second silicon dioxide film 209 which will be a capacitance insulating film and a tunnel insulating film. Then, a second polysilicon film 210 A is deposited on the second silicon dioxide film 209 by a CVD process.
- a mask pattern 211 which has an opening over the drain forming region to extend in the gate width direction of the control gate electrodes 204 , is defined on the second polysilicon film 210 A by a photolithographic process. Then, the second polysilicon film 210 A is dry-etched using the mask pattern 211 and the first insulating films 205 as a mask, thereby forming sidewall-shaped polysilicon films 210 B out of the second polysilicon film 210 A.
- a mask pattern 212 is defined by a photolithographic process to mask the drain forming regions of the semiconductor substrate 201 and sidewall-shaped polysilicon films 210 B.
- the second polysilicon film 210 A and the sidewall-shaped polysilicon films 210 B are dry-etched using the mask pattern 212 and the first insulating films 205 as a mask, thereby forming island-shaped floating gate electrodes 210 c, overlapping the step regions 201 a , out of the sidewall-shaped polysilicon films 210 B in the drain forming regions.
- drain regions 214 are defined in the drain forming regions and source regions 215 are defined in the source forming regions.
- the etch selectivity of this second polysilicon film 210 A to the second silicon dioxide film 209 is approximately 40. Accordingly, the second silicon dioxide film 209 , which is exposed in the regions identified by the reference numeral 201 b in FIGS. 18A and 18C and has a thickness of 9 nm, partially breaks. As a result, the semiconductor substrate 201 is etched unintentionally and part of the doped layer located between the STIs 202 disconnects.
- Another problem relates to the mask pattern 212 shown in FIG. 16A for masking the drain forming regions of the substrate and sidewall-shaped polysilicon films 210 B.
- the mask pattern 212 actually formed often has its corner rounded like the mask pattern 212 A shown in FIG. 19, thus possibly deteriorating the resultant size accuracy.
- a size of the mask pattern should be allowed a relatively great margin.
- each of the STIs 202 should have its size increased in the gate width direction of the control gate electrodes 204 , and therefore the area of each cell cannot be reduced.
- a first object of the present invention is to keep the doped regions from being disconnected.
- a second object of the present invention is to reduce the total area of a memory cell.
- isolations with a continuous striped pattern are formed for respective memory cells.
- the unnecessary parts of the second conductive film to be the floating gate electrodes are not removed at a time from over the isolations and the source-to-be regions. Instead, those excessive parts of the second conductive film are removed from over the isolations first and then the remaining parts of the second conductive film are removed from over the source-to-be regions.
- a semiconductor memory device includes isolations, active regions, control gate electrodes and floating gate electrodes.
- the isolations are formed on a semiconductor substrate.
- the active regions are defined on the semiconductor substrate and isolated from each other by the isolations.
- the control gate electrodes are formed over the semiconductor substrate.
- Each of the control gate electrodes crosses all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate.
- Each of the floating gate electrodes is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes.
- the isolations are spaced apart from each other along the width of the control gate electrodes and each of the isolations crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes.
- the isolations are spaced apart from each other along the width of the control gate electrodes.
- Each of the isolations crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes. Accordingly, when an etching process is carried out to form the floating gate electrodes, the semiconductor substrate is no longer etched unintentionally. Therefore, no doped regions are disconnected.
- the inventive memory device may further include a third insulating film formed on each of the control gate electrodes.
- each of the active regions may have a plurality of step regions, each of which may be overlapped by associated one of the floating gate electrodes.
- source regions may be defined in respective upper parts of the step regions and a drain region may be defined below the step region. Then, channel hot electrons, created during a writing operation, can be injected into the floating gate electrodes much more efficiently.
- an inventive method for fabricating a semiconductor memory device includes the step of a) forming a plurality of isolations on a semiconductor substrate, thereby defining a plurality of active regions, which have been isolated from each other by the isolations, on the semiconductor substrate.
- the method further includes the step of b) forming a first insulating film and a first conductive film in this order over the semiconductor substrate and then selectively etching the first conductive film, thereby forming a control gate electrode out of the first conductive film so that the control gate electrode crosses all of the isolations and all of the active regions.
- the method further includes the step of c) forming a second insulating film and a second conductive film in this order over the semiconductor substrate as well as over the isolations and the control gate electrode and then selectively etching parts of the second conductive film, thereby forming floating gate electrodes out of the second conductive film for the active regions so that the floating gate electrodes cover a side face of the control gate electrode.
- the method further includes the step of d) implanting ions into the semiconductor substrate using the control gate electrode and the floating gate electrodes as a mask, thereby defining source and drain regions in each said active region.
- the step c) includes: forming and selectively etching the second conductive film to form a sidewall-shaped conductive film out of the second conductive film on the side face of the control gate electrode; removing parts of the sidewall-shaped conductive film and parts of the second conductive film from over the isolations; and removing remaining parts of the second conductive film from upper and another side faces of the control gate electrode, thereby forming the floating gate electrodes as islands out of the sidewall-shaped conductive film on the side of the control gate electrode.
- the active regions and the members located over the active regions can be masked continuously in the gate length direction.
- the mask pattern does not have to consist of the known isolated elements. Therefore, there is no need to worry about the rounding at the corners of the isolated pattern elements.
- a margin that should be allowed for the mask pattern can be reduced.
- each of the isolations can have its size reduced in the gate width direction of the control gate electrode, and therefore the area of each cell can be reduced. Accordingly, the memory cells can have their size reduced and can be integrated much more densely.
- the step a) may include forming the isolations in a striped pattern on the semiconductor substrate so that the isolations are spaced apart from each other along the width of the control gate electrode. Then, the first object can also be achieved, and therefore no doped regions are disconnected between adjacent ones of the isolations.
- the step b) may include forming a third insulating film on the first conductive film and then etching the third insulating film and the first conductive film. Then, in the etching process step for forming the floating gate electrodes out of the second conductive film, the upper face of the control gate electrode that has been formed out of the first conductive film can be protected as intended by the third insulating film that covers the control gate electrodes.
- the step c) may include forming a sidewall insulating film on side faces of the control gate electrode with the second insulating film interposed between the sidewall insulating film and the control gate electrode.
- the step c) may further include etching parts of the semiconductor substrate, which parts are located below the side face of the control gate electrode, using the sidewall insulating film as a mask, thereby forming a plurality of step regions for the active regions.
- FIG. 1 is a partial plan view illustrating a semiconductor memory device according to an embodiment of the present invention.
- FIG. 2A, 2B and 2 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 2A is a partial plan view
- FIG. 2B is a cross-sectional view taken along the line IIb-IIb shown in FIG. 2A
- FIG. 2C is a cross-sectional view taken along the line IIc-IIc shown in FIG. 2A.
- FIG. 3A, 3B and 3 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 3A is a partial plan view
- FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb shown in FIG. 3 A
- FIG. 3C is a cross-sectional view taken along the line IIIc-IIIc shown in FIG. 3A.
- FIG. 4A, 4B and 4 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 4A is a partial plan view
- FIG. 4B is a cross-sectional view taken along the line IVb-IVb shown in FIG. 4A
- FIG. 4C is a cross-sectional view taken along the line IVc-IVc shown in FIG. 4A.
- FIG. 5A, 5B and 5 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 5A is a partial plan view
- FIG. 5B is a cross-sectional view taken along the line Vb-Vb shown in FIG. 5A
- FIG. 5C is a cross-sectional view taken along the line Vc-Vc shown in FIG. 5A.
- FIG. 6A, 6B and 6 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 6A is a partial plan view
- FIG. 6B is a cross-sectional view taken along the line VIb-VIb shown in FIG. 6A
- FIG. 6C is a cross-sectional view taken along the line VIc-VIc shown in FIG. 6A.
- FIG. 7A, 7B and 7 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 7A is a partial plan view
- FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb shown in FIG. 7A
- FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc shown in FIG. 7A.
- FIG. 8A, 8B and 8 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 8A is a partial plan view
- FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb shown in FIG. 8A
- FIG. 8C is a cross-sectional view taken along the line VIIIc-VIIIc shown in FIG. 8A.
- FIG. 9A, 9B and 9 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 9A is a partial plan view
- FIG. 9B is a cross-sectional view taken along the line IXb-IXb shown in FIG. 9A
- FIG. 9C is a cross-sectional view taken along the line IXc-IXc shown in FIG. 9A.
- FIGS. 10A, 10B and 10 C illustrate the known semiconductor memory device:
- FIG. 10A is a partial plan view
- FIG. 10B is a cross-sectional view taken along the line Xb-Xb shown in FIG. 10A
- FIG. 10C is a cross-sectional view taken along the line Xc-Xc shown in FIG. 10A.
- FIG. 11A, 11B and 11 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 11A is a partial plan view
- FIG. 11B is a cross-sectional view taken along the line XIb-XIb shown in FIG. 11A
- FIG. 11C is a cross-sectional view taken along the line XIc-XIc shown in FIG. 11A.
- FIGS. 12A, 12B and 12 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 12A is a partial plan view
- FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb shown in FIG. 12A
- FIG. 12C is a cross-sectional view taken along the line XIIc-XIIc shown in FIG. 12A.
- FIG. 13A, 13B and 13 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 13A is a partial plan view
- FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb shown in FIG. 13A
- FIG. 13C is a cross-sectional view taken along the line XIIIc-XIIIc shown in FIG. 13A.
- FIG. 14A, 14B and 14 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 14A is a partial plan view
- FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb shown in FIG. 14A
- FIG. 14C is a cross-sectional view taken along the line XIVc-XIVc shown in FIG. 14A.
- FIGS. 15A, 15B and 15 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 15A is a partial plan view
- FIG. 15B is a cross-sectional view taken along the line XVb-XVb shown in FIG. 15A
- FIG. 15C is a cross-sectional view taken along the line XVc-XVc shown in FIG. 15A.
- FIG. 16A, 16B and 16 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 16A is a partial plan view
- FIG. 16B is a cross-sectional view taken along the line XVIb-XVIb shown in FIG. 16A
- FIG. 16C is a cross-sectional view taken along the line XVIc-XVIc shown in FIG. 16A.
- FIGS. 17A, 17B and 17 C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 17A is a partial plan view
- FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb shown in FIG. 17A
- FIG. 17C is a cross-sectional view taken along the line XVIIc-XVIIc shown in FIG. 17A.
- FIGS. 18A, 18B and 18 C illustrate how the doped regions are disconnected in the known method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 18A is a partial plan view
- FIG. 18B is a cross-sectional view taken along the line XVIIIb-XVIIIb shown in FIG. 18A
- FIG. 18C is a cross-sectional view taken along the line XVIIIc-XVIIIc shown in FIG. 18A.
- FIG. 19 is a plan view schematically illustrating how the mask pattern has its corners rounded and its size accuracy deteriorated in the known method for fabricating the semiconductor memory device shown in FIG. 10.
- FIG. 1 illustrates a planar layout for a semiconductor memory device according to an embodiment of the present invention.
- multiple control gate electrodes 4 are formed over a semiconductor substrate 1 of silicon (Si) with a gate insulating film (not shown in FIG. 1) interposed between the control gate electrodes 4 and the semiconductor substrate 1 .
- Multiple shallow trench isolations (STIs) 2 are also formed in a striped pattern on the semiconductor substrate 1 so as to be spaced apart from each other in the direction in which the control gate electrodes 4 extend, i.e., in the width direction of the control gate electrodes 4 .
- Each of the STIs 2 crosses all of the control gate electrodes 4 .
- island-shaped floating gate electrodes 6 are formed for each active region located between adjacent ones of the STIs 2 on the semiconductor substrate 1 with an insulating film (not shown in FIG. 1) interposed between the floating gate electrode 6 and the control gate electrode 4 .
- Each of the floating gate electrodes 6 has its ends in the gate width direction positioned on associated ones of the STIs 2 .
- part of the insulating film sandwiched between the control gate electrode 4 and the floating gate electrode 6 will be a capacitance insulating film.
- Another part of the insulating film sandwiched between the active region and the floating gate electrode 6 will be a tunnel insulating film.
- a step region exists in part of the active region under each floating gate electrode 6 . Also, a drain region 7 has been defined in another part of the active region closer to the floating gate electrode 6 and a source region 8 has been defined in still another part of the active region opposite to the floating gate electrode 6 .
- FIGS. 2A through 9C illustrate respective process steps for fabricating the semiconductor memory device of this embodiment.
- A illustrates a partial planar layout of the structure
- B illustrates a cross-sectional view of the structure shown in A including an active region
- C illustrates a cross-sectional view of the structure shown in A including an STI.
- multiple STIs 12 are formed in a striped pattern on a semiconductor substrate 11 of silicon so as to be spaced apart from each other.
- active regions 11 a isolated from each other by the STIs 12 , are defined in a striped pattern on the semiconductor substrate 11 .
- the exposed surface of the semiconductor substrate 11 is thermally oxidized, thereby forming a first silicon dioxide film, which has a thickness of about 9 nm, over the semiconductor substrate 11 .
- a first polysilicon film and a silicon nitride film 15 are deposited by a CVD process in this order on the first silicon dioxide film to about 200 nm and about 150 nm, respectively.
- a mask pattern 16 for forming control gate electrodes is defined by a photolithographic process, and the silicon nitride film 15 , the first polysilicon film and the first silicon dioxide film are dry-etched using the mask pattern 16 . In this manner, control gate electrodes 14 are formed out of the first polysilicon film and control gate insulating films 13 are formed out of the first silicon dioxide film.
- an HTO (high temperature oxide) film and a silicon nitride film are deposited by a CVD process to about 5 nm and about 10 nm, respectively, over the semiconductor substrate 11 as well as over the control gate electrodes 14 and the silicon nitride films 15 .
- capacitance insulating films 17 are formed.
- a BPSG film made of a silicon dioxide containing boron and phosphorus is deposited over the semiconductor substrate 11 .
- the BPSG film is dry-etched, thereby forming sidewall insulating films 18 out of the BPSG film on the side faces of the control gate electrodes 14 .
- a mask pattern 19 which exposes the drain forming regions of the active regions 11 a in the gate width direction of the control gate electrodes 14 , is defined over the substrate 11 by a photolithographic process for the purpose of forming the step regions. Then, the semiconductor substrate 11 is dry-etched isotropically using the mask pattern 19 , the silicon nitride films 15 and the sidewall insulating films 18 as a mask, thereby forming step regions 11 b to a depth of about 40 nm in the drain forming regions of the semiconductor substrate 11 .
- etching process using vapor phase hydrogen fluoride is carried out to remove the sidewall insulating films 18 .
- the step regions 11 b have their surface thermally oxidized, thereby forming tunnel insulating films 20 of silicon dioxide.
- a second polysilicon film 21 A is deposited by a CVD process to a thickness of about 100 nm over the semiconductor substrate 11 as well as over the control gate electrodes 14 and the silicon nitride films 15 .
- a mask pattern 22 which exposes the drain forming regions of the active regions 11 a and the STIs 12 in the gate width direction of the control gate electrodes 14 , is defined by a photolithographic process on the second polysilicon film 21 A.
- the second polysilicon film 21 A is dry-etched anisotropically using the mask pattern 22 and the silicon nitride films 15 as a mask, thereby forming sidewall-shaped polysilicon films 21 B overlapping the step regions 11 b out of the second polysilicon film 21 A.
- a mask pattern 23 which exposes the STIs 12 (i.e., masks the active regions 11 a ), is defined by a photolithographic process over the semiconductor substrate 11 .
- the second polysilicon film 21 A and the sidewall-shaped polysilicon films 21 B are dry-etched anisotropically using the mask pattern 23 .
- island-shaped floating gate electrodes 21 C overlapping the step regions 11 b, are formed out of the sidewall-shaped polysilicon films 21 B in the drain forming regions of the active regions 11 a.
- Each of the floating gate electrodes 21 C has its ends in the gate width direction positioned on associated ones of the STIs 12 . That is to say, multiple floating gate electrodes 21 C are formed for each control gate electrode.
- a mask pattern 24 which exposes the source forming regions of the active regions 11 a and the STIs 12 in the gate width direction of the control gate electrodes 14 , is defined by a photolithographic process. Then, an isotropic dry etching process is carried out using the mask pattern 24 and the silicon nitride films 15 as a mask to remove the remaining parts of the second polysilicon film 21 A located over the source forming regions.
- the process step of removing those parts of the second polysilicon film 21 A and the sidewall-shaped polysilicon films 21 B from over the STIs 12 as shown in FIGS. 7A, 7B and 7 C and the process step of removing the remaining parts of the second polysilicon film 21 A from over the source forming regions as shown in FIGS. 8A, 8B and 8 C may be carried out in reverse order.
- arsenic (As) ions are implanted into the semiconductor substrate 11 at a dose of 6 ⁇ 10 15 /cm 2 and with an acceleration voltage of 40 keV applied using the silicon nitride films 15 and the floating gate electrodes 21 C as a mask.
- drain regions 25 are defined in the drain forming regions and source regions 26 are defined in the source forming regions.
- the STIs 12 for isolating adjacent ones of the memory cells from each other in the gate width direction of the control gate electrodes 14 are formed in a striped pattern on the semiconductor substrate 11 . That is to say, the STIs 12 are spaced apart from each other in the gate width direction. Also, each of the STIs 12 crosses all of the control gate electrodes 14 and extends continuously in the length direction of the gate electrodes.
- FIG. 7C when those parts of the second polysilicon film 21 A and the sidewall-shaped polysilicon films 21 B are etched away from over the STIs 12 , the exposed tunnel insulating film 20 should not break and the semiconductor substrate 11 should no longer be etched unintentionally. Therefore, no doped region should be disconnected.
- the second polysilicon film 21 A for forming the floating gate electrodes 21 C is not patterned at a time in a single process step. Specifically, parts of the second polysilicon film 21 A and the sidewall-shaped polysilicon films 21 B are removed from over the STIs 12 in the process step shown in FIGS. 7A, 7B and 7 C. Subsequently, the remaining parts of the second polysilicon film 21 A are removed from over the source forming regions in the process step shown in FIGS. 8A, 8B and 8 C.
- the active regions 11 a and members located over the regions 11 a can be masked continuously in the gate length direction.
- the mask pattern 23 does not have to be an isolated one. Therefore, there is no need to worry about the rounding of the corners of the mask pattern 23 . Then, a margin that should be allowed for the mask pattern can be reduced.
- each of the STIs 12 can have its size reduced in the gate width direction of the control gate electrodes 14 , and therefore the area of each cell can be reduced.
- the size accuracy of the mask pattern can be improved, and thus the total cell area can be reduced. Therefore, a semiconductor memory device, including floating and control gate electrodes that are formed side by side on a semiconductor substrate, can have its size reduced and its performance enhanced greatly.
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Abstract
A semiconductor memory device according to the present invention includes isolations, active regions, control gate electrodes and floating gate electrodes. The isolations are formed on a semiconductor substrate. The active regions are defined on the semiconductor substrate and isolated from each other by the isolations. The control gate electrodes are formed over the semiconductor substrate. Each of the control gate electrodes crosses all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate. Each of the floating gate electrodes is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes. In this device, the isolations are spaced apart from each other along the width of the control gate electrodes and each of the isolations crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes.
Description
- The present invention relates to a semiconductor memory device and a method for fabricating the device, and more particularly relates to a nonvolatile semiconductor memory device of which the floating gate electrode is formed on a side face of the control gate electrode thereof and a method for fabricating the device.
- Flash EEPROM (Electrically Erasable Programmable ROM) devices are well known as electrically erasable and programmable nonvolatile memory devices.
- Recently, U.S. Pat. No. 5,780,341 disclosed a memory cell structure for a flash EEPROM semiconductor memory device, which includes: a step region formed in the drain region thereof; a floating gate electrode formed so as to overlap with the step region; and a control gate electrode adjacent to the floating gate electrode. In this memory cell, channel hot electrons are created by applying a voltage to the drain region and the control gate electrode. Then, a write operation is carried out by injecting the created hot electrons into the floating gate electrode located over the step region, i.e., in the direction in which the electrons move.
- Hereinafter, the known semiconductor memory device including the step region in its drain region will be described with reference to the accompanying drawings.
- FIGS. 10A, 10B and10C illustrate a structure for the known semiconductor memory device. FIG. 10A illustrates a planar layout of the device. FIG. 10B illustrates a cross-sectional structure for part of the device including an active region. FIG. 10C illustrates a cross-sectional structure for part of the device including an isolation film.
- As shown in FIGS. 10A, 10B and10C, multiple
control gate electrodes 104 are formed over asemiconductor substrate 101 made of silicon with agate insulating film 103 interposed between theelectrodes 104 and thesubstrate 101. Multiple shallow trench isolations (STIs) 102 are also formed on thesubstrate 101 so as to be spaced apart from each other in the direction in which thecontrol gate electrodes 104 extend, i.e., in the width direction of thecontrol gate electrodes 104. Each of theSTIs 102 crosses with associated ones of thecontrol gate electrodes 104. - On a side face of each of the
control gate electrodes 104, afloating gate electrode 106 is formed with aninsulating film 105, which will be a capacitance insulating film and a tunnel insulating film, interposed between the floatinggate electrode 106 and thecontrol gate electrode 104. Thefloating gate electrode 106 is located in an active region between adjacent ones of theSTIs 102 on thesemiconductor substrate 101. - As shown in FIG. 10B, a
step region 101 a exists in part of the active region under eachfloating gate electrode 106. Also, adrain region 107 has been defined in another part of the active region closer to thefloating gate electrode 106 and asource region 108 has been defined in still another part of the active region opposite to thefloating gate electrode 106. - As shown in FIGS. 10B and 10C, the
drain region 107 extends continuously in the gate width direction of thecontrol gate electrode 104. In this manner, in the known semiconductor memory device, thedrain region 107 is shared between multiple cells and thus a drain line can be formed on thesemiconductor substrate 101. Accordingly, it is not necessary to form an additional drain line over thesemiconductor substrate 101 with contacts interposed between the drain line and the substrate. Thus, the number of contacts needed can be reduced. As a result, the proportion of the contacts to the total cell area can be reduced, thus contributing to the downsizing of the device. - Hereinafter, a method for fabricating the known semiconductor memory device will be described with reference to the accompanying drawings.
- FIGS. 11A through 17C illustrate respective process steps for fabricating the known semiconductor memory device. In each of these drawings, A illustrates a planar layout of the structure, B illustrates a cross-sectional structure including an active region and C illustrates a cross-sectional structure including STIs.
- First, as shown in FIGS. 11A, 11B and11C, multiple slip-
shaped STIs 202 are formed on asemiconductor substrate 201 of silicon so as to be spaced apart from each other. - Next, as shown in FIGS. 12A, 12B and12C, the exposed surface of the
semiconductor substrate 201 is thermally oxidized, thereby forming a first silicon dioxide film on thesemiconductor substrate 201. Then, a first polysilicon film and a firstinsulating film 205 are deposited in this order on the first silicon dioxide film by a CVD process. Then, amask pattern 206 for forming control gate electrodes is defined by a photolithographic process, and the firstinsulating film 205, the first polysilicon film and the first silicon dioxide film are dry-etched using themask pattern 206. In this manner,control gate electrodes 204 are formed out of the first polysilicon film and controlgate insulating films 203 are formed out of the first silicon dioxide film. - Next, as shown in FIGS. 13A, 13B and13C, after the
mask pattern 206 has been removed, a second insulating film is deposited over thesemiconductor substrate 201 by a CVD process. Then, the second insulating film is dry-etched, thereby formingsidewall insulating films 207 out of the second insulating film on the side faces of thecontrol gate electrodes 204. - Next, as shown in FIGS. 14A, 14B and14C, a
mask pattern 208, which has an opening over part of the active region of thesemiconductor substrate 201 where the drain region will be defined, is defined over thesubstrate 201 for purpose of forming the step regions by a photolithographic process. Then, thestep regions 201 a are defined in the drain forming region of thesemiconductor substrate 201 by a dry etching process using themask pattern 208, firstinsulating films 205 and sidewallinsulating films 207 as a mask. - Then, as shown in FIGS. 15A, 15B and15C, after the
mask pattern 208 has been removed, thesidewall insulating films 207 are removed by a wet etching process. Subsequently, the side faces of thecontrol gate electrodes 204 and thestep regions 201 a are thermally oxidized, thereby forming a secondsilicon dioxide film 209 which will be a capacitance insulating film and a tunnel insulating film. Then, asecond polysilicon film 210A is deposited on the secondsilicon dioxide film 209 by a CVD process. Thereafter, amask pattern 211, which has an opening over the drain forming region to extend in the gate width direction of thecontrol gate electrodes 204, is defined on thesecond polysilicon film 210A by a photolithographic process. Then, thesecond polysilicon film 210A is dry-etched using themask pattern 211 and the firstinsulating films 205 as a mask, thereby forming sidewall-shaped polysilicon films 210B out of thesecond polysilicon film 210A. - Subsequently, as shown in FIGS. 16A, 16B and16C, after the
mask pattern 211 has been removed, amask pattern 212 is defined by a photolithographic process to mask the drain forming regions of thesemiconductor substrate 201 and sidewall-shaped polysilicon films 210B. Then, thesecond polysilicon film 210A and the sidewall-shaped polysilicon films 210B are dry-etched using themask pattern 212 and the firstinsulating films 205 as a mask, thereby forming island-shaped floating gate electrodes 210 c, overlapping thestep regions 201 a, out of the sidewall-shaped polysilicon films 210B in the drain forming regions. - Next, as shown in FIGS. 17A, 17B and17C, after the
mask pattern 212 has been removed, arsenic ions are implanted using the firstinsulating films 205 and thefloating gate electrodes 210C as a mask. In this manner,drain regions 214 are defined in the drain forming regions andsource regions 215 are defined in the source forming regions. - The known fabrication process, however, has the following two problems.
- First, when the
second polysilicon film 210A and those parts of the sidewall-shaped polysilicon films 210B located over theSTIs 202 are removed using themask pattern 212 shown in FIGS. 16A and 16B, an anisotropic etching process is carried out to obtain thefloating gate electrodes 210C in good shape out of the sidewall-shaped polysilicon films 210B. In this case, the upper face of thesecond polysilicon film 210A on theSTIs 202 has a height of approximately 450 nm, when the thicknesses of thecontrol gate electrodes 204, the firstinsulating films 205 and thesecond polysilicon film 210A are 200 nm, 150 nm and 100 nm, respectively, as shown in FIG. 15. When thesecond polysilicon film 210A is etched away, the etch selectivity of thissecond polysilicon film 210A to the secondsilicon dioxide film 209 is approximately 40. Accordingly, the secondsilicon dioxide film 209, which is exposed in the regions identified by thereference numeral 201 b in FIGS. 18A and 18C and has a thickness of 9 nm, partially breaks. As a result, thesemiconductor substrate 201 is etched unintentionally and part of the doped layer located between theSTIs 202 disconnects. - Another problem relates to the
mask pattern 212 shown in FIG. 16A for masking the drain forming regions of the substrate and sidewall-shapedpolysilicon films 210B. Specifically, themask pattern 212 actually formed often has its corner rounded like themask pattern 212A shown in FIG. 19, thus possibly deteriorating the resultant size accuracy. To avoid such an unfavorable situation, a size of the mask pattern should be allowed a relatively great margin. As a result, each of theSTIs 202 should have its size increased in the gate width direction of thecontrol gate electrodes 204, and therefore the area of each cell cannot be reduced. - A first object of the present invention is to keep the doped regions from being disconnected.
- A second object of the present invention is to reduce the total area of a memory cell.
- In order to achieve the first object, according to this invention, isolations with a continuous striped pattern are formed for respective memory cells. Also, to achieve the second object, according to an inventive method for fabricating a semiconductor memory device, the unnecessary parts of the second conductive film to be the floating gate electrodes are not removed at a time from over the isolations and the source-to-be regions. Instead, those excessive parts of the second conductive film are removed from over the isolations first and then the remaining parts of the second conductive film are removed from over the source-to-be regions.
- Specifically, to achieve the first object, a semiconductor memory device according to the present invention includes isolations, active regions, control gate electrodes and floating gate electrodes. The isolations are formed on a semiconductor substrate. The active regions are defined on the semiconductor substrate and isolated from each other by the isolations. The control gate electrodes are formed over the semiconductor substrate. Each of the control gate electrodes crosses all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate. Each of the floating gate electrodes is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes. In this device, the isolations are spaced apart from each other along the width of the control gate electrodes and each of the isolations crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes.
- In the inventive semiconductor memory device, the isolations are spaced apart from each other along the width of the control gate electrodes. Each of the isolations crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes. Accordingly, when an etching process is carried out to form the floating gate electrodes, the semiconductor substrate is no longer etched unintentionally. Therefore, no doped regions are disconnected.
- In one embodiment of this invention, the inventive memory device may further include a third insulating film formed on each of the control gate electrodes.
- In another embodiment, each of the active regions may have a plurality of step regions, each of which may be overlapped by associated one of the floating gate electrodes. In each of the active regions, source regions may be defined in respective upper parts of the step regions and a drain region may be defined below the step region. Then, channel hot electrons, created during a writing operation, can be injected into the floating gate electrodes much more efficiently.
- To achieve the second object, an inventive method for fabricating a semiconductor memory device includes the step of a) forming a plurality of isolations on a semiconductor substrate, thereby defining a plurality of active regions, which have been isolated from each other by the isolations, on the semiconductor substrate. The method further includes the step of b) forming a first insulating film and a first conductive film in this order over the semiconductor substrate and then selectively etching the first conductive film, thereby forming a control gate electrode out of the first conductive film so that the control gate electrode crosses all of the isolations and all of the active regions. The method further includes the step of c) forming a second insulating film and a second conductive film in this order over the semiconductor substrate as well as over the isolations and the control gate electrode and then selectively etching parts of the second conductive film, thereby forming floating gate electrodes out of the second conductive film for the active regions so that the floating gate electrodes cover a side face of the control gate electrode. And the method further includes the step of d) implanting ions into the semiconductor substrate using the control gate electrode and the floating gate electrodes as a mask, thereby defining source and drain regions in each said active region. In this method, the step c) includes: forming and selectively etching the second conductive film to form a sidewall-shaped conductive film out of the second conductive film on the side face of the control gate electrode; removing parts of the sidewall-shaped conductive film and parts of the second conductive film from over the isolations; and removing remaining parts of the second conductive film from upper and another side faces of the control gate electrode, thereby forming the floating gate electrodes as islands out of the sidewall-shaped conductive film on the side of the control gate electrode.
- In the inventive method, when the excessive parts of the sidewall-shaped conductive film and the second conductive film are etched away from over the isolations in the step c), the active regions and the members located over the active regions can be masked continuously in the gate length direction. Thus, the mask pattern does not have to consist of the known isolated elements. Therefore, there is no need to worry about the rounding at the corners of the isolated pattern elements. Thus, a margin that should be allowed for the mask pattern can be reduced. As a result, each of the isolations can have its size reduced in the gate width direction of the control gate electrode, and therefore the area of each cell can be reduced. Accordingly, the memory cells can have their size reduced and can be integrated much more densely.
- In one embodiment of this invention, the step a) may include forming the isolations in a striped pattern on the semiconductor substrate so that the isolations are spaced apart from each other along the width of the control gate electrode. Then, the first object can also be achieved, and therefore no doped regions are disconnected between adjacent ones of the isolations.
- In another embodiment, the step b) may include forming a third insulating film on the first conductive film and then etching the third insulating film and the first conductive film. Then, in the etching process step for forming the floating gate electrodes out of the second conductive film, the upper face of the control gate electrode that has been formed out of the first conductive film can be protected as intended by the third insulating film that covers the control gate electrodes.
- In still another embodiment, the step c) may include forming a sidewall insulating film on side faces of the control gate electrode with the second insulating film interposed between the sidewall insulating film and the control gate electrode. The step c) may further include etching parts of the semiconductor substrate, which parts are located below the side face of the control gate electrode, using the sidewall insulating film as a mask, thereby forming a plurality of step regions for the active regions.
- FIG. 1 is a partial plan view illustrating a semiconductor memory device according to an embodiment of the present invention.
- FIGS. 2A, 2B and2C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 2A is a partial plan view; FIG. 2B is a cross-sectional view taken along the line IIb-IIb shown in FIG. 2A; and FIG. 2C is a cross-sectional view taken along the line IIc-IIc shown in FIG. 2A.
- FIGS. 3A, 3B and3C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 3A is a partial plan view; FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb shown in FIG.3A; and FIG. 3C is a cross-sectional view taken along the line IIIc-IIIc shown in FIG. 3A.
- FIGS. 4A, 4B and4C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 4A is a partial plan view; FIG. 4B is a cross-sectional view taken along the line IVb-IVb shown in FIG. 4A; and FIG. 4C is a cross-sectional view taken along the line IVc-IVc shown in FIG. 4A.
- FIGS. 5A, 5B and5C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 5A is a partial plan view; FIG. 5B is a cross-sectional view taken along the line Vb-Vb shown in FIG. 5A; and FIG. 5C is a cross-sectional view taken along the line Vc-Vc shown in FIG. 5A.
- FIGS. 6A, 6B and6C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 6A is a partial plan view; FIG. 6B is a cross-sectional view taken along the line VIb-VIb shown in FIG. 6A; and FIG. 6C is a cross-sectional view taken along the line VIc-VIc shown in FIG. 6A.
- FIGS. 7A, 7B and7C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 7A is a partial plan view; FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb shown in FIG. 7A; and FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc shown in FIG. 7A.
- FIGS. 8A, 8B and8C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 8A is a partial plan view; FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb shown in FIG. 8A; and FIG. 8C is a cross-sectional view taken along the line VIIIc-VIIIc shown in FIG. 8A.
- FIGS. 9A, 9B and9C illustrate a method for fabricating the semiconductor memory device shown in FIG. 1:
- FIG. 9A is a partial plan view; FIG. 9B is a cross-sectional view taken along the line IXb-IXb shown in FIG. 9A; and FIG. 9C is a cross-sectional view taken along the line IXc-IXc shown in FIG. 9A.
- FIGS. 10A, 10B and10C illustrate the known semiconductor memory device:
- FIG. 10A is a partial plan view; FIG. 10B is a cross-sectional view taken along the line Xb-Xb shown in FIG. 10A; and FIG. 10C is a cross-sectional view taken along the line Xc-Xc shown in FIG. 10A.
- FIGS. 11A, 11B and11C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 11A is a partial plan view; FIG. 11B is a cross-sectional view taken along the line XIb-XIb shown in FIG. 11A; and FIG. 11C is a cross-sectional view taken along the line XIc-XIc shown in FIG. 11A.
- FIGS. 12A, 12B and12C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 12A is a partial plan view; FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb shown in FIG. 12A; and FIG. 12C is a cross-sectional view taken along the line XIIc-XIIc shown in FIG. 12A.
- FIGS. 13A, 13B and13C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 13A is a partial plan view; FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb shown in FIG. 13A; and FIG. 13C is a cross-sectional view taken along the line XIIIc-XIIIc shown in FIG. 13A.
- FIGS. 14A, 14B and14C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 14A is a partial plan view; FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb shown in FIG. 14A; and FIG. 14C is a cross-sectional view taken along the line XIVc-XIVc shown in FIG. 14A.
- FIGS. 15A, 15B and15C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 15A is a partial plan view; FIG. 15B is a cross-sectional view taken along the line XVb-XVb shown in FIG. 15A; and FIG. 15C is a cross-sectional view taken along the line XVc-XVc shown in FIG. 15A.
- FIGS. 16A, 16B and16C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 16A is a partial plan view; FIG. 16B is a cross-sectional view taken along the line XVIb-XVIb shown in FIG. 16A; and FIG. 16C is a cross-sectional view taken along the line XVIc-XVIc shown in FIG. 16A.
- FIGS. 17A, 17B and17C illustrate a method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 17A is a partial plan view; FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb shown in FIG. 17A; and FIG. 17C is a cross-sectional view taken along the line XVIIc-XVIIc shown in FIG. 17A.
- FIGS. 18A, 18B and18C illustrate how the doped regions are disconnected in the known method for fabricating the semiconductor memory device shown in FIG. 10:
- FIG. 18A is a partial plan view; FIG. 18B is a cross-sectional view taken along the line XVIIIb-XVIIIb shown in FIG. 18A; and FIG. 18C is a cross-sectional view taken along the line XVIIIc-XVIIIc shown in FIG. 18A.
- FIG. 19 is a plan view schematically illustrating how the mask pattern has its corners rounded and its size accuracy deteriorated in the known method for fabricating the semiconductor memory device shown in FIG. 10.
- Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
- FIG. 1 illustrates a planar layout for a semiconductor memory device according to an embodiment of the present invention.
- As shown in FIG. 1, multiple
control gate electrodes 4 are formed over asemiconductor substrate 1 of silicon (Si) with a gate insulating film (not shown in FIG. 1) interposed between thecontrol gate electrodes 4 and thesemiconductor substrate 1. Multiple shallow trench isolations (STIs) 2 are also formed in a striped pattern on thesemiconductor substrate 1 so as to be spaced apart from each other in the direction in which thecontrol gate electrodes 4 extend, i.e., in the width direction of thecontrol gate electrodes 4. Each of theSTIs 2 crosses all of thecontrol gate electrodes 4. - On a side face of each of the
control gate electrodes 4, island-shaped floatinggate electrodes 6 are formed for each active region located between adjacent ones of theSTIs 2 on thesemiconductor substrate 1 with an insulating film (not shown in FIG. 1) interposed between the floatinggate electrode 6 and thecontrol gate electrode 4. Each of the floatinggate electrodes 6 has its ends in the gate width direction positioned on associated ones of theSTIs 2. In this structure, part of the insulating film sandwiched between thecontrol gate electrode 4 and the floatinggate electrode 6 will be a capacitance insulating film. Another part of the insulating film sandwiched between the active region and the floatinggate electrode 6 will be a tunnel insulating film. - As will be described later, a step region exists in part of the active region under each floating
gate electrode 6. Also, adrain region 7 has been defined in another part of the active region closer to the floatinggate electrode 6 and a source region 8 has been defined in still another part of the active region opposite to the floatinggate electrode 6. - Hereinafter, a method for fabricating a semiconductor memory device having this structure will be described with reference to the accompanying drawings.
- FIGS. 2A through 9C illustrate respective process steps for fabricating the semiconductor memory device of this embodiment. In each of these drawings, A illustrates a partial planar layout of the structure, B illustrates a cross-sectional view of the structure shown in A including an active region and C illustrates a cross-sectional view of the structure shown in A including an STI.
- First, as shown in FIGS. 2A, 2B and2C,
multiple STIs 12 are formed in a striped pattern on asemiconductor substrate 11 of silicon so as to be spaced apart from each other. In this manner,active regions 11 a, isolated from each other by theSTIs 12, are defined in a striped pattern on thesemiconductor substrate 11. - Next, as shown in FIGS. 3A, 3B and3C, the exposed surface of the
semiconductor substrate 11 is thermally oxidized, thereby forming a first silicon dioxide film, which has a thickness of about 9 nm, over thesemiconductor substrate 11. Then, a first polysilicon film and asilicon nitride film 15 are deposited by a CVD process in this order on the first silicon dioxide film to about 200 nm and about 150 nm, respectively. Then, amask pattern 16 for forming control gate electrodes is defined by a photolithographic process, and thesilicon nitride film 15, the first polysilicon film and the first silicon dioxide film are dry-etched using themask pattern 16. In this manner,control gate electrodes 14 are formed out of the first polysilicon film and controlgate insulating films 13 are formed out of the first silicon dioxide film. - Next, as shown in FIGS. 4A, 4B and4C, after the
mask pattern 16 has been removed, an HTO (high temperature oxide) film and a silicon nitride film are deposited by a CVD process to about 5 nm and about 10 nm, respectively, over thesemiconductor substrate 11 as well as over thecontrol gate electrodes 14 and thesilicon nitride films 15. In this manner,capacitance insulating films 17 are formed. Then, a BPSG film made of a silicon dioxide containing boron and phosphorus is deposited over thesemiconductor substrate 11. Subsequently, the BPSG film is dry-etched, thereby formingsidewall insulating films 18 out of the BPSG film on the side faces of thecontrol gate electrodes 14. - Next, as shown in FIGS. 5A, 5B and5C, a
mask pattern 19, which exposes the drain forming regions of theactive regions 11 a in the gate width direction of thecontrol gate electrodes 14, is defined over thesubstrate 11 by a photolithographic process for the purpose of forming the step regions. Then, thesemiconductor substrate 11 is dry-etched isotropically using themask pattern 19, thesilicon nitride films 15 and thesidewall insulating films 18 as a mask, thereby formingstep regions 11 b to a depth of about 40 nm in the drain forming regions of thesemiconductor substrate 11. - Next, as shown in FIGS. 6A, 6B and6C, after the
mask pattern 19 has been removed, an etching process using vapor phase hydrogen fluoride is carried out to remove thesidewall insulating films 18. Subsequently, thestep regions 11 b have their surface thermally oxidized, thereby formingtunnel insulating films 20 of silicon dioxide. Thereafter, asecond polysilicon film 21A is deposited by a CVD process to a thickness of about 100 nm over thesemiconductor substrate 11 as well as over thecontrol gate electrodes 14 and thesilicon nitride films 15. Then, amask pattern 22, which exposes the drain forming regions of theactive regions 11 a and theSTIs 12 in the gate width direction of thecontrol gate electrodes 14, is defined by a photolithographic process on thesecond polysilicon film 21A. Thereafter, thesecond polysilicon film 21A is dry-etched anisotropically using themask pattern 22 and thesilicon nitride films 15 as a mask, thereby forming sidewall-shapedpolysilicon films 21B overlapping thestep regions 11 b out of thesecond polysilicon film 21A. - Next, as shown in FIGS. 7A, 7B and7C, after the
mask pattern 22 has been removed, amask pattern 23, which exposes the STIs 12 (i.e., masks theactive regions 11 a), is defined by a photolithographic process over thesemiconductor substrate 11. Subsequently, thesecond polysilicon film 21A and the sidewall-shapedpolysilicon films 21B are dry-etched anisotropically using themask pattern 23. In this manner, island-shaped floatinggate electrodes 21C, overlapping thestep regions 11 b, are formed out of the sidewall-shapedpolysilicon films 21B in the drain forming regions of theactive regions 11 a. Each of the floatinggate electrodes 21C has its ends in the gate width direction positioned on associated ones of theSTIs 12. That is to say, multiple floatinggate electrodes 21C are formed for each control gate electrode. - Next, as shown in FIGS. 8A, 8B and8C, after the
mask pattern 23 has been removed, amask pattern 24, which exposes the source forming regions of theactive regions 11 a and theSTIs 12 in the gate width direction of thecontrol gate electrodes 14, is defined by a photolithographic process. Then, an isotropic dry etching process is carried out using themask pattern 24 and thesilicon nitride films 15 as a mask to remove the remaining parts of thesecond polysilicon film 21A located over the source forming regions. - The process step of removing those parts of the
second polysilicon film 21A and the sidewall-shapedpolysilicon films 21B from over theSTIs 12 as shown in FIGS. 7A, 7B and 7C and the process step of removing the remaining parts of thesecond polysilicon film 21A from over the source forming regions as shown in FIGS. 8A, 8B and 8C may be carried out in reverse order. - Next, as shown in FIGS. 9A, 9B and9C, after the
mask pattern 24 has been removed, arsenic (As) ions are implanted into thesemiconductor substrate 11 at a dose of 6×1015/cm2 and with an acceleration voltage of 40 keV applied using thesilicon nitride films 15 and the floatinggate electrodes 21C as a mask. In this manner,drain regions 25 are defined in the drain forming regions andsource regions 26 are defined in the source forming regions. - Thereafter, other fabrication process steps such as metalization, passivation film forming and bonding pad forming process steps are carried out.
- In this embodiment, the
STIs 12 for isolating adjacent ones of the memory cells from each other in the gate width direction of thecontrol gate electrodes 14 are formed in a striped pattern on thesemiconductor substrate 11. That is to say, theSTIs 12 are spaced apart from each other in the gate width direction. Also, each of theSTIs 12 crosses all of thecontrol gate electrodes 14 and extends continuously in the length direction of the gate electrodes. Thus, as shown in FIG. 7C, when those parts of thesecond polysilicon film 21A and the sidewall-shapedpolysilicon films 21B are etched away from over theSTIs 12, the exposedtunnel insulating film 20 should not break and thesemiconductor substrate 11 should no longer be etched unintentionally. Therefore, no doped region should be disconnected. - Furthermore, the
second polysilicon film 21A for forming the floatinggate electrodes 21C is not patterned at a time in a single process step. Specifically, parts of thesecond polysilicon film 21A and the sidewall-shapedpolysilicon films 21B are removed from over theSTIs 12 in the process step shown in FIGS. 7A, 7B and 7C. Subsequently, the remaining parts of thesecond polysilicon film 21A are removed from over the source forming regions in the process step shown in FIGS. 8A, 8B and 8C. Accordingly, when those parts of thesecond polysilicon film 21A and the sidewall-shapedpolysilicon films 21B are etched away from over theSTIs 12, theactive regions 11 a and members located over theregions 11 a can be masked continuously in the gate length direction. Thus, themask pattern 23 does not have to be an isolated one. Therefore, there is no need to worry about the rounding of the corners of themask pattern 23. Then, a margin that should be allowed for the mask pattern can be reduced. As a result, each of theSTIs 12 can have its size reduced in the gate width direction of thecontrol gate electrodes 14, and therefore the area of each cell can be reduced. - Accordingly, in the semiconductor memory device and its fabrication process according to this embodiment, the size accuracy of the mask pattern can be improved, and thus the total cell area can be reduced. Therefore, a semiconductor memory device, including floating and control gate electrodes that are formed side by side on a semiconductor substrate, can have its size reduced and its performance enhanced greatly.
Claims (7)
1. A semiconductor memory device comprising:
a plurality of isolations formed on a semiconductor substrate;
a plurality of active regions defined on the semiconductor substrate and isolated from each other by the isolations;
a plurality of control gate electrodes formed over the semiconductor substrate, each said control gate electrode crossing all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate; and
a plurality of floating gate electrodes, each of which is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes,
wherein the isolations are spaced apart from each other along the width of the control gate electrodes and
wherein each said isolation crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes.
2. The device of claim 1 , further comprising a third insulating film formed on each of the control gate electrodes.
3. The device of claim 1 , wherein each of the active regions has a plurality of step regions, each of which is overlapped by associated one of the floating gate electrodes and,
wherein in each said active region, source regions are defined in respective upper parts of the step regions and a drain region is defined below the step region.
4. A method for fabricating a semiconductor memory device, comprising the steps of:
a) forming a plurality of isolations on a semiconductor substrate, thereby defining a plurality of active regions, which have been isolated from each other by the isolations, on the semiconductor substrate;
b) forming a first insulating film and a first conductive film in this order over the semiconductor substrate and then selectively etching the first conductive film, thereby forming a control gate electrode out of the first conductive film so that the control gate electrode crosses all of the isolations and all of the active regions;
c) forming a second insulating film and a second conductive film in this order over the semiconductor substrate as well as over the isolations and the control gate electrode and then selectively etching parts of the second conductive film, thereby forming floating gate electrodes out of the second conductive film for the active regions so that the floating gate electrodes cover a side face of the control gate electrode; and
d) implanting ions into the semiconductor substrate using the control gate electrode and the floating gate electrodes as a mask, thereby defining source and drain regions in each said active region,
wherein the step c) includes:
forming and selectively etching the second conductive film to form a sidewall-shaped conductive film out of the second conductive film on the side face of the control gate electrode;
removing parts of the sidewall-shaped conductive film and parts of the second conductive film from over the isolations; and
removing remaining parts of the second conductive film from upper and another side faces of the control gate electrode, thereby forming the floating gate electrodes as islands out of the sidewall-shaped conductive film on the side of the control gate electrode.
5. The method of claim 4 , wherein the step a) comprises forming the isolations in a striped pattern on the semiconductor substrate so that the isolations are spaced apart from each other along the width of the control gate electrode.
6. The method of claim 4 , wherein the step b) comprises forming a third insulating film on the first conductive film and then etching the third insulating film and the first conductive film.
7. The method of claim 4 , wherein the step c) comprises:
forming a sidewall insulating film on side faces of the control gate electrode with the second insulating film interposed between the sidewall insulating film and the control gate electrode; and
etching parts of the semiconductor substrate, which parts are located below the side face of the control gate electrode, using the sidewall insulating film as a mask, thereby forming a plurality of step regions for the active regions.
Priority Applications (1)
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US10/648,515 US20040036110A1 (en) | 2000-09-29 | 2003-08-27 | Semiconductor memory device and method for fabricating the same |
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JP2000298306A JP2002110823A (en) | 2000-09-29 | 2000-09-29 | Semiconductor storage device and its manufacturing method |
JP2000-298306 | 2000-09-29 | ||
US09/964,521 US6677203B2 (en) | 2000-09-29 | 2001-09-28 | Method of manufacturing a semiconductor memory device which reduces the minimum area requirements of the device |
US10/648,515 US20040036110A1 (en) | 2000-09-29 | 2003-08-27 | Semiconductor memory device and method for fabricating the same |
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US09/964,521 Division US6677203B2 (en) | 2000-09-29 | 2001-09-28 | Method of manufacturing a semiconductor memory device which reduces the minimum area requirements of the device |
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US09/964,521 Expired - Fee Related US6677203B2 (en) | 2000-09-29 | 2001-09-28 | Method of manufacturing a semiconductor memory device which reduces the minimum area requirements of the device |
US10/648,515 Abandoned US20040036110A1 (en) | 2000-09-29 | 2003-08-27 | Semiconductor memory device and method for fabricating the same |
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EP (1) | EP1193763A2 (en) |
JP (1) | JP2002110823A (en) |
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KR100603694B1 (en) * | 2005-04-26 | 2006-07-20 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
US7931160B2 (en) | 2006-09-06 | 2011-04-26 | 3M Innovative Properties Company | Vertically mounted shelf assembly and accessories therefor |
JP2010267732A (en) * | 2009-05-13 | 2010-11-25 | Panasonic Corp | Method for manufacturing nonvolatile semiconductor memory device |
KR101583948B1 (en) | 2014-06-24 | 2016-01-08 | 현대자동차주식회사 | Lithium-sulfur battery cathode |
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- 2000-09-29 JP JP2000298306A patent/JP2002110823A/en active Pending
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- 2001-09-27 TW TW090123904A patent/TW504847B/en not_active IP Right Cessation
- 2001-09-28 EP EP01123471A patent/EP1193763A2/en not_active Withdrawn
- 2001-09-28 US US09/964,521 patent/US6677203B2/en not_active Expired - Fee Related
- 2001-09-28 KR KR1020010060295A patent/KR20020025782A/en not_active Application Discontinuation
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2003
- 2003-08-27 US US10/648,515 patent/US20040036110A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
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TW504847B (en) | 2002-10-01 |
US20020039823A1 (en) | 2002-04-04 |
EP1193763A2 (en) | 2002-04-03 |
KR20020025782A (en) | 2002-04-04 |
US6677203B2 (en) | 2004-01-13 |
JP2002110823A (en) | 2002-04-12 |
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