JP3876069B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an extremely thin gate insulating film and a manufacturing method thereof, and is particularly suitable for application to a semiconductor device in which an extremely thin tunnel oxide film is formed on a part of a gate oxide film.
[0002]
[Prior art]
In recent years, further miniaturization and high integration of semiconductor devices have progressed, and accordingly, gate oxide films of transistors tend to be thinned. In particular, in a nonvolatile semiconductor memory, for example, a FLOTOX type EEPROM, in which stored data is retained even when the connection with the power source is cut off and electrically erasable, a recess is formed in a portion of the gate oxide film located above the drain A very thin tunnel oxide film having a thickness of about 100 mm is formed.
[0003]
When manufacturing a FLOTOX type EEPROM, first, after forming a gate oxide film, a part of the tunnel oxide film is removed by wet etching to form a tunnel oxide film. Here, as described above, in order to form a tunnel oxide film in a portion of the gate oxide film located above the drain, a resist pattern having a predetermined shape is formed on the gate oxide film before forming a floating gate or the like. Then, using this resist pattern as a mask, ions are implanted into the surface region of the semiconductor substrate on both sides of the resist pattern through the gate oxide film to form the source / drain. Subsequently, the portion located on the drain of the gate oxide film is removed, and the exposed surface of the semiconductor substrate is thermally oxidized to form a tunnel oxide film. Thereafter, a floating gate, a dielectric film, a control gate, and the like are patterned, an interlayer insulating film and various wirings are formed, and the EEPROM is completed.
[0004]
[Problems to be solved by the invention]
As described above, when a FLOTOX type EEPROM is manufactured, it is necessary to form a resist pattern on the gate oxide film and implant ions before forming the floating gate, the control gate, and the like. This increases the manufacturing process and increases the manufacturing cost. Further, in the case of the above-described manufacturing method, there is a concern that the quality of the tunnel oxide film is deteriorated due to the influence of high concentration impurities in the semiconductor substrate.
[0005]
In Japanese Patent Publication No. 7-36441, P ^- A technique is disclosed in which it is not necessary to form only the base region, the process is simplified, and the elements are reduced. In this method, an oxide film having a stepped portion on the upper surface is formed on a semiconductor substrate, and a polycrystalline silicon film on the oxide film is formed and patterned. Then, ion implantation is performed with ultrahigh energy through the oxide film, and P is applied to the semiconductor substrate under the oxide film. ^- A base region is formed. Subsequently, ions are implanted into the semiconductor substrate between the oxide film and the polycrystalline silicon film to form a source region. However, in this method, since ion implantation is performed with ultrahigh energy, there is a concern that some damage may be caused when the oxide film is an extremely thin oxide film such as a tunnel oxide film.
[0006]
Accordingly, an object of the present invention is to provide a highly reliable semiconductor device having an extremely thin gate insulating film, such as a tunnel oxide film, which is formed without increasing the number of manufacturing steps, and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a source and a drain, a floating gate patterned through an insulating film on a channel region of a semiconductor substrate formed between the source and the drain, and a dielectric on the floating gate. In a semiconductor device including a control gate formed through a body film, the floating gate includes first and second wiring patterns, and the first wiring pattern has the second wiring pattern on an upper surface. The second wiring pattern is formed with a pattern width smaller than the first wiring pattern width, and is formed on a surface region of the semiconductor substrate located on both sides of the convex portion. The source and the drain are formed, and a portion of the insulating film located above the drain is removed and exposed to a surface of the semiconductor substrate, which is compared with a thickness of the insulating film. A thin tunnel insulating film is formed, the floating gate has the convex portion at a position located above the tunnel insulating film, and low concentration impurities are introduced into the source and the drain, respectively. A sidewall conductive film is formed on the dielectric film so as to cover a side surface of the convex portion via the dielectric film, and the sidewall conductive film is formed on the control gate. And a second impurity layer is formed by introducing a high-concentration impurity into a surface region of the semiconductor substrate located on both sides of the sidewall conductive film, and the first impurity layer and the first impurity layer are formed. The two impurity layers are joined.
The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation structure on a semiconductor substrate to define an element active region, a step of forming an insulating film on the element active region, Forming a tunnel insulating film by thermally oxidizing the exposed surface of the semiconductor substrate, and forming a first conductive film on the entire surface of the insulating film and the tunnel insulating film including the element isolation structure And flattening the surface of the first conductive film, forming a strip-shaped mask on the flattened first conductive film, and forming the surface of the element isolation structure on the first conductive film. Patterning until exposed, processing the first conductive film into a shape having a convex portion following the mask on the upper surface, and dividing the first conductive film into each element active region; and the semiconductor Impurities of low concentration through the first conductive film on the substrate So that a low-concentration first impurity layer is formed on the surface region of the semiconductor substrate located on both sides of the convex portion, and the tunnel insulating film is located on one of the first impurity layers. Forming a dielectric film on the entire surface of the first conductive film including the element isolation structure; forming a second conductive film on the second insulating film; and The entire surface of the second conductive film is anisotropically etched until the surface of the insulating film is exposed, and the second conductive film is left on the side surface of the convex portion through the dielectric film to form a sidewall conductive film. A high concentration impurity is introduced into the semiconductor substrate through the dielectric film and the floating gate, and a high concentration first region is formed at a portion located on both sides of the sidewall conductive film in the surface region of the semiconductor substrate. 2 impurity layers are formed, and the first impurity layer and the second impurity layer are formed. Bonding a layer, forming a third conductive film on the dielectric film and the sidewall conductive film, the third conductive film, the dielectric film, and the first conductive film. Patterning is performed to form a floating gate leaving the first conductive film in an island shape corresponding to each element active region, and a third so as to extend on the floating gate via the dielectric film. And forming a control gate leaving the conductive film.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
(First embodiment)
First, the first embodiment will be described. In the first embodiment, the semiconductor device is a non-volatile semiconductor memory that retains stored data even when the connection with the power source is cut off and is electrically erasable, and is above the drain of the gate oxide film. An example of a FLOTOX type EEPROM in which an extremely thin tunnel oxide film is formed at a position located in the region will be described. In the first embodiment, the main configuration of the EEPROM memory cell will be described together with its manufacturing method. FIG. 1 is a schematic plan view showing the main configuration of the EEPROM memory cell of the first embodiment, FIGS. 2 to 4 are schematic cross-sectional views showing the manufacturing method of the EEPROM in the order of steps, and FIGS. 4 corresponds to the cross section along the alternate long and short dash line II ′, and FIG. 4 corresponds to the cross section along the alternate long and short dash line II-II ′ in FIG.
[0026]
First, as shown in FIG. 2A, a field shield element isolation structure 2 is formed on a p-type silicon semiconductor substrate 1.
[0027]
Specifically, the field gate oxide film 21 is formed by performing thermal oxidation on the surface of the silicon semiconductor substrate 1, and then the polycrystalline silicon film 22 and the silicon oxide film 23 are sequentially formed on the field gate oxide film 21. Subsequently, the field gate oxide film 21, the polycrystalline silicon film 22, and the silicon oxide film 23 are selectively removed by patterning by photolithography and subsequent dry etching or the like.
[0028]
Then, after a silicon oxide film 24 is formed on the entire surface so as to cover the remaining field gate oxide film 21, polycrystalline silicon film 22 and silicon oxide film 23, the entire surface of the silicon oxide film 23 is anisotropically dried by RIE or the like. The silicon oxide film 24 is left only on the side surfaces of the field gate oxide film 21, the polycrystalline silicon film 22, and the silicon oxide film 23 by etching. Thereby, the field shield element isolation structure 2 including the shield plate electrode made of the polycrystalline silicon film surrounded by the silicon oxide film is formed.
[0029]
As an element isolation structure, a field oxide film may be formed by a so-called LOCOS method instead of the field shield element isolation structure 2.
[0030]
Subsequently, the surface of the defined element active region 3 is thermally oxidized to form a gate oxide film 4 having a thickness of about 200 mm.
[0031]
Next, as shown in FIG. 2B, a part of the gate oxide film 3 is removed by wet etching, and a part of the surface of the silicon semiconductor substrate 1 is exposed. Subsequently, the exposed surface of the silicon semiconductor substrate 1 is again thermally oxidized to form a tunnel oxide film 5 having a thickness of about 110 mm.
[0032]
Next, as shown in FIG. 2C, a polycrystalline silicon film 31 is deposited to a thickness of about 3000 mm on the entire surface including the field shield element isolation structure 2 by low pressure CVD.
[0033]
Next, as shown in FIG. 2D, the surface of the polycrystalline silicon film 31 is polished, here by a chemical mechanical polishing (CMP) method, so that the surface of the polycrystalline silicon film 31 is planarized. At this time, the thickness of the polycrystalline silicon film 31 is thinner on the field shield element isolation structure 2 by the thickness of the field shield element isolation structure 2 than on the element active region 3.
[0034]
Next, as shown in FIGS. 3A and 4A, a photoresist 32 on the polycrystalline silicon film 31 is applied, the photoresist 32 is processed by photolithography, and the photoresist is formed into a predetermined strip shape. Leave 32. Here, it is necessary to process the photoresist 32 into a pattern in which the tunnel oxide film 5 does not exist immediately below the photoresist 32.
[0035]
Subsequently, using the photoresist 32 as a mask and using the surface of the field shield element active region 2 as a stopper, the polycrystalline silicon film 31 is dry-etched (half-etched) until the surface of the field shield element isolation structure 2 is exposed. At this time, the polycrystalline silicon film 31 is divided on the field shield element isolation structure 2 surrounding the element active region 3 so as to embed the element active region 3, and as shown in FIG. Further, it is formed in a shape having a belt-like convex portion 11 following the photoresist 32. Here, the portion of the polycrystalline silicon film 31 where the convex portion 11 is not formed (hereinafter referred to as a thin portion) has a thickness of about 1000 to 1500 １ depending on the thickness of the field shield element isolation structure 2. An example of using half etching when forming the gate electrode of a MOS transistor is disclosed in Japanese Patent Laid-Open No. 61-145868.
[0036]
Next, as shown in FIG. 3B, after the photoresist 32 is removed by ashing or the like, the thin portion of the polycrystalline silicon film 31 and the convex portion 11 and the field shield element isolation structure 2 are used as a mask. Ions are implanted into the surface region of the silicon semiconductor substrate 1 through the gate oxide film 4 (tunnel oxide film 5). Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions.
[0037]
Subsequently, the silicon semiconductor substrate 1 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the implanted ions, thereby forming a source 6 and a drain 7 as a pair of impurity diffusion layers. .
[0038]
Next, as shown in FIGS. 3C and 4B, a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed on the entire surface of the polycrystalline silicon film 31 including the field shield element isolation structure 2 by a low pressure CVD method. A silicon oxide film is sequentially deposited to a film thickness of about 100 mm, about 150 mm, and about 100 mm to form an ONO film 8 having a three-layer structure.
[0039]
Subsequently, a polycrystalline silicon film 33 having a thickness of about 1500 mm is deposited on the ONO film 8 by low pressure CVD.
[0040]
Next, as shown in FIG. 3D, the polycrystalline silicon film 33, the ONO film 8, and the polycrystalline silicon film 31 are simultaneously patterned by photolithography and subsequent dry etching. More specifically, the tunnel oxide film 5 is covered on each element active region 3, and the polycrystalline silicon film 31 is left so as to be independent on each element active region 3. The polycrystalline silicon film 33 is left in parallel strips. At this time, an island-like floating gate 9 made of a polycrystalline silicon film 31 is formed on each element active region 3, and a multi-layer extending across the field shield element isolation structure 2 via the ONO film 8 on the floating gate 9. A control gate 10 made of the crystalline silicon film 33 is formed.
[0041]
In the above Japanese Patent Laid-Open No. 61-145868, after half etching, nitrogen is ion-implanted into the polycrystalline silicon film using a resist as a mask, source / drains are formed, and the semiconductor substrate is annealed. This insulates the portion of the polycrystalline silicon film into which nitrogen ions are implanted. This technique requires a high-temperature annealing process and is difficult to apply to an EEPROM. There is also a problem of increasing the number of processes.
[0042]
Thereafter, an interlayer insulating film covering the control gate 10 and a bit line etc. (both not shown) connected to the drain 7 and intersecting the control gate 10 are formed to complete an EEPROM memory cell. Although description is omitted, the selection transistor of the memory cell is formed as appropriate together with the above-described steps.
[0043]
As described above, in the first embodiment, after forming the tunnel oxide film 5, not only the gate oxide film 4 (tunnel oxide film 5) but also the thin portion of the polycrystalline silicon film 31 is allowed to pass through the source 6 And the drain 7 are formed. Therefore, the photo process is reduced as compared with the case where the source / drain is formed before the tunnel oxide film 5 is formed as in the prior art, and the manufacturing process can be shortened and the manufacturing cost can be reduced. This makes it difficult to be affected by high-concentration impurities, thereby realizing a highly reliable EEPROM.
[0044]
(Modification)
Hereinafter, some modified examples of the first embodiment will be described. In addition, about the member etc. corresponding to EEPROM of 1st Embodiment, the same code | symbol is described and description is abbreviate | omitted.
[0045]
-Modification 1-
First, Modification 1 will be described. The EEPROM according to the first modification has substantially the same configuration as the EEPROM according to the first embodiment and is manufactured through substantially the same process. However, the impurity diffusion layer mainly has an LDD structure. Is different. In the first modification, as in the first embodiment, the main configuration of the EEPROM memory cell will be described together with its manufacturing method. FIG. 5 is a schematic cross-sectional view showing the main steps of the method for manufacturing an EEPROM according to the first modification, and corresponds to the cross section taken along the alternate long and short dash line II ′ of FIG. 1, that is, FIGS.
[0046]
First, similarly to the first embodiment, the respective steps shown in FIGS. 2 (a) to 2 (d) and FIG. 3 (a) are used to have a convex portion 11 on the surface, and each is a field shield element isolation. A polycrystalline silicon film 31 separated by the structure 2 is formed.
[0047]
Next, as shown in FIG. 5A, the convex portion 11 and the field shield element isolation structure 2 are used as a mask through the thin portion of the polycrystalline silicon film 31 and the gate oxide film 4 (tunnel oxide film 5). Ions are implanted into the surface region of the silicon semiconductor substrate 1. Specifically, the acceleration energy is 120 keV and the dose amount is 5 × 10. ¹³ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions. At this time, impurities are introduced at a lower concentration than in the case of the first embodiment.
[0048]
Next, as shown in FIG. 5B, after removing the photoresist 32 by ashing or the like, a polycrystalline silicon film is formed on the entire surface including the exposed field shield element isolation structure 2 by low pressure CVD. Then, the entire surface of the polycrystalline silicon film is anisotropically etched again using the field shield element isolation structure 2 as a stopper. At this time, a sidewall 41 made of a polycrystalline silicon film covering only the side surface of the convex portion 11 on the polycrystalline silicon film 31 is formed.
[0049]
Next, as shown in FIG. 5C, the thin portion of the polycrystalline silicon film 31 and the gate oxide film 4 (tunnel oxide film 5) using the convex portion 11, the sidewall 41 and the field shield element isolation structure 2 as a mask. ) To the surface region of the silicon semiconductor substrate 1 again. Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions. At this time, impurities are introduced at a higher concentration than in the first ion implantation, and a high concentration impurity region is formed leaving the surface region of the silicon semiconductor substrate 1 in the vicinity immediately below the sidewall 41.
[0050]
Next, as shown in FIG. 5D, the silicon semiconductor substrate 1 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the ion-implanted impurities, and immediately below the sidewalls 41. N nearby ^- Type low concentration diffusion layer 42 and n bonded to the low concentration diffusion layer 42 ⁺ A high-concentration diffusion layer 43 of the mold is formed, and a source 44 and a drain 45 having an LDD structure made of both of them are formed.
[0051]
Then, similarly to the first embodiment, the ONO film 8 and the polycrystalline silicon film 33 are sequentially deposited, and the polycrystalline silicon film 33, the ONO film 8 and the polycrystalline silicon film 31 are patterned at the same time, so that FIG. As shown in (d), the island-like floating gate 9 made of the polycrystalline silicon film 31 and the polycrystalline extending over the field shield element isolation structure 2 via the ONO film 8 on the floating gate 9. A control gate 10 made of the silicon film 33 is formed.
[0052]
Thereafter, as in the first embodiment, an interlayer insulating film covering the control gate 10 and a bit line (not shown) that is connected to the drain 45 and intersects the control gate 10 are formed, and the EEPROM is formed. The memory cell is completed. Although description is omitted, the selection transistor of this memory cell is also formed as appropriate together with the above-described steps.
[0053]
As described above, in the first modification of the first embodiment, not only the gate oxide film 4 (tunnel oxide film 5) but also many after the tunnel oxide film 5 is formed, as in the case of the first embodiment. A source 44 and a drain 45 are formed by allowing impurities to pass through a thin portion of the crystalline silicon film 31. Therefore, the photo process is reduced as compared with the case where the source / drain is formed before the tunnel oxide film 5 is formed as in the prior art, and the manufacturing process can be shortened and the manufacturing cost can be reduced. This makes it difficult to be affected by high-concentration impurities, thereby realizing a highly reliable EEPROM.
[0054]
Furthermore, in the first modification, since the source 44 and the drain 45 have an LDD structure, in addition to the above effects, generation of hot carriers can be suppressed and the breakdown voltage can be greatly improved. .
[0055]
-Modification 2-
Next, Modification 2 of the first embodiment will be described. In the EEPROM of the second modification, the impurity diffusion layer has an LDD structure as in the first modification, but there are some differences in the process. FIG. 6 is a schematic cross-sectional view showing the main steps of the method for manufacturing an EEPROM according to the modified example 2, and corresponds to the cross section taken along the alternate long and short dash line II ′ of FIG. 1, that is, FIGS.
[0056]
First, similarly to the first embodiment, the respective steps shown in FIGS. 2 (a) to 2 (d) and FIG. 3 (a) are used to have a convex portion 11 on the surface, and each is a field shield element isolation. A polycrystalline silicon film 31 separated by the structure 2 is formed.
[0057]
Next, as shown in FIG. 6A, after the photoresist 32 is removed by ashing or the like, the thin portion of the polycrystalline silicon film 31 and the convex portion 11 and the field shield element isolation structure 2 are used as a mask. Ions are implanted into the surface region of the silicon semiconductor substrate 1 through the gate oxide film 4 (tunnel oxide film 5). Specifically, the acceleration energy is 120 keV and the dose amount is 5 × 10. ¹³ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions. At this time, impurities are introduced at a lower concentration than in the case of the first embodiment.
[0058]
Next, as shown in FIG. 6B, a silicon oxide film, a silicon nitride film, and a silicon oxide film are respectively formed on the entire surface of the polycrystalline silicon film 31 including the field shield element isolation structure 2 by low pressure CVD. The ONO film 8 having a three-layer structure is formed by sequentially depositing and forming a thickness of about 100 mm, about 150 mm, and about 100 mm.
[0059]
Next, as shown in FIG. 6C, a polycrystalline silicon film is formed on the entire surface of the ONO film 8 by low-pressure CVD, and the entire surface of the polycrystalline silicon film is changed using the surface of the ONO film 8 as a stopper. Isotropic etching. At this time, a sidewall 51 made of a polycrystalline silicon film covering only the side surface of the convex portion 11 is formed via the ONO film 8.
[0060]
Next, as shown in FIG. 6D, the ONO film 8, the thin portion of the polycrystalline silicon film 31, and the gate oxide film 4 (with the convex portion 11, the sidewall 51, and the field shield element isolation structure 2 as a mask) Ion implantation is again performed on the surface region of the silicon semiconductor substrate 1 through the tunnel oxide film 5). Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions. At this time, impurities are introduced at a higher concentration than in the first ion implantation, and a high concentration impurity region is formed leaving the surface region of the silicon semiconductor substrate 1 in the vicinity immediately below the sidewall 51.
[0061]
Subsequently, the silicon semiconductor substrate 1 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the ion-implanted impurities, and n near the sidewall 51 is activated. ^- Type low concentration diffusion layer 52 and n bonded to this low concentration diffusion layer 52 ⁺ A high-concentration diffusion layer 53 of the mold is formed, and a source 54 and a drain 55 having an LDD structure made of both of them are formed.
[0062]
Then, as in the first embodiment, the polycrystalline silicon film 33 is sequentially deposited so as to cover the ONO film 8 and the sidewalls 51. At this time, the sidewall 51 and the polycrystalline silicon film 33 are integrated. Subsequently, by simultaneously patterning the polycrystalline silicon film 33, the ONO film 8, and the polycrystalline silicon film 31, as shown in FIG. 6E, an island-shaped floating gate 9 made of the polycrystalline silicon film 31, On the floating gate 9, the control gate 10 made of the polycrystalline silicon film 33 is formed with the ONO film 8 interposed and extending across the field shield element isolation structure 2.
[0063]
As described above, in the second modification of the first embodiment, as in the case of the first embodiment, not only the gate oxide film 4 (tunnel oxide film 5) but also the many after the tunnel oxide film 5 is formed. A source 54 and a drain 55 are formed by allowing impurities to pass through a thin portion of the crystalline silicon film 31. Therefore, the photo process is reduced as compared with the case where the source / drain is formed before the tunnel oxide film 5 is formed as in the prior art, and the manufacturing process can be shortened and the manufacturing cost can be reduced. This makes it difficult to be affected by high-concentration impurities, thereby realizing a highly reliable EEPROM.
[0064]
Furthermore, in the second modification, since the source 54 and the drain 55 have an LDD structure, in addition to the above-described effects, generation of hot carriers can be suppressed and the breakdown voltage can be greatly improved. .
[0065]
-Modification 3-
Next, Modification 3 of the first embodiment will be described. The EEPROM of Modification 3 has substantially the same configuration as that of the EEPROM of the first embodiment and is manufactured through substantially the same process, but further suppresses adverse effects on the tunnel oxide film 5 due to high-concentration impurities. In consideration, mainly, the photoresist 32 on the polycrystalline silicon film 31 in FIGS. 3A and 4A is processed so as to leave a region covering the tunnel oxide film 5 in addition to a predetermined band-like one. It is different in point. FIG. 7 is a schematic plan view showing the main configuration of the EEPROM memory cell of the third modification, FIGS. 8 to 9 are schematic cross-sectional views showing the manufacturing method of the EEPROM in the order of steps, and FIG. 8 is an alternate long and short dash line I in FIG. 9 corresponds to a cross section taken along the line −I ′, and FIG. 9 corresponds to a cross section taken along the alternate long and short dash line II-II ′ in FIG. 7.
[0066]
First, as in the case of the first embodiment, the polycrystalline silicon planarized on the field shield element isolation structure 2 and the element active region 3 through the respective steps of FIGS. 2A to 2D. A film 31 is formed.
[0067]
Next, as shown in FIGS. 8A and 9A, a photoresist 32 is applied on the polycrystalline silicon belly 31, the photoresist 32 is processed by photolithography, and the photoresist is formed into a predetermined strip shape. 32 and the photoresist 32 are also left in the region covering the tunnel oxide film 5.
[0068]
Subsequently, using the photoresist 32 as a mask and using the surface of the field shield element isolation structure 2 as a stopper, the polycrystalline silicon film 31 is dry-etched (half-etched) until the surface of the field shield element isolation structure 2 is exposed. At this time, the polycrystalline silicon film 31 is divided on the field shield element isolation structure 2 surrounding the element active region 3 to embed the element active region 3, and as shown in FIG. In addition, it is formed in an island shape covering the strip-shaped convex portion 11 and the tunnel oxide film 5 following the photoresist 32, in this case, having a rectangular convex portion 11 ′. Here, the thin part of the polycrystalline silicon belly 31 has a film thickness of about 1000 to 1500 mm depending on the thickness of the field shield element isolation structure 2.
[0069]
Next, as shown in FIG. 8B, after the photoresist 32 is removed by ashing or the like, the above-described polycrystalline silicon film 31 is formed using the convex portions 11 and 11 ′ and the field shield element isolation structure 2 as a mask. Ions are implanted into the surface region of the silicon semiconductor substrate 1 through the book portion and the gate oxide film 4. Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (/ Cm ² ) An n-type blunt material, here arsenic (As), is ion-implanted under the various conditions. At this time, since the convex portion 11 ′ exists on the tunnel oxide film 5, the tunnel oxide film 5 of the silicon semiconductor substrate 1 is present. Ion implantation is not performed on the lower part. In this case, a slight ion implantation may be performed on the portion below the tunnel oxide film 5. Specifically, a technique such as ion implantation (oblique ion implantation) from a direction inclined by a predetermined angle with respect to the surface of the silicon semiconductor substrate 1 is suitable.
[0070]
Subsequently, as shown in FIGS. 8C and 9B, the silicon semiconductor substrate 1 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the implanted ions. A source 6 and a drain 7 which are a pair of impurity diffusion layers are formed. At this time, a portion corresponding to the lower portion of the tunnel oxide film 5 of the drain 7 becomes a non-formation region 7a where no impurity diffusion layer is formed.
[0071]
Thereafter, similarly to the first embodiment, the EEPROM is completed through the process of FIG. 8D corresponding to FIG.
[0072]
As described above, in Modification 3 of the first embodiment, in addition to the various effects of the first embodiment, the source 6 is formed by allowing impurities to pass through the thin portion of the polycrystalline silicon film 31 and the gate oxide film 4. In forming the drain 7, the tunnel oxide film 5 does not allow high-concentration impurities to pass through, so that further high quality of the tunnel oxide film 5 is ensured and a highly reliable EEPROM can be realized.
[0073]
-Modification 4-
Next, Modification 4 of the first embodiment will be described. The EEPROM of Modification 4 has the same configuration as that of Modification 3 and is manufactured through the same steps, but differs in that the element isolation structure is different. 10 to 12 are schematic cross-sectional views showing the main steps of the manufacturing method of the EEPROM according to the modified example 4. FIGS. 10 and 11 are cross-sectional views taken along the alternate long and short dash line II ′ of FIG. 7 substantially correspond to the cross section taken along the alternate long and short dash line II-II ′.
[0074]
First, as shown in FIG. 10A, after the surface of the p-type silicon semiconductor substrate 1 is thermally oxidized to form a pad oxide film 61 with a thickness of about 300 mm, silicon is deposited on the pad oxide film 61 by a CVD method. The nitride film 62 is deposited to a thick film thickness, for example, about 1000 to 1500 mm.
[0075]
Next, as shown in FIG. 10B, the silicon nitride film 62 and the pad oxide film 61 corresponding to the element isolation region of the silicon semiconductor substrate are removed by photolithography and subsequent dry etching, and then the remaining silicon Using the nitride film 62 as a mask, a groove 63 having a depth of about 4 μm is formed in the silicon semiconductor substrate 1.
[0076]
Next, as shown in FIG. 10C, a silicon oxide film 64 is deposited and formed on the entire surface by the CVD method so as to fill the groove 63, and chemical mechanical polishing (chemical mechanical polishing) is performed on the silicon oxide film 64 using the silicon nitride film 62 as a stopper. CMP) is performed to leave the silicon oxide film 64 in the trench 63.
[0077]
Then, as shown in FIG. 10D, the silicon nitride film 62 and the pad oxide film 61 are removed using a predetermined chemical solution, and the trench type element isolation structure 65 in which the silicon oxide film 64 is filled in the groove 63 is obtained. To complete. At this time, the silicon oxide film 64 has a shape protruding from the surface of the silicon semiconductor substrate 1 by the thickness of the silicon nitride film 62 (and the pad oxide film 61).
[0078]
Subsequently, as in the case of the first embodiment, the tunnel oxide film 5 and the polycrystalline silicon film 31 are formed through the same steps as in FIG. 2B to FIG. The surface of 31 is flattened.
[0079]
Next, as shown in FIGS. 11A and 12A, a photoresist 32 on the polycrystalline silicon film 31 is applied, the photoresist 32 is processed by photolithography, and a predetermined strip-shaped photoresist 32 is formed. And the photoresist 32 is also left in the region covering the tunnel oxide film 5.
[0080]
Subsequently, using the photoresist 32 as a mask and using the surface of the silicon oxide film 64 of the trench type element isolation structure 65 as a stopper, the polycrystalline silicon film 31 is dry-etched (half-etched) until the surface of the silicon oxide film 64 is exposed. ) At this time, the polycrystalline silicon film 31 is divided on the trench type element isolation structure 65 surrounding the element active region 3 so as to embed the element active region 3, and as shown in FIG. In addition, it is formed in an island shape covering the strip-shaped convex portion 11 and the tunnel oxide film 5 following the photoresist 32, in this case, having a rectangular convex portion 11 ′. Here, the thin portion of the polycrystalline silicon belly 31 has a film thickness of about 1000 to 1500 mm depending on the thickness of the silicon oxide film 64 of the trench type element isolation structure 65.
[0081]
Next, as shown in FIG. 11B, after the photoresist 32 is removed by ashing or the like, the above-described polycrystalline silicon film 31 is formed using the protrusions 11 and 11 ′ and the trench-type element isolation structure 65 as a mask. Ions are implanted into the surface region of the silicon semiconductor substrate 1 through the book portion and the gate oxide film 4. Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (/ Cm ² ) An n-type blunt material, here arsenic (As), is ion-implanted under various conditions. At this time, since the protrusion 11 ′ exists on the tunnel oxide film 5, the tunnel oxide film 5 of the silicon semiconductor substrate 1 is present. Ion implantation is not performed on the lower part.
[0082]
Subsequently, as shown in FIGS. 11C and 12B, the silicon semiconductor substrate 1 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the implanted ions. A source 6 and a drain 7 which are a pair of impurity diffusion layers are formed. At this time, a portion corresponding to the lower portion of the tunnel oxide film 5 of the drain 7 becomes a non-formation region 7a where no impurity diffusion layer is formed.
[0083]
Thereafter, similarly to the first embodiment, the EEPROM is completed through the process of FIG. 11D corresponding to FIG.
[0084]
As described above, in the fourth modification of the first embodiment, in addition to the various effects of the first embodiment, a source of non-conformity is passed through the thin portion of the polycrystalline silicon film 31 and the gate oxide film 4. In forming the drain 6 and the drain 7, since the high-concentration impurities are not allowed to pass through the tunnel oxide film 5, further high quality of the tunnel oxide film 5 is ensured, and a highly reliable EEPROM can be realized.
[0085]
Furthermore, since the trench type element isolation structure 65 is formed as the element isolation structure, it is possible to sufficiently cope with further miniaturization of the EEPROM.
[0086]
The trench type element isolation structure 65 exemplified in the modification 4 can be applied to the first embodiment, the second embodiment described later, and all of these modifications. As the element isolation structure, a field oxide film formed by, for example, a LOCOS method may be applied other than the field shield element isolation structure and the trench type element isolation structure.
[0087]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the second embodiment, a MOS transistor having a thin gate oxide film is illustrated as a semiconductor device. In the second embodiment, the main structure of the MOS transistor will be described together with its manufacturing method. FIG. 13 is a schematic plan view showing the main configuration of the MOS transistor of the second embodiment, FIGS. 14 to 16 are schematic cross-sectional views showing the manufacturing method of the MOS transistor in the order of steps, and FIGS. FIG. 16 corresponds to the cross section taken along the alternate long and short dash line II-II ′ in FIG. 13.
[0088]
First, as shown in FIG. 14A, a field shield element isolation structure 102 is formed on a p-type silicon semiconductor substrate 101.
[0089]
Specifically, the surface of the silicon semiconductor substrate 101 is thermally oxidized to form a field gate oxide film 121, and then a polycrystalline silicon film 122 and a silicon oxide film 123 are sequentially formed on the field gate oxide film 121. Subsequently, the field gate oxide film 121, the polycrystalline silicon film 122, and the silicon oxide film 123 are patterned and removed selectively by photolithography and subsequent dry etching to define the element active region 103.
[0090]
A silicon oxide film 124 is formed on the entire surface so as to cover the remaining field gate oxide film 121, polycrystalline silicon film 122, and silicon oxide film 123, and then the entire surface of the silicon oxide film 123 is anisotropically dried by RIE or the like. The silicon oxide film 124 is left only on the side walls of the field gate oxide film 121, the polycrystalline silicon film 122, and the silicon oxide film 123 by etching. As a result, a field shield element isolation structure 102 having a shield plate electrode made of a polycrystalline silicon film surrounded by a silicon oxide film is formed in the field region.
[0091]
As an element isolation structure, a field oxide film may be formed by a so-called LOCOS method instead of the field shield element isolation structure 102.
[0092]
Subsequently, the surface of the defined device active region 103 is thermally oxidized to form a thin gate oxide film 104 having a thickness of about 110 mm.
[0093]
Next, as shown in FIG. 14B, a polycrystalline silicon film 131 is deposited to a thickness of about 3000 mm on the entire surface including the field shield element isolation structure 102 by low pressure CVD.
[0094]
Next, as shown in FIG. 14C, the surface of the polycrystalline silicon film 131 is polished, here by a chemical mechanical polishing (CMP) method, and the surface of the polycrystalline silicon film 131 is planarized. At this time, the thickness of the polycrystalline silicon film 131 is thinner on the field shield element isolation structure 102 by the thickness of the field shield element isolation structure 102 than on the element active region 103.
[0095]
Next, as shown in FIGS. 15A and 16A, a photoresist 132 on the polycrystalline silicon film 131 is applied, the photoresist 132 is processed by photolithography, and the photoresist is formed into a predetermined strip shape. Leave 132.
[0096]
Subsequently, while using the photoresist 132 as a mask, the polycrystalline silicon film 131 is dry-etched (half-etched) until the film thickness reaches a predetermined thickness on the field shield element isolation structure 102. At this time, as shown in FIG. 15A, the polycrystalline silicon film 131 is formed in a shape having a belt-like convex portion 111 following the photoresist 132 on the surface thereof.
[0097]
Next, as shown in FIG. 15B, after the photoresist 132 is removed by ashing or the like, the thin portion of the polycrystalline silicon film 131 and the convex portion 111 and the field shield element isolation structure 102 are used as a mask. Ions are implanted into the surface region of the silicon semiconductor substrate 101 through the gate oxide film 104. Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions.
[0098]
Subsequently, the silicon semiconductor substrate 101 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the ion-implanted impurities, thereby forming a source 106 and a drain 107 as a pair of impurity diffusion layers. .
[0099]
Next, as shown in FIG. 15C and FIG. 16B, the polycrystalline silicon film 131 is patterned by photolithography and subsequent dry etching to form a polycrystal in a strip shape substantially parallel to the longitudinal direction of the convex portion 111. The silicon film 131 is left. At this time, the gate electrode 108 made of the polycrystalline silicon film 131 extending on the element active region 103 across the field shield element isolation structure 102 is formed.
[0100]
Thereafter, an interlayer insulating film covering the gate electrode 108, various wirings connected to the source 106 and the drain 107 (both not shown) are formed, and the MOS transistor is completed.
[0101]
Thus, in the second embodiment, after forming the gate oxide film 104, the source 106 and the drain 107 are formed by allowing impurities to pass through not only the gate oxide film 104 but also the thin portion of the polycrystalline silicon film 131. Therefore, the thin gate oxide film 104 is hardly affected by high concentration impurities, and a highly reliable MOS transistor is realized.
[0102]
(Modification)
Hereinafter, modifications of the second embodiment will be described. Note that members corresponding to those of the MOS transistor of the second embodiment are denoted by the same reference numerals, and description thereof is omitted. The MOS transistor of this modification has almost the same configuration as the MOS transistor of the second embodiment and is manufactured through substantially the same process, but the impurity diffusion layer mainly has an LDD structure. Is different. Also in this modification, as in the second embodiment, the main configuration of the MOS transistor will be described together with its manufacturing method. FIG. 17 is a schematic cross-sectional view showing the main steps of the MOS transistor manufacturing method according to the modification, corresponding to the cross section taken along the alternate long and short dash line II ′ of FIG. 13 of the second embodiment, that is, FIG. 14 and FIG. is doing.
[0103]
First, similarly to the second embodiment, a polycrystalline silicon film 131 having a convex portion 111 on the surface is formed through the steps of FIGS. 14A to 14C and FIG. 15A.
[0104]
Next, as shown in FIG. 17A, after removing the photoresist 132 by ashing or the like, the thin portion of the polycrystalline silicon film 131 and the convex portion 111 and the field shield element isolation structure 102 are used as a mask. Ions are implanted into the surface region of the silicon semiconductor substrate 101 through the gate oxide film 104. Specifically, the acceleration energy is 120 keV and the dose amount is 5 × 10. ¹³ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions. At this time, impurities are introduced at a lower concentration than in the case of the second embodiment.
[0105]
Next, as shown in FIG. 17B, a polycrystalline silicon film is formed on the entire surface including the exposed field shield element isolation structure 102 by low-pressure CVD, and the field shield element isolation structure 102 is used as a stopper. The entire surface of the crystalline silicon film is anisotropically etched. At this time, a sidewall 141 made of a polycrystalline silicon film is formed on the polycrystalline silicon film 131 so as to cover only the side surface of the convex portion 111.
[0106]
Next, as shown in FIG. 17C, a silicon semiconductor is formed through the thin portion of the polycrystalline silicon film 131 and the gate oxide film 104 using the convex portion 111, the sidewall 141, and the field shield element isolation structure 102 as a mask. Ion implantation is again performed on the surface region of the substrate 101. Specifically, the acceleration energy is 200 keV and the dose amount is 5 × 10. ¹⁵ (1 / cm ² ) N-type impurities, here arsenic (As), are ion-implanted under various conditions. At this time, impurities are introduced at a higher concentration than in the first ion implantation, and a high-concentration impurity region is formed leaving the surface region of the silicon semiconductor substrate 101 in the vicinity immediately below the sidewall 141.
[0107]
Next, as shown in FIG. 17D, the silicon semiconductor substrate 101 is annealed under conditions of a temperature of 900 ° C. and a time of about 30 minutes to activate the ion-implanted impurities, and the sidewall 141 N in the immediate vicinity ^- Type low concentration diffusion layer 142 and n bonded to the low concentration diffusion layer 142 ⁺ A high-concentration diffusion layer 143 of the mold is formed, and a source 144 and a drain 145 having an LDD structure made of both of them are formed.
[0108]
Then, as in the second embodiment, the polycrystalline silicon film 131 is patterned to extend over the element active region 103 across the field shield element isolation structure 102 as shown in FIG. A strip-shaped gate electrode 108 made of the polycrystalline silicon film 131 is formed.
[0109]
Thereafter, as in the second embodiment, an interlayer insulating film covering the gate electrode 108, various wirings connected to the source 106 and the drain 107 (both are not shown), and the MOS transistor is formed. Finalize.
[0110]
As described above, in the modification of the second embodiment, after forming the gate oxide film 104, the impurity is allowed to pass through not only the gate oxide film 104 but also the thin portion of the polycrystalline silicon film 131, and the source 145 and the drain 146. Therefore, the thin gate oxide film 104 is hardly affected by high-concentration impurities, and a highly reliable MOS transistor is realized.
[0111]
Furthermore, in this modified example, since the source 144 and the drain 145 have an LDD structure, in addition to the above effects, generation of hot carriers can be suppressed and the breakdown voltage can be significantly improved.
[0112]
【The invention's effect】
According to the present invention, it is possible to realize a semiconductor device having a very thin gate insulating film, for example, a tunnel oxide film, which has a high quality and high reliability, by omitting the photo process and reducing the number of manufacturing processes.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a main configuration of an EEPROM memory cell according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing the method of manufacturing the EEPROM memory cell according to the first embodiment of the present invention in the order of steps.
3 is a schematic cross-sectional view showing the method of manufacturing the EEPROM memory cell according to the first embodiment of the present invention in the order of steps, following FIG. 2;
FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the EEPROM memory cell according to the first embodiment of the present invention in the order of steps.
FIG. 5 is a schematic cross-sectional view showing the main steps of a method for manufacturing an EEPROM memory cell in order of steps in Modification 1 of the first embodiment of the present invention.
6 is a schematic cross-sectional view showing the main steps of a method for manufacturing an EEPROM memory cell in order of steps in Modification 2 of the first embodiment of the present invention. FIG.
FIG. 7 is a schematic plan view showing a main configuration of an EEPROM memory cell in a third modification of the first embodiment of the present invention.
8 is a schematic cross-sectional view showing the main steps of a method of manufacturing an EEPROM memory cell in order of steps in Modification 3 of the first embodiment of the present invention. FIG.
FIG. 9 is a schematic cross-sectional view showing the main steps of the method of manufacturing the EEPROM memory cell in order of steps in Modification 3 of the first embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view showing the main steps of the method of manufacturing the EEPROM memory cell in order of steps in Modification 4 of the first embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view showing main steps of the method of manufacturing the EEPROM memory cell in the order of steps in the fourth modification of the first embodiment of the present invention following FIG. 10;
12 is a schematic cross-sectional view showing the main steps of a method of manufacturing an EEPROM memory cell in order of steps in Modification 4 of the first embodiment of the present invention. FIG.
FIG. 13 is a schematic plan view showing the main configuration of a MOS transistor according to a second embodiment of the present invention.
FIG. 14 is a schematic cross sectional view showing the method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps.
15 is a schematic cross-sectional view subsequent to FIG. 14, showing a MOS transistor manufacturing method according to the second embodiment of the present invention in the order of steps; FIG.
FIG. 16 is a schematic cross sectional view showing the method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps.
FIG. 17 is a schematic cross-sectional view showing the main steps of a MOS transistor manufacturing method in the order of steps in a modification of the second embodiment of the present invention.
[Explanation of symbols]
1,102 Silicon semiconductor substrate
2,102 Field shield element isolation structure
3,103 Device active region
4,104 Gate oxide film
5,105 Tunnel oxide film
6,44,54,106,144 source
7, 45, 55, 107, 145 Drain
7a Non-formation area
8 ONO film
9 Floating gate
10 Control gate
11, 11'111 convex part
21, 121 Field gate oxide film
22,122 Polycrystalline silicon film
23, 24, 64, 123, 124 Silicon oxide film
31, 33, 131 Polycrystalline silicon film
41, 51, 141 sidewall
42, 52, 142 Low concentration diffusion layer
43, 53, 143 High concentration diffusion layer
61 Pad oxide film
62 Silicon nitride film
63 groove
65 Trench type element isolation structure
108 Gate electrode

Claims (2)

A source and a drain;
A floating gate patterned through an insulating film on a channel region of a semiconductor substrate formed between the source and the drain;
In a semiconductor device comprising a control gate formed on the floating gate via a dielectric film,
The floating gate includes first and second wiring patterns,
The first wiring pattern has a convex portion formed of the second wiring pattern on an upper surface,
The second wiring pattern is formed with a pattern width smaller than the first wiring pattern width,
The source and the drain are formed in a surface region of the semiconductor substrate located on both sides of the convex portion,
Wherein a surface of said semiconductor substrate partially exposed by removing positioned above the drain of the insulating film, Ri Contact the thin tunnel insulating film than the film thickness of the insulating film is formed,
Before SL source and the drain are a first impurity layer low-concentration impurity respectively is introduced,
A sidewall conductive film is formed on the dielectric film so as to cover a side surface of the convex portion via the dielectric film, and the sidewall conductive film is integrated with the control gate. A high-concentration impurity is introduced into a surface region of the semiconductor substrate located on both sides to form a second impurity layer, and the first impurity layer and the second impurity layer are joined. A semiconductor device. Forming an element isolation structure on a semiconductor substrate to define an element active region;
Forming an insulating film on the device active region;
Removing a part of the insulating film and thermally oxidizing the exposed surface of the semiconductor substrate to form a tunnel insulating film;
Forming a first conductive film on the entire surface of the insulating film and the tunnel insulating film including on the element isolation structure, and planarizing a surface of the first conductive film;
A band-shaped mask is formed on the planarized first conductive film, the first conductive film is patterned until the surface of the element isolation structure is exposed, and a convex portion following the mask is formed on the upper surface. Processing the first conductive film into a shape having, and dividing the first conductive film for each element active region;
A low-concentration impurity is introduced into the semiconductor substrate through the first conductive film, and a low-concentration first impurity layer is formed in a surface region of the semiconductor substrate located on both sides of the convex portion. The tunnel insulating film is positioned on the first impurity layer;
Forming a dielectric film on the entire surface of the first conductive film including on the element isolation structure;
Forming a second conductive film on the dielectric film; anisotropically etching the entire surface of the second conductive film until the surface of the dielectric film is exposed; Forming a sidewall conductive film leaving the second conductive film on the side surface of the portion;
A high-concentration impurity is introduced into the semiconductor substrate through the dielectric film and the floating gate, and a high-concentration second impurity layer is formed at portions located on both sides of the sidewall conductive film in the surface region of the semiconductor substrate. Forming and bonding the first impurity layer and the second impurity layer;
Forming a third conductive film on the dielectric film and the sidewall conductive film;
Patterning the third conductive film, the dielectric film, and the first conductive film to form a floating gate leaving the first conductive film in an island shape corresponding to each element active region; And a step of forming a control gate leaving the third conductive film so as to extend through the dielectric film on the floating gate.

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