KR20020093260A - Method for forming metal interconnection layer of seniconductor device - Google Patents
Method for forming metal interconnection layer of seniconductor device Download PDFInfo
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- KR20020093260A KR20020093260A KR1020010031727A KR20010031727A KR20020093260A KR 20020093260 A KR20020093260 A KR 20020093260A KR 1020010031727 A KR1020010031727 A KR 1020010031727A KR 20010031727 A KR20010031727 A KR 20010031727A KR 20020093260 A KR20020093260 A KR 20020093260A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 90
- 239000002184 metal Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 53
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 230000008569 process Effects 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229910010272 inorganic material Inorganic materials 0.000 claims description 6
- 239000011147 inorganic material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 14
- 239000006117 anti-reflective coating Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 23
- 238000009792 diffusion process Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 229910021645 metal ion Inorganic materials 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게는, CVD 공정에 의한 TiN막을 금속배선의 캡핑층(Capping Layer)으로서 적용하는 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings of semiconductor devices, and more particularly, to a method for forming metal wirings by applying a TiN film by a CVD process as a capping layer of metal wiring.
주지된 바와 같이, 금속배선의 재료로서는 알루미늄(Al)이 주로 이용되어 왔으며, 최근들어, 구리(Cu)의 이용이 증가되고 있는 추세이다. 이러한 알루미늄 또는 구리 재질의 금속배선은 전기전도도가 매우 우수하고, 아울러, 가공성이 좋기 때문에 소자의 전기적 특성을 확보하는데 매우 유리하다.As is well known, aluminum (Al) has been mainly used as a material for metal wiring, and in recent years, the use of copper (Cu) is increasing. The metal wiring of aluminum or copper material is very advantageous in securing electrical characteristics of the device because of its excellent electrical conductivity and good processability.
한편, 알루미늄 또는 구리 재질의 금속배선은 반도체 제조 공정 동안, 또는, 소자의 동작시에 흐르는 전류 및 이에 기인해서 발생되는 주울 열(joule heating)로 인하여, 필연적으로 전자 이동(electromigration) 또는 외방 확산이 일어나게 되며, 이로 인해, 소자의 전기적 특성에 악영향을 미치게 된다. 특히, 알루미늄 금속배선의 경우에, 전자 이동에 기인해서 보이드(void), 또는, 힐락(hillock)과 같은 현상이 발생됨으로써, 단선(open)과 같은 치명적인 결함이 발생할 수 있으며, 이러한 전자 이동 현상은 금속배선의 선폭 및 두께가 감소됨에 따라 전류 밀도(current density)가 증가되어 더 높은 주울 열 발생이 일어나게 되면서 그 발생 정도는 더욱 심화될 것으로 예상된다.On the other hand, the metal wiring made of aluminum or copper is inevitably caused by electromigration or outward diffusion due to the current flowing during the semiconductor manufacturing process or the operation of the device and the Joule heating generated thereby. This can adversely affect the electrical properties of the device. In particular, in the case of aluminum metal wiring, a phenomenon such as void or hillock may occur due to electron movement, and a fatal defect such as open may occur. As the line width and thickness of the metal wires are reduced, the current density is increased to generate higher Joule heat, which is expected to increase.
따라서, 알루미늄 또는 구리 재질의 금속배선을 포함한 대부분의 금속배선은 그 하부에 베리어막(barrier layer)을, 그리고, 상부에 난반사막(Anti Reflective Coating layer)을 배치시킴으로써, 상기 베리어막과 난반사막이 각각 고유의 기능, 예컨데, 상기 베리어막이 배선용 금속막의 접착력 증대 및 기판 실리콘과의 반응을 억제시키도록 기능하고, 난반사막이 식각 프로파일의 유지하도록 기능하도록 하는 것 이외에, 부가적으로 전자 이동에 의한 금속이온 이동 및 확산에 기인하는 문제들을 최대한 감소시키는 기능을 하도록 하고 있다.Therefore, most metal wirings, including metal wirings made of aluminum or copper, have a barrier layer at the bottom thereof and an anti-reflective coating layer at the top thereof, whereby the barrier film and the diffuse reflection film are respectively formed. In addition to the inherent function, for example, the barrier film functions to increase the adhesion of the metal film for wiring and to suppress the reaction with the substrate silicon, and to allow the diffuse reflection film to maintain the etching profile, additionally, metal ion movement by electron transfer. And to minimize the problems caused by diffusion.
그런데, 이러한 금속배선 구조에서는 베리어막과 난반사막에 의해 배선용 금속막의 하부 및 상부 방향으로의 전자 이동에 의한 금속이온 이동 및 확산은 억제 가능하지만, 측면으로의 금속이온 이동 및 확산은 여전히 존재하게 된다. 이에, 최근의 금속배선 공정에서는 금속배선을 캡핑층(Capping Layer)으로 덮음으로써, 금속배선 측면 방향으로의 금속이온 이동 또는 확산을 방지시키고 있다.By the way, in the metal wiring structure, the barrier film and the diffuse reflection film can suppress the movement and diffusion of metal ions due to the movement of electrons in the lower and upper directions of the wiring metal film, but the movement and diffusion of metal ions to the side surfaces still exist. . Therefore, in the recent metallization process, the metallization is covered with a capping layer, thereby preventing the movement or diffusion of metal ions in the metallization side direction.
도 1은 종래 캡핑층이 형성된 금속배선을 도시한 단면도이다. 여기서, 도 1은 하지층을 포함한 반도체 기판, 2는 Ti/TiN 재질의 베리어막, 3은 알루미늄 또는 구리로된 배선용 금속막, 4는 Ti/TiN 재질의 제1난반사막, 5는 무기질의 제2난반사막, 6은 금속배선, 7은 산화막(Oxide) 또는 질산화막(Oxynitride)으로된 캡핑층, 10는 산화막 계열의 층간절연막을 각각 나타낸다.1 is a cross-sectional view illustrating a metal wiring in which a capping layer is formed in the related art. 1 is a semiconductor substrate including an underlayer, 2 is a barrier film made of Ti / TiN material, 3 is a wiring metal film made of aluminum or copper, 4 is a first diffuse reflection film made of Ti / TiN material, and 5 is made of inorganic material. 2 diffuse reflection film, 6 is a metal wiring, 7 is a capping layer made of oxide or oxynitride, and 10 is an oxide-based interlayer insulating film, respectively.
도시된 바와 같이, 금속배선(6)은 베리어막(2), 배선용 금속막(3) 및 난반사막(4, 5)의 적층 구조로 이루어지며, 이러한 금속배선(6)은 산화막 또는 질산화막 재질의 캡핑층(7)으로 덮혀져 있고, 그리고, 층간절연막(Inter Metal Layer : 이하, IMD)이 전체 구조물 상에 도포되어 있다.As shown, the metal wiring 6 has a laminated structure of the barrier film 2, the wiring metal film 3, and the diffuse reflection films 4 and 5, and the metal wiring 6 is formed of an oxide film or a nitrification material. Is covered with a capping layer 7, and an interlayer insulating film (hereinafter referred to as IMD) is applied over the entire structure.
한편, 이러한 구조에 있어서, 알루미늄 또는 구리로된 배선용 금속막에서의 전자 이동 및 확산은 베리어막과 난반사막 및 캡핑층에 의해 억제될 수 있지만, 금속배선의 선폭 및 금속배선들간의 간격(이하, 스페이스라 칭함) 감소가 요구되면서 이웃하는 금속배선들 사이에서의 기생 캐패시턴스에 의한 신호 지연 현상이 심화됨으로써, 결국, 전술한 바와 같은 구조의 금속배선은 소자의 전기적 특성을 확보할 수 없다는 문제를 갖게 된다.On the other hand, in this structure, electron transfer and diffusion in the wiring metal film made of aluminum or copper can be suppressed by the barrier film, the diffuse reflection film, and the capping layer, but the line width of the metal wiring and the spacing between the metal wirings (hereinafter, As a reduction is required, signal delay due to parasitic capacitance between neighboring metal wires is intensified, and as a result, the metal wire structure as described above has a problem in that it is impossible to secure the electrical characteristics of the device. do.
따라서, 최근에는 금속배선들간의 사이에 개재되는 유전막, 즉, 층간절연막의 재질로서 저유전율(Low-k) 절연막을 이용함으로써, 기생 캐패시턴스에 의한 신호 지연 현상을 최대한 억제시키고 있다.Therefore, recently, a low dielectric constant (Low-k) insulating film is used as the material of the dielectric film interposed between the metal wirings, that is, the interlayer insulating film, thereby minimizing the signal delay caused by parasitic capacitance.
그러나, 층간절연막의 재질로서 저유전율 절연막을 이용하는 방법은, 예컨데, 0.2㎛×0.2㎛ 이하의 선폭 및 스페이스를 갖는 금속배선에 적용될 경우, 금속배선들 사이에 개재되는 유전막의 유전상수 값에서 캡핑층의 비중이 높아지게 되고, 여기서, 산화막 또는 질산화막으로된 캡핑층의 유전율은 저유전율 절연막에 비해 상대적으로 높기 때문에 상기 저유전율 절연막에 의한 유전율 감소 효과는 미약하게 되며, 결국, 신호 지연 문제는 해결되지 못한다.However, a method of using a low dielectric constant insulating film as a material of an interlayer insulating film, for example, when applied to a metal wiring having a line width and space of 0.2 μm × 0.2 μm or less, a capping layer at a dielectric constant value of a dielectric film interposed between the metal wires. Since the dielectric constant of the capping layer made of an oxide film or a nitric oxide film is relatively higher than that of the low dielectric constant insulating film, the dielectric constant reduction effect of the low dielectric constant insulating film becomes weak, and thus, the signal delay problem is not solved. can not do it.
또한, 도 1에 도시된 바와 같이, 산화막 또는 질산화막 재질의 캡핑층(7)은 그 형성시에 금속배선(6)의 상부에서 오버행(Over-hang) 현상이 발생되기 때문에, 후속 공정에서 갭필(gap-fill) 문제를 야기시키게 되며, 아울러, 이러한 갭필의 문제는 캠핑층으로 고밀도 플라즈마 산화막(High Density Plasma Oxide)으로 형성하는 것에 의해 해결 가능하지만, 이 방법은 유전율 측면에서는 바람직하지 못하다.In addition, as shown in FIG. 1, the capping layer 7 made of an oxide film or an oxynitride film has an overhang phenomenon on the upper portion of the metal wiring 6 at the time of its formation. (gap-fill) problem, and also, the gap fill problem can be solved by forming a high density plasma oxide (High Density Plasma Oxide) in the camping layer, this method is not preferable in terms of permittivity.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 층간절연막의 재질인 저유전 절연막의 유전 특성을 확보할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of securing dielectric properties of a low dielectric insulating film, which is a material of an interlayer insulating film.
또한, 본 발명은 고집적화에 기인하는 층간절연막의 갭필 문제를 해결할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can solve the gap fill problem of an interlayer insulating film due to high integration.
게다가, 본 발명은 금속배선의 전기적 특성을 확보할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 또 다른 목적이 있다.In addition, another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of securing the electrical characteristics of the metal wiring.
도 1은 종래 기술에 따라 형성된 금속배선을 도시한 단면도.1 is a cross-sectional view showing a metal wiring formed according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 금속배선 형성방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method for forming metal wiring according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 20 : 하지층11 semiconductor substrate 20 base layer
21 : 베리어 금속막 22 : 배선용 금속막21: barrier metal film 22: wiring metal film
23 : 제1난반사막 24 : 제2난반사막23: first diffused desert 24: second diffused desert
30 : 금속배선 31 : TiN막30 metal wiring 31 TiN film
31a : TiN 스페이서 32 : 저유전율 절연막31a: TiN spacer 32: low dielectric constant insulating film
상기와 같은 목적을 달성하기 위한 본 발명의 금속배선 형성방법은, 반도체 기판 상에 베리어막, 배선용 금속막 및 난반사막을 차례로 증착하고, 그런다음, 상기 난반사막, 배선용 금속막 및 베리어막을 패터닝하여 금속배선을 형성한다. 이어서, 상기 금속배선을 포함한 반도체 기판 상에 캡핑층(Capping Layer)으로서 CVD 공정으로 TiN막을 증착한 다음, 상기 TiN막을 블랭킷 식각하여 상기 금속배선의 양측벽에 TiN 스페이서를 형성한다.In the metal wiring forming method of the present invention for achieving the above object, a barrier film, a wiring metal film and a diffuse reflection film is sequentially deposited on a semiconductor substrate, and then the diffuse reflection film, the wiring metal film and the barrier film are patterned to form a metal. Form the wiring. Subsequently, a TiN film is deposited by a CVD process as a capping layer on the semiconductor substrate including the metal wiring, and the TiN film is blanket-etched to form TiN spacers on both sidewalls of the metal wiring.
여기서, 본 발명의 금속배선 형성방법은 상기 TiN 스페이서를 금속배선을 포함한 반도체 기판 상에 CVD 공정으로 TiN막을 증착함과 동시에 RF 처리를 반복하여 형성할 수도 있다.Here, in the method for forming a metal wiring of the present invention, the TiN spacer may be formed by repeatedly depositing a TiN film on a semiconductor substrate including a metal wiring by a CVD process and simultaneously performing an RF treatment.
또한, 본 발명의 금속배선 형성방법은, 상기 난사반사막을 Ti/TiN으로된 제1난반사막과 무기질 물질로된 제2난반사막으로 구성하며, 상기 무기질 물질로된 제2난반사막은 300∼1,000Å 두께로 형성한다.In addition, the method for forming a metal wiring according to the present invention comprises the diffuse reflection film comprising a first diffuse reflection film made of Ti / TiN and a second diffuse reflection film made of an inorganic material, and the second diffuse reflection film made of the inorganic material is 300 to 1,000 mW. Form to thickness.
게다가, 본 발명의 금속배선 형성방법은 CVD 공정에 의한 TiN막을 500℃ 이하의 온도에서 100∼500Å 두께로 증착한다.In addition, the metal wiring forming method of the present invention deposits a TiN film by a CVD process to a thickness of 100 to 500 kPa at a temperature of 500 ° C or lower.
아울러, 본 발명의 금속배선 형성방법은 배선용 금속막으로서 알루미늄막 또는 구리막을 이용한다.In addition, the metal wiring formation method of this invention uses an aluminum film or a copper film as a metal film for wiring.
본 발명에 따르면, 캡핑층으로서 CVD 공정에 의한 TiN을 이용함으로써, 층간절연막의 저유전율 특성을 확보하면서, 고집적화에 기인하는 갭필 문제도 해결할 수 있고, 아울러, 금속배선에서의 신호 지연의 문제도 해결할 수 있다.According to the present invention, by using TiN by the CVD process as the capping layer, it is possible to solve the gap fill problem caused by high integration while securing the low dielectric constant characteristics of the interlayer insulating film, and also to solve the problem of signal delay in metal wiring. Can be.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시에에 따른 금속배선 형성방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.2A to 2D are cross-sectional views illustrating a method for forming a metal wiring according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(11) 상에 공지의 공정을 통해 트랜지스터(도시안됨)를 포함한 하지층(20)을 형성한다. 그런다음, 하지층(20) 상에 Ti/TiN으로된 베리어막(21)과, 알루미늄 또는 구리로된 배선용 금속막(22), Ti/TiN으로된 제1난반사막(23) 및 질산화막과 같은 무기질 물질로된 제2난반사막(24)을 차례로 증착한다. 이어서, 제2 및 제1난반사막(24, 23)과 알루미늄막(22) 및 베리어막(21)을 공지의 마스크 공정 및 RIE 공정을 통해 패터닝하여 금속배선(30)을 형성한다.Referring to FIG. 2A, an underlayer 20 including a transistor (not shown) is formed on a semiconductor substrate 11 through a known process. Then, the barrier film 21 made of Ti / TiN, the wiring metal film 22 made of aluminum or copper, the first diffuse reflection film 23 made of Ti / TiN, and the nitride oxide film were formed on the base layer 20. A second diffuse reflection film 24 made of the same inorganic material is deposited one after another. Subsequently, the second and first diffuse reflection films 24 and 23, the aluminum film 22, and the barrier film 21 are patterned through a well-known mask process and RIE process to form the metal wiring 30.
여기서, 상기 제1난반사막(23)은 식각 배선용 금속막(22)에서의 전자 이동 또는 외방 확산을 방지하기 위해 형성하는 것이며, 상기 제2난반사막(24)은 금속배선의 식각 프로파일을 유지하면서 후속의 블랭킷 식각시에 금속배선(30)을 보호하기 위해 형성하는 것이다. 이때, 상기 제2난반사막(24)은 종래 보다는 두껍게, 예컨데, 300∼1,000Å 두께로 형성함이 바람직하다.Here, the first diffuse reflection film 23 is formed to prevent electron movement or outward diffusion in the etch wiring metal film 22, while the second diffuse reflection film 24 maintains the etching profile of the metal wiring. It is formed to protect the metal wiring 30 during subsequent blanket etching. At this time, the second diffuse reflection film 24 is thicker than the prior art, for example, preferably formed to a thickness of 300 ~ 1,000∼.
도 2b를 참조하면, 금속배선(30)을 포함한 반도체 기판(11)의 전체 상에 캡핑층으로서 CVD(Chemical Vapor Deposition) 공정으로 TiN막(31)을 100∼500Å 두께로 증착한다. 이때, 상기 CVD 공정에 의한 TiN막(31)은 500℃ 이하의 온도에서 증착하며, 아울러, 열적 버짓(Thermal Budget)을 줄이기 위해 TDMAT를 전구체로 이용한다.Referring to FIG. 2B, a TiN film 31 is deposited to a thickness of 100 to 500 Å by a CVD (Chemical Vapor Deposition) process as a capping layer over the entire semiconductor substrate 11 including the metal wiring 30. In this case, the TiN film 31 by the CVD process is deposited at a temperature of 500 ° C. or less, and in addition, TDMAT is used as a precursor to reduce the thermal budget.
도 2c를 참조하면, TiN막을 블랭킷(blanket) 식각하여 금속배선(30)의 양측벽에 TiN 스페이서(31a)를 형성하고, 이 결과로서, 스페이서 형태로 캡핑층을 갖는 본 발명에 따른 금속배선(30)을 완성한다.Referring to FIG. 2C, the TiN film is blanket-etched to form TiN spacers 31a on both side walls of the metal wire 30, and as a result, the metal wire according to the present invention having a capping layer in the form of a spacer ( Complete 30).
이후, 도 2d를 참조하면, 상기 단계까지의 결과물 상에 저유전율 절연막을 증착하고, 이어, 도시하지는 않았으나, 후속 공정을 진행한다.Thereafter, referring to FIG. 2D, a low dielectric constant insulating film is deposited on the resultant up to the above step, and then, although not illustrated, a subsequent process is performed.
상기와 같은 본 발명의 금속배선 형성방법에 있어서, 캡핑층이 스텝 커버리지가 양호한 CVD TiN막으로 형성되며, 또한, 종래 산화막 계열의 캡핑층이 1,000∼3,000Å 정도의 두께로 증착되는 것에 비해 상기 CVD TiN막은 100∼500Å 정도의 두께로 증착되기 때문에, 그 증착시에 오버행 현상을 발생되지 않으며, 따라서, 오버행으로 인한 후속에서의 갭필 문제가 근본적으로 해결될 수 있다.In the metal wiring forming method of the present invention as described above, the capping layer is formed of a CVD TiN film having good step coverage, and the CVD capping layer is conventionally deposited with a thickness of about 1,000 to 3,000 kPa. Since the TiN film is deposited to a thickness of about 100 to 500 占 퐉, no overhang phenomenon occurs during the deposition, and therefore, the problem of gap fill after the overhang can be fundamentally solved.
또한, CVD TiN막은 절연막이 아닌 금속막이므로, 배선용 금속막의 저항을 줄일 수 있고, 특히, 후속에서 층간절연막으로서 형성되는 저유전율 절연막의 유전율 특성 저하를 야기시키지 않으며, 그래서, 금속배선에서의 신호 지연 현상을 억제시킬 수 있는 것으로 인해 소자의 전기적 특성을 확보할 수 있게 된다.In addition, since the CVD TiN film is a metal film rather than an insulating film, the resistance of the wiring metal film can be reduced, and in particular, it does not cause a decrease in the dielectric constant characteristics of the low dielectric constant insulating film subsequently formed as an interlayer insulating film, so that the signal delay in the metal wiring is reduced. Since the phenomenon can be suppressed, it is possible to secure the electrical characteristics of the device.
게다가, TiN막은 하드 코팅(Hard Coating) 물질이며, 금속막과 절연막간의 반응 억제력이 좋기 때문에 알루미늄 배선인 경우에는 전자 이동에 의한 금속이온의 이동을, 그리고, 구리 배선인 경우에는 외방 확산을 방지할 수 있으며, 그래서,금속배선의 신뢰성도 확보할 수 있게 된다.In addition, since the TiN film is a hard coating material and has a good suppression force between the metal film and the insulating film, the movement of metal ions due to electron migration in the case of aluminum wiring, and the outward diffusion in the case of copper wiring are prevented. Thus, it is possible to ensure the reliability of the metal wiring.
한편, 전술한 실시예에서는 금속배선의 캡핑층인 TiN 스페이서를 TiN막의 증착 후에 블랭킷 식각을 수행하여 형성하지만, 본 발명의 다른 실시예로서 TiN막의 증착과 동시에 RF 처리(treatment), 즉, 아르곤 이온에 의한 수직 방향으로의 스퍼터 식각을 반복적으로 행함으로써, 금속배선의 양측벽에만 TiN 스페이서가 형성되도록 할 수도 있다.Meanwhile, in the above-described embodiment, the TiN spacer, which is a capping layer of the metallization, is formed by blanket etching after the deposition of the TiN film. However, as another embodiment of the present invention, RF treatment, that is, argon ion is performed simultaneously with the deposition of the TiN film. By repeatedly performing the sputter etching in the vertical direction, the TiN spacer may be formed only on both side walls of the metal wiring.
이상에서와 같이, 본 발명의 방법은 금속배선의 캡핑층을 CVD 공정에 의한 TiN막으로 형성하기 때문에 저유전율 절연막의 유전 특성 저하를 방지할 수 있으며, 이에 따라, 금속배선에서의 신호 지연에 의한 소자의 전기적 특성 저하를 방지할 수 있다. 또한, 상기 CVD 공정에 의한 TiN막은 스텝 커버리지가 우수하며, 그 증착 두께를 얇게 하면서도 금속배선을 보호할 수 있기 때문에 갭필 문제도 해결할 수 있다.As described above, the method of the present invention forms the capping layer of the metal interconnection with the TiN film by the CVD process, thereby preventing the deterioration of the dielectric properties of the low dielectric constant insulating film. Deterioration of the electrical characteristics of the device can be prevented. In addition, the TiN film by the CVD process is excellent in step coverage, and the gap fill problem can be solved because the thickness of the TiN film can be reduced while protecting the metal wiring.
게다가, 본 발명의 방법은 캡핑층을 포함한 베리어막 및 난반사막에 의해서 배선용 금속막이 외부와 격리되도록 하기 때문에 상기 배선용 금속막에서의 전자 이동 또는 외방 확산을 방지할 수 있으며, 이에 따라, 그 자신의 신뢰성은 물론 소자의 신뢰성도 향상시킬 수 있다.In addition, the method of the present invention allows the wiring metal film to be isolated from the outside by the barrier film and the diffuse reflection film including the capping layer, thereby preventing the movement of electrons or the outward diffusion in the wiring metal film. Not only the reliability but also the reliability of the device can be improved.
아울러, 본 발명의 방법은 금속막에 대한 화학적기계연마(Chemical Mechanical Polishing)를 행하지 않고도 다마신(Damascene) 공정과 유사한 소자 특성을 확보할 수 있기 때문에 비용 절감의 효과도 얻을 수 있다.In addition, the method of the present invention can achieve cost reduction because device characteristics similar to the damascene process can be obtained without performing chemical mechanical polishing on the metal film.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (12)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052207A (en) * | 1995-12-06 | 1997-07-29 | 문정환 | Method of forming fine metal wiring in semiconductor device |
| KR970052332A (en) * | 1995-12-22 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR19990074940A (en) * | 1998-03-16 | 1999-10-05 | 윤종용 | Metal wiring formation method having fluorine blocking film on sidewall |
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2001
- 2001-06-07 KR KR1020010031727A patent/KR20020093260A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052207A (en) * | 1995-12-06 | 1997-07-29 | 문정환 | Method of forming fine metal wiring in semiconductor device |
| KR970052332A (en) * | 1995-12-22 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR19990074940A (en) * | 1998-03-16 | 1999-10-05 | 윤종용 | Metal wiring formation method having fluorine blocking film on sidewall |
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