KR20020091935A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20020091935A
KR20020091935A KR1020010030753A KR20010030753A KR20020091935A KR 20020091935 A KR20020091935 A KR 20020091935A KR 1020010030753 A KR1020010030753 A KR 1020010030753A KR 20010030753 A KR20010030753 A KR 20010030753A KR 20020091935 A KR20020091935 A KR 20020091935A
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South Korea
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interlayer insulating
sac
insulating film
film
forming
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KR1020010030753A
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KR100702837B1 (en
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이상현
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삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to simplify manufacturing processes and to improve step coverage by using an SAC(Self Aligned Contact) process. CONSTITUTION: A gate pattern on which a gate electrode(104), a silicide film(106) and a hard mask(108) are sequentially stacked is formed on a silicon substrate(100) having a TI(Trench Isolation)(102). A nitride layer and an interlayer dielectric(112) are sequentially formed on the resultant structure and performed by heat flowing. After etching the interlayer dielectric(112), a nitride spacer(110a) and an SAC(h) are formed to expose the substrate(100) of an active region by selectively etching the nitride layer. A conductive layer(116) is sufficiently filled into the SAC(h). A pad is formed in the SAC(h) by polishing the conductive layer(116) and the interlayer dielectric(112) so as to expose the nitride spacer(110a).

Description

반도체 소자 제조방법 {Method for fabricating semiconductor device}Semiconductor device manufacturing method {Method for fabricating semiconductor device}

본 발명은 SAC(Self Align Contact) 프로세스를 적용한 반도체 소자 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device to which a self alignment contact (SAC) process is applied.

반도체 소자의 고집적화가 진행됨에 따라 소자 제조공정이 더욱 복잡해지고 있으며, 특히 포토(photo) 공정의 미스-얼라인 마진(mis-align margin) 확보에 유리한 콘택 형성방법의 중요성이 점차 늘어가고 있다. 이에 따라 최근에는 디자인 룰이 0.21㎛ 이하급인 반도체 소자의 경우, 스몰 콘택을 형성하기 위하여 통상 SAC 프로세스를 적용하여 소자 제조를 이루고 있다.As the integration of semiconductor devices increases, the device manufacturing process becomes more complicated, and in particular, the importance of a contact forming method which is advantageous for securing a mis-align margin of a photo process is increasing. Accordingly, in recent years, in the case of semiconductor devices having a design rule of 0.21 µm or less, device manufacturing is generally performed by applying a SAC process to form small contacts.

그러나 종래의 SAC 프로세스는 공정이 복잡하고, 여러 차례의 힛 플로우(heat flow) 공정 및 에치백(etchback) 공정을 포함하고 있어 디바이스의 쉬링크(shrink)에 의해 트랜지스터의 펀치 쓰루 마진(punch through margin)이 줄어들고 파티클이 많이 발생하는 등의 단점이 있다.Conventional SAC processes, however, are complex and include multiple heat flow and etchback processes, resulting in punch through margins of transistors due to shrinking of the device. ), And particles are generated a lot.

이를 도 1a ~ 도 1f에 제시된 SAC 프로세스를 적용한 종래의 반도체 소자 제조방법을 보인 공정순서도를 참조하여 살펴보면 다음과 같다. 여기서는 편의상 상기 공정을 제 6 단계로 구분하여 설명한다.This will be described below with reference to a process flowchart showing a method of manufacturing a conventional semiconductor device to which the SAC process shown in FIGS. 1A to 1F is applied. For convenience, the process is divided into six steps.

제 1 단계로서, 도 1a와 같이 TI(Trench Isolation)(12)가 구비된 실리콘 기판(10) 상에 폴리실리콘 재질의 게이트 전극(14)과 실리사이드막(16) 및 절연마스크(18)가 순차 적층된 구조의 결과물을 형성한다. 여기서, Ti(12) 상에 형성된 게이트 전극은 패스(path) 트랜지스터용 전극을 나타내고, 액티브영역에 형성된 전극은 억세스(access) 트랜지스터용 전극을 나타낸다. 이어, 상기 결과물을 포함한 기판(10) 상에 이후 스페이서로 이용될 소정 두께의 질화막(20)을 형성하고, 상기 질화막(20) 사이의 액티브영역이 충분히 채워지도록 상기 질화막(20) 상에 산화막 재질의 제 1 층간절연막(22)을 8000 ~ 10000Å 두께로 형성한 다음, 힛 플로우 공정을 실시한다. 힛 플로우 공정으로 게이트 전극(14) 사이의 틈새를 메우고 나면 제 1 층간절연막(22)의 두께가 초기보다 10 ~ 20% 정도 줄어들므로, 제 1 층간절연막(22)이 약 6000 ~ 8000Å의 두께를 유지하게 된다.As a first step, as shown in FIG. 1A, a polysilicon gate electrode 14, a silicide layer 16, and an insulating mask 18 are sequentially formed on a silicon substrate 10 having a trench isolation (TI) 12. The result is a stacked structure. Here, a gate electrode formed on Ti 12 represents an electrode for a path transistor, and an electrode formed in an active region represents an electrode for an access transistor. Subsequently, an nitride film 20 having a predetermined thickness to be used as a spacer is formed on the substrate 10 including the resultant, and an oxide film material is formed on the nitride film 20 to sufficiently fill an active region between the nitride films 20. The first interlayer insulating film 22 is formed to a thickness of 8000 to 10000 mm, and then the thin flow process is performed. After the gap between the gate electrodes 14 is filled in the flow process, the thickness of the first interlayer insulating film 22 is reduced by about 10 to 20% from the initial stage. Thus, the first interlayer insulating film 22 is about 6000 to 8000 mm thick. Will be maintained.

제 2 단계로서, 도 1b와 같이 절연마스크(18) 상단의 질화막(20) 표면이 노출되도록 제 1 층간절연막(22)을 CMP 처리하여 막질 평탄화를 이룬 다음, 그 위에산화막 재질의 제 2 층간절연막(24)을 형성한다.As a second step, as shown in FIG. 1B, the first interlayer insulating film 22 is subjected to CMP treatment so that the surface of the nitride film 20 on the insulating mask 18 is exposed to form a planarized film, and then the second interlayer insulating film of oxide film is formed thereon. To form (24).

제 3 단계로서, 도 1c와 같이 제 2 층간절연막(24) 상에 콘택 형성부를 한정하는 레지스트 패턴(26)을 형성하고, 이를 마스크로해서 제 2 층간절연막(24)과 제 1 층간절연막(22)을 순차식각한다.As a third step, a resist pattern 26 defining a contact forming portion is formed on the second interlayer insulating film 24 as shown in FIG. 1C, and the second interlayer insulating film 24 and the first interlayer insulating film 22 are formed using the mask as a mask. ) Is sequentially etched.

제 4 단계로서, 도 1d와 같이 레지스트 패턴(26)을 제거하고, 식각처리된 상기 절연막(24),(22)을 마스크로해서 소스와 드레인이 형성될 부분의 기판(10) 표면이 노출되도록 상기 질화막(20)을 선택식각한다. 그 결과, 게이트 전극(14)의 양 측벽으로는 질화막 재질의 스페이서(20a)가 놓이고, 스페이스(20a)와 스페이서(20a) 사이에는 SAC(h)가 정의되는 구조의 결과물이 만들어진다.As a fourth step, as shown in FIG. 1D, the resist pattern 26 is removed and the surface of the substrate 10 of the portion where the source and drain are to be formed is exposed by using the etched insulating layers 24 and 22 as a mask. The nitride film 20 is selectively etched. As a result, a spacer 20a made of a nitride film is placed on both sidewalls of the gate electrode 14, and a product having a structure in which the SAC (h) is defined is formed between the space 20a and the spacer 20a.

제 5 단계로서, 도 1e와 같이 SAC(h) 내부가 충분히 채워지도록 상기 제 2 층간절연막(24) 상에 폴리실리콘 재질의 도전막(28)을 형성한다.As a fifth step, a polysilicon conductive film 28 is formed on the second interlayer insulating film 24 such that the inside of the SAC (h) is sufficiently filled as shown in FIG. 1E.

제 6 단계로서, 도 1f와 같이 질화막 재질의 스페이스(20a)가 드러나도록 도전막과 층간절연막(24)을 함께 에치백하여 SAC(h) 내에 패드(28a)를 형성하므로써, 본 공정 진행을 완료한다. 이때, 상기 스페이서(20a)는 에치백 공정시 에치스토퍼층으로 사용된다.As a sixth step, the process is completed by etching back the conductive film and the interlayer insulating film 24 together so that the space 20a of the nitride film is exposed as shown in FIG. 1F to form the pad 28a in the SAC (h). do. In this case, the spacer 20a is used as an etch stopper layer during the etch back process.

하지만 상기 공정을 적용하여 SAC(h) 내에 패드(28a)를 형성하면, 소자 제조시 에치백 공정과 2회의 층간절연막 증착 공정 및 2회의 힛 플로우 공정이 요구되므로 공정이 복잡하고, 힛 버짓(heat budget)면에서 불리하다는 문제가 발생된다.However, if the pad 28a is formed in the SAC (h) by applying the above process, the process is complicated because an etch back process, two interlayer dielectric film deposition processes, and two thin flow processes are required to manufacture the device. A disadvantage arises in terms of budget.

뿐만 아니라 에치백 공정으로 패드(28a) 형성을 마감하므로 파티클 발생이 많고, 도 1f에 보인 바와 같이 최종 완성된 패드(28a) 상부의 단면 프로파일 또한고르지 못하여 평탄도가 떨어지며, 이로 인해 후속 포토 공정시 얼라인 관점에서도 불량이 발생될 가능성이 높아지는 등의 문제가 유발된다.In addition, since the pad 28a is formed by the etch back process, there are many particles, and as shown in FIG. 1F, the cross-sectional profile of the upper part of the final pad 28a is also uneven, resulting in inferior flatness. Problems such as an increase in the likelihood of defects are also caused from the alignment point of view.

본 발명의 목적은, 기존에 2회에 걸쳐 진행되던 층간절연막 증착 공정과 힛 플로우 공정을 1회로 줄이고, 에치백 공정을 생략하며, CMP 공정으로 패드 형성을 마감할 수 있도록 SAC 프로세스를 변경하므로써, 공정을 단순화하고 파티클 발생을 억제하며 평탄도 특성을 향상시킬 수 있도록 한 반도체 소자 제조방법을 제공함에 있다.The object of the present invention is to reduce the interlayer insulating film deposition process and the wet flow process, which have been performed twice, by changing the SAC process so that the etchback process can be omitted, and the pad formation can be finished by the CMP process. The present invention provides a method for fabricating a semiconductor device that simplifies the process, suppresses particle generation, and improves flatness characteristics.

도 1a ~ 도 1f는 종래의 SAC 프로세스를 적용한 반도체 소자 제조방법을 보인 공정순서도,1A to 1F are process flowcharts showing a method of manufacturing a semiconductor device to which a conventional SAC process is applied;

도 2a ~ 도 2e는 본 발명에 의한 SAC 프로세스를 적용한 반도체 소자 제조방법을 보인 공정순서도이다.2A to 2E are process flowcharts showing a method of manufacturing a semiconductor device to which the SAC process according to the present invention is applied.

상기 목적을 달성하기 위하여 본 발명에서는, TI가 구비된 실리콘 기판 상에 게이트 전극과 실리사이드막 및 절연 마스크가 순차 적층된 구조의 결과물을 형성하는 단계; 상기 결과물을 포함한 상기 기판 상에 소정 두께의 질화막을 형성하는 단계; 상기 질화막 상에 12000Å 이상의 두께로 층간절연막을 형성한 후, 이를 힛 플로우시키는 단계; 콘택 형성부를 한정하는 레지스트 패턴을 마스크로해서 상기 층간절연막을 식각하는 단계; 식각처리된 상기 층간절연막을 마스크로해서 소스·드레인이 형성될 부분의 상기 기판 표면이 노출되도록 상기 질화막을 선택식각하여, 질화막 스페이서와 SAC를 각각 형성하는 단계; 상기 SAC 내부가 충분히 채워지도록 상기 층간절연막 상에 도전막을 형성하는 단계; 및 상기 질화막 스페이서가노출되도록 상기 도전막과 상기 층간절연막을 함께 CMP 처리하여, 상기 SAC 내에 패드를 형성하는 단계로 이루어진 반도체 소자 제조방법이 제공된다.In order to achieve the above object, in the present invention, forming a result of the structure in which the gate electrode, the silicide film and the insulating mask are sequentially stacked on the silicon substrate with TI; Forming a nitride film having a predetermined thickness on the substrate including the resultant product; Forming an interlayer insulating film on the nitride film with a thickness of 12000 GPa or more, and then rapidly flowing it; Etching the interlayer insulating film using a resist pattern defining a contact forming portion as a mask; Using the etched interlayer insulating film as a mask to selectively etch the nitride film so as to expose the surface of the substrate where portions of the source and drain are to be formed, thereby forming nitride spacers and SACs, respectively; Forming a conductive film on the interlayer insulating film to sufficiently fill the SAC; And forming a pad in the SAC by CMP-processing the conductive film and the interlayer insulating film together so that the nitride film spacers are exposed.

이와 같이 공정을 진행할 경우, 기존에 2회에 걸쳐 진행되던 층간절연막 증착 공정과 힛 플로우 공정을 1회로 줄일 수 있게 될 뿐 아니라 에치백 공정을 스킵 할 수 있고, CMP 공정으로 패드 형성을 마감할 수 있게 된다.In this way, not only can the interlayer insulation film deposition process and the wet flow process be performed twice, but also the etch back process can be skipped, and the pad formation can be finished by the CMP process. Will be.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 2a ~ 도 2e는 본 발명에서 제안된 SAC 프로세스를 적용한 반도체 소자 제조방법을 보인 공정순서도이다. 상기 공정수순도를 참조하여 그 제조방법을 제 5 단계로 구분하여 설명하면 다음과 같다.2A to 2E are process flowcharts showing a method of manufacturing a semiconductor device to which the SAC process proposed in the present invention is applied. Referring to the above-mentioned process purity, the manufacturing method is divided into a fifth step as follows.

제 1 단계로서, 도 2a와 같이 TI(102)가 구비된 실리콘 기판(100) 상에 폴리실리콘 재질의 게이트 전극(104)과 실리사이드막(106) 및 절연마스크(108)가 순차 적층된 구조의 결과물을 형성한다. 여기서, Ti(102) 상에 형성된 게이트 전극은 패스 트랜지스터용 전극을 나타내고, 액티브영역에 형성된 전극은 억세스 트랜지스터용 전극을 나타낸다. 이어, 상기 결과물을 포함한 기판(100) 상에 이후 스페이서로 사용될 소정 두께의 질화막(110)을 형성하고, 상기 질화막(110) 사이의 액티브영역이 충분히 채워지도록 상기 질화막(110) 상에 CVD법으로 BPSG 재질의 제 1 층간절연막(112)을 12000Å 이상의 두께로 형성하여 칩내 평탄화를 이룬 다음, 이를 힛 플로우시켜 게이트 전극(104) 틈새에 생길 수 있는 보이드(void)를 방지한다. 힛 플로우 공정으로 게이트 전극(104) 사이의 틈새를 메우고 나면 층간절연막(112)의두께가 초기보다 10 ~ 20% 정도 줄어들므로, 층간절연막(112)이 약 10000Å 이상의 두께를 유지하게 된다.As a first step, as shown in FIG. 2A, the polysilicon gate electrode 104, the silicide layer 106, and the insulating mask 108 are sequentially stacked on the silicon substrate 100 having the TI 102. Form the result. Here, the gate electrode formed on Ti 102 represents an electrode for a pass transistor, and the electrode formed in an active region represents an electrode for an access transistor. Next, a nitride film 110 having a predetermined thickness to be used later as a spacer is formed on the substrate 100 including the resultant, and the CVD method is performed on the nitride film 110 to sufficiently fill the active region between the nitride films 110. The first interlayer insulating film 112 of BPSG material is formed to a thickness of 12000 GPa or more to achieve planarization in the chip, and then flows to prevent voids that may occur in the gap between the gate electrode 104. After filling the gap between the gate electrodes 104 by the flow process, the thickness of the interlayer insulating film 112 is reduced by about 10 to 20% from the initial time, so that the interlayer insulating film 112 maintains a thickness of about 10000 kPa or more.

제 2 단계로서, 도 2b와 같이 상기 층간절연막(112) 상에 콘택 형성부를 한정하는 레지스트 패턴(114)을 형성하고, 이를 마스크로해서 층간절연막(112)을 선택식각하여, 게이트 전극(104) 사이에 질화막(110)이 노출되도록 한다.As a second step, as shown in FIG. 2B, a resist pattern 114 defining a contact forming portion is formed on the interlayer insulating layer 112, and the interlayer insulating layer 112 is selectively etched using the mask to form the gate electrode 104. The nitride film 110 is exposed in between.

제 3 단계로서, 도 2c와 같이 레지스트 패턴(114)을 제거하고, 식각처리된 층간절연막(112)을 마스크로해서 소스와 드레인이 형성될 부분의 기판(100) 표면이 노출되도록 상기 질화막(110)을 선택식각한다. 그 결과, 게이트 전극(104)의 양 측벽으로는 질화막 재질의 스페이서(110a)가 놓이고, 스페이스(110a)와 스페이서(110a) 사이에는 SAC(h)가 정의되는 구조의 결과물이 만들어진다.As a third step, as shown in FIG. 2C, the resist pattern 114 is removed, and the nitride film 110 is exposed to expose the surface of the substrate 100 where the source and drain are to be formed using the etched interlayer insulating film 112 as a mask. Select). As a result, a spacer 110a made of a nitride film is disposed on both sidewalls of the gate electrode 104, and a product having a structure in which the SAC (h) is defined is formed between the space 110a and the spacer 110a.

제 4 단계로서, 도 2d와 같이 SAC(h) 내부가 충분히 채워지도록 상기 층간절연막(112) 상에 폴리실리콘 재질의 도전막(116)을 형성한다.As a fourth step, as shown in FIG. 2D, a polysilicon conductive layer 116 is formed on the interlayer insulating layer 112 to sufficiently fill the inside of the SAC (h).

제 5 단계로서, 도 2e와 같이 질화막 재질의 스페이스(110')가 드러나도록 상기 도전막(116)과 층간절연막(112)을 함께 CMP 처리하여 SAC(h) 내에 패드(116a)를 형성하므로써, 본 공정 진행을 완료한다. 이때, 상기 스페이서(110a)는 CMP 공정시 에치스토퍼층으로 사용된다.As a fifth step, by forming the pad 116a in the SAC (h) by CMP-processing the conductive film 116 and the interlayer insulating film 112 together so that the space 110 ′ of the nitride film material is exposed as shown in FIG. 2E. Complete this process. In this case, the spacer 110a is used as an etch stopper layer in the CMP process.

상기 공정을 적용하여 SAC(h)과 패드(116a)를 제조할 경우, 기존의 제 2 층간절연막 증착 공정과 이의 후속 공정으로 실시되던 힛 플로우 공정 및 에치백 공정을 모두 스킵(skip)할 수 있게 되므로, 종래대비 공정을 단순화할 수 있을 뿐 아니라 힛 버짓 측면에서도 유리한 위치를 점할 수 있게 된다.In the case of manufacturing the SAC (h) and the pad 116a by applying the above process, it is possible to skip both the wet flow process and the etch back process performed by the existing second interlayer dielectric film deposition process and its subsequent process. Therefore, it is possible not only to simplify the process compared to the prior art, but also to occupy an advantageous position in terms of the wet budget.

게다가, CMP 공정으로 패드(116a) 형성을 마감하므로 에치백 공정을 적용하던 종래대비 파티클 발생이 줄어들고, 도 2e에서 최종 완성된 패드(116a) 상부의 단면 프로파일을 보면 알 수 있듯이 평탄도 특성 또한 기존대비 향상시킬 수 있게 되므로, 후속 공정 진행이 용이하다는 잇점을 얻을 수 있게 된다.In addition, since the formation of the pad 116a by the CMP process reduces particle generation compared to the conventional etchback process, and as shown in the cross-sectional profile of the top of the final pad 116a in FIG. The contrast can be improved, so that the following process can be easily proceeded.

이상에서 살펴본 바와 같이 본 발명에 의하면, 1) 기존 2회에 걸쳐 진행되던 층간절연막 증착 공정과 힛 플로우 공정을 1회 줄일 수 있을 뿐 아니라 에치백 공정 또한 생략할 수 있으므로 공정을 단순화할 수 있게 되고, 2) CMP 공정으로 패드 형성이 마감되므로 에치백 공정을 적용하던 종래대비 파티클 발생을 줄일 수 있을 뿐 아니라 패드 상부의 평탄화 특성 또한 향상시킬 수 있게 된다.As described above, according to the present invention, 1) it is possible to simplify the process because it can not only reduce the interlayer insulating film deposition process and the wet flow process, but also the etch back process. , 2) Since the pad formation is completed by the CMP process, it is possible to reduce particle generation as well as to improve flatness of the upper part of the pad as compared with the conventional etchback process.

Claims (3)

TI가 구비된 실리콘 기판 상에 게이트 전극과 실리사이드막 및 절연 마스크가 순차 적층된 구조의 결과물을 형성하는 단계;Forming a result of a structure in which a gate electrode, a silicide layer, and an insulating mask are sequentially stacked on a silicon substrate having a TI; 상기 결과물을 포함한 상기 기판 상에 소정 두께의 질화막을 형성하는 단계; 상기 질화막 상에 12000Å 이상의 두께로 층간절연막을 형성한 후, 이를 힛 플로우시키는 단계;Forming a nitride film having a predetermined thickness on the substrate including the resultant product; Forming an interlayer insulating film on the nitride film with a thickness of 12000 GPa or more, and then rapidly flowing it; 콘택 형성부를 한정하는 레지스트 패턴을 마스크로해서 상기 층간절연막을 식각하는 단계;Etching the interlayer insulating film using a resist pattern defining a contact forming portion as a mask; 식각처리된 상기 층간절연막을 마스크로해서 소스·드레인이 형성될 부분의 상기 기판 표면이 노출되도록 상기 질화막을 선택식각하여, 질화막 스페이서와 SAC를 각각 형성하는 단계;Using the etched interlayer insulating film as a mask to selectively etch the nitride film so as to expose the surface of the substrate where portions of the source and drain are to be formed, thereby forming nitride spacers and SACs, respectively; 상기 SAC 내부가 충분히 채워지도록 상기 층간절연막 상에 도전막을 형성하는 단계; 및Forming a conductive film on the interlayer insulating film to sufficiently fill the SAC; And 상기 질화막 스페이서가 노출되도록 상기 도전막과 상기 층간절연막을 함께 CMP 처리하여, 상기 SAC 내에 패드를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.And CMP-processing the conductive film and the interlayer insulating film together to expose the nitride film spacers, thereby forming pads in the SAC. 제 1항에 있어서, 상기 층간절연막은 BPSG 재질로 형성하는 것을 특징으로하는 반도체 소자 제조방법.The method of claim 1, wherein the interlayer insulating layer is formed of a BPSG material. 제 1항에 있어서, 상기 층간절연막은 CVD법으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the interlayer insulating film is formed by a CVD method.
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