KR20020090068A - Method of manufacturing a silicon-based single electron transistor logic device. - Google Patents

Abstract

PURPOSE: A Method of manufacturing a silicon-based single electron transistor logic device is provided to form simultaneously a multiple quantum point and a side gate on the same plane by using an electron beam etch method and a thermal oxidation deposition method. CONSTITUTION: An SOI substrate is prepared on a silicon substrate. A semiconductor layer is formed on the SOI substrate. The first photoresist pattern is formed between the semiconductor layers. The semiconductor layer is etched by using the photoresist pattern. An active region forming a source and a drain and channels is defined. The first photoresist pattern is removed. An electron beam resist pattern is formed on the active region by using an electron beam. The channel layers and side gates are formed by etching the active region. The electron beam resist pattern is removed. A gate oxide layer(30) is formed by performing a thermal oxidation process. The thickness of the channel layers is reduced by the thermal oxidation process. A photoresist is coated on a whole surface of the substrate. A photoresist pattern is formed by performing an exposure process. The side gates are doped and a source and a drain are formed by implanting dopants into the active region. A source and a drain pad(50A',50B') and a side gate pad are formed by removing the photoresist pattern. A control gate and a pad(60A,60A') are formed by coating a photoresist, forming a photoresist pattern, depositing a metal layer thereon, and removing the photoresist.

Description

Method of manufacturing a silicon-based single electron transistor logic device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a single electron logic device, and more particularly, to a method for manufacturing a single electron logic device using simultaneous formation of multiple quantum dots and side gates through electron beam exposure and a thermal oxide film.

The single-electron logic element is a complementary metal oxide semiconductor (Complementary metal) of a single-electron transistor (SET) that can add or subtract one electron to the electrode by the Coulomb blockade effect -oxide-semiconductor (CMOS) type of single-electron transistor logic element in the form of a complementary metal oxide semiconductor that uses a voltage-state at the logic level instead of the field-effect transistor (FET) in a logic circuit. SET Logic device) is typical.

The conventional single-electron logic device described above is not shown, but in two forms, a thin wire-shaped metal orthogonal to the channel for stacking an insulating oxide film on a conventional metal oxide semiconductor field effect transistor (MOSFET) and forming a quantum dot in the channel layer. In this case, a SET having a dual gate for manufacturing a gate is used as a unit device, or a SET having a single quantum dot type in which the size of a quantum dot and tunnel junction is already defined is used as a unit device. However, in the case of making a logic device using such single-electron unit devices, first, the lamination process is very complicated and unstable when using a double gate single-electron device, and second, when using a single quantum dot SET, Coulomb blockade imperfection, There are disadvantages such as voltage gain, increased power consumption by cotunneling, and reduced efficiency of functions as logic devices.

Therefore, the present invention is to solve the above-mentioned problems, by using a multi-quantum dot and side gates easily formed on the same plane at the same time by using electron beam etching and thermal oxidation lamination, the function of the single-electron logic device, especially Coulomb blockade It is an object of the present invention to provide a method of manufacturing a single-electronic logic device that can reduce the manufacturing cost by improving the safety and voltage gain, and reducing power consumption and simplifying the manufacturing process.

1A to 1F are plan views illustrating a method of manufacturing a single electron logic device according to an embodiment of the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a single electronic device according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line 2A-2A 'of FIG. 1A,

FIG. 2B is a cross-sectional view taken along the line 2B-2B 'of FIG. 1C;

FIG. 2C is a cross-sectional view taken along the line 2C-2C 'of FIG. 1D,

FIG. 2D is a cross-sectional view taken along line 2D-2D ′ of FIG. 1E.

※ Explanation of codes for main parts of drawing

10: SOI substrate 11: semiconductor substrate

12 oxide film 20 semiconductor layer and active region

20A, 20B: side gate 20C: quantum dot

20D: tunneling junction (barrier) 30: gate oxide film

40 photoresist pattern for doping mask

50A, 50B: source, drain 50A ', 50B': source, drain pad

60A: Control Gate 60A ', 60B': Gate Pad

60A1: Control (Input) Gate 60B1: Control (Input) Gate

70: output terminal

In order to achieve the above object of the present invention, according to the present invention, a semiconductor layer is first formed on an SOI substrate, and the semiconductor layer is etched to define an active region in which a source and a drain, a quantum dot connecting them and a side gate are to be formed. . Then, the active region is etched after the electron beam exposure to form a quantum dot having a submicron size or less, a junction portion and a side gate used as a tunnel barrier are simultaneously formed, a gate oxide film is formed on the entire surface of the substrate, and then the quantum dot region used as a channel is covered. A photoresist masking pattern is formed on the gate oxide layer as large as possible. Then, impurities are implanted into the active regions on both sides of the side gate and the photoresist masking pattern to dope the side gates to simultaneously form the source and drain regions, and then expose the gate oxide film to expose portions of the source and drain and side gates. After exposure and etching, the photoresist masking pattern layer for forming the first to fourth contact holes is left, and a metal film is deposited on the photoresist masking pattern layer to be filled in the first to fourth contact holes, and then a solvent such as acetone is used. The source, drain, and side gate metal pads are respectively formed by removing the photoresist masking pattern film using an agent. Then, the photoresist is applied to the entire surface of the substrate and exposed, leaving a photoresist masking pattern film for forming a control gate, and depositing a metal film on the pattern film, and then resting the remaining photoresist portions other than the metal film deposited in the shape of the photoresist masking pattern. To form a metal control gate.

In the present invention, the quantum dot, the junction portion, and the side gate form an electron beam resist pattern on a region to be formed by using an electron beam on the active region, and dryly etch the active region by using an electron beam resist pattern, followed by an electron beam resist pattern. Remove it to form.

In addition, the gate oxide film is formed in a thickness of 100 to 200 nm by a thermal oxidation process.

In addition, the metal gate thickness is formed to a thickness of 100 to 200nm by the thermal deposition process. PMMA is used as the electron beam resist.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1A to 1F and 2A to 2D are plan and cross-sectional views illustrating a method of manufacturing a single electronic device according to an exemplary embodiment of the present invention.

2A is a cross-sectional view taken along the line 2A-2A 'of FIG. 1A, FIG. 2B is a cross-sectional view taken along the line 2B-2B' of FIG. 1C, FIG. 2C is a cross-sectional view taken along the line 2C-2C 'of FIG. 1D, FIG. 2D is a cross-sectional view taken along line 2D-2D ′ of FIG. 1E.

First, FIGS. 1A and 1E and FIGS. 2A to 2D show a manufacturing process of one single-electron device which is a unit device of the single-electron logic device, and FIG. 1F shows a completed single-electron logic including the other single-electron device. Since the two symmetrical single-electron devices as the shape of the device go through the same fabrication process at the same time in the above-described fabrication process, only the fabrication process of one single-electron unit device is illustrated as an example.

1A and 2A, an SOI substrate 10 having a structure in which an oxide film 12 is stacked on a semiconductor substrate 11 such as silicon is prepared, and a semiconductor layer is formed on the SOI substrate 10. Preferably, the oxide film 12 is made of a silicon oxide film (SiO ₂ ), and the semiconductor layer is made of silicon.

Then, a first photoresist pattern (not shown) is formed between the semiconductor layers by photolithography, the semiconductor layer is etched using the photoresist pattern, and as shown in FIG. 2A, a source to be subsequently formed. And an active region 20 in which drains and channels connecting them (quantum dots 20C and tunneling junctions 20D) are to be formed. Preferably, the etching proceeds to dry or wet etching. Then, the first photoresist pattern is removed by a known method.

Referring to FIG. 1B, an electron beam resist pattern (not shown) having a submicron size is formed in the channel predetermined region by using an electron beam (E-beam) on the active region 20. Here, the electron beam resist pattern is formed using PMMA. Then, the active region 20 is etched using the electron beam resist pattern to form a channel layer (quantum dot 20C and tunneling junction 20D) and side gates 20A and 20C having a size of the submicron or less. Form. Preferably the etching proceeds to dry etching. The electron beam resist pattern is then removed by known methods. 1C and 1D, a gate oxide film 30 made of a silicon oxide film is formed on the entire surface of the substrate. Preferably, the gate oxide film 30 is formed to a thickness of 100 nm to 200 nm, more preferably 100 nm or less using a thermal oxidation process.

Referring to FIG. 1C, the channel layer (quantum dot 20C and the tunneling junction 20D) is further reduced due to a stress dependent phenomenon due to stacking of the gate oxide layer through the thermal oxidation process.

The channel layer 30A indicated by the dotted line is the channel layer before the thermal oxidation process, and 20D and 20C are the reduced quantum dot and tunneling junctions due to the PADOX phenomenon.

1D and 2C, after the photoresist is applied to the entire surface of the substrate, the photoresist pattern 40 is formed by exposure, and the side gates 20A and 20B and the photoresist pattern are formed using the photoresist pattern as a mask. Impurity ions are implanted into both active regions 20 to dope the side gates 20A and 20B, and simultaneously form the source and drain 50A and 50B, and then remove the photoresist pattern by a known method.

1E and 2D, a second photoresist pattern (not shown) is formed on the gate oxide layer 30 by photolithography, and the source and drain 50A, 50B and side gates 20A are formed using the photoresist. The gate oxide layer 30 is etched to expose a portion of 20B to form first to fourth contact layers. Preferably the etching proceeds by wet etching. Then, an aluminum film is deposited as a metal film on the gate oxide film 30 so as to be buried in the first to fourth contact holes, and the photoresist pattern is removed by a known method to contact the source and drain 50A and 50B. Source and drain pads 50A 'and 50B' and side gate pads (not shown) are formed, respectively.

Then, a photoresist is applied on the entire surface of the substrate to form a third photoresist pattern (not shown), a metal film is deposited to be embedded in the photoresist pattern, and the photoresist is removed by a known method to control the gate and pad 60A. , 60A ') at the same time. Preferably, aluminum is used as the metal of the control gate.

The manufacturing process described above illustrates a unit single electron device constituting the single electron logic device, but practically all of the manufacturing processes are simultaneously applied to each unit single electron device of the complementary single electron logic device simultaneously. Therefore, FIG. 1F illustrates a plan view of the single-electron logic device completed according to the above-described single unit electronic device manufacturing process.

Referring to FIG. 1F, a single electron unit element consisting of a control gate pad 60A 'and a control gate 60A1 indicated by a dotted line between the source and drain pads 50A' and 50B 'and a control gate pad 60B' and a dotted line An output terminal 70 is shown between the single electron unit elements composed of the control gate 60B1. Since the gate of each single-electron element is an input terminal, when a voltage is applied to the gate of one single-electron element and no voltage is applied to the gate of the other single-electron element, the resistance is very turned on, and the phase of the output voltage is reversed. One single-electron logic element becomes an inverter logic element of complementary type. In the single-electron device, the potential of the quantum dot QD is changed according to the voltage applied to each of the gates 60A1 and 60B1 so that electrons in the source move to the drain by tunneling through the quantum dot.

According to the present invention described above, it is possible to easily form a quantum dot and a tunneling barrier without forming a double gate as in the prior art. Unlike the conventional fixed tunneling barrier and quantum dot formation method, the size and adjacent effect of the quantum dot can be controlled, and the operating temperature of the device is made smaller by performing the PADOX process simultaneously with the gate oxide layer deposition. Can be improved. As a result, the manufacturing cost, driving control, and operating temperature of the device may be improved by simplifying the process of manufacturing a complementary single-electron logic device. In addition, the present invention is not limited to the above embodiments and can be carried out in various modifications without departing from the technical gist of the present invention.

Claims (3)

A method of fabricating a logic device having the feature of using a single electron device having multiple quantum dots and side gates as a unit device of a single electron logic device. A method of fabricating a single-electron device having multiple quantum dots, which is a constituent element of a single-electron logic device, wherein the formation of multiple quantum dots and side gates is performed simultaneously by using an electron beam exposure pattern and dry etching. Forming a semiconductor layer on the SOI substrate; Etching the semiconductor layer to define an active region in which a source and a drain and a channel connecting them are formed; Simultaneously forming a quantum dot, a tunneling barrier, and a side gate having a submicron size in the active region; Forming a gate oxide film on the entire surface of the substrate; Forming a side gate at the same time as forming a source and a drain by doping with a photoresist as a mask on the channel layer; Forming a photoresist pattern on the gate oxide layer and etching the source, drain and side gate portions to form first to fourth contact holes; Depositing a metal film to fill the first to fourth contact holes and removing the photoresist to form source, drain, and side gate pads, respectively; Forming a control gate by removing the photoresist after forming a photoresist pattern and depositing a metal film on the entire surface of the substrate.