KR100996778B1 - Single- electron tunneling invertor circuit and fabrication method thereof - Google Patents

Abstract

The present invention relates to a single electron tunneling inverter circuit operated by one input voltage and a method of manufacturing the same. According to the present invention, the phase difference is changed by the operation of the side gate of the SET according to the same input voltage instead of the inverter logic element due to the phase change according to the ON / OFF of each SET gate as in the related art. The output voltage can be derived. In addition, compared to the conventional CMOS type inverter using two types of transistors, N-MOS and P-MOS, only the phase difference is used in the same transistor, thereby simplifying the manufacturing and shortening the manufacturing time. Terminals can be fabricated simultaneously using electron beam lithography to improve directness. In addition, it can improve the functionality of single-electron logic circuits, achieve low power consumption, simplify the process, and shorten the process time. Can be reduced. In addition, a basic inverter logic circuit can be configured by two single-electron transistors having side gates that can control the phase of a quantum dot using a pattern formed by electron beam lithography.

Single-electron device, silicon, single-electron logic circuit, inverter, quantum dot, coulomb block

Description

Single-electron tunneling invertor circuit and fabrication method

1 is a perspective view showing a substrate including a first silicon layer, a first oxide layer, and a second silicon layer in a single electron tunneling inverter circuit according to the present invention;
2A is a perspective view illustrating a state in which a second silicon layer is etched in a single electron tunneling inverter circuit according to the present invention;
FIG. 2B is a cross sectional view of AA shown in FIG. 2A; FIG.
3 is a perspective view showing a state in which a quantum dot, a tunneling junction and an output terminal are simultaneously formed in a single electron tunneling inverter circuit according to the present invention.
4A is a perspective view showing a state in which a second oxide film is formed in a single electron tunneling inverter circuit according to the present invention;
4B is a cross-sectional view of the BB shown in FIG. 4A.
5A is a perspective view illustrating a state in which a polygate is formed in a single electron tunneling inverter circuit according to the present invention;
5B is a cross-sectional view of the CC shown in FIG. 5A.
FIG. 6 is a perspective view illustrating a state in which a second oxide layer and a poly gate are etched in a single electron tunneling inverter circuit according to the present invention; FIG.
7A is a perspective view showing a state in which a pad is formed by depositing a metal film in a single electron tunneling inverter circuit according to the present invention;
FIG. 7B is a sectional view of DD shown in FIG. 7A; FIG.
Explanation of symbols on the main parts of the drawings
10: first silicon layer 11: first oxide layer
12: second silicon layer 20: drain
22: source 24: side gate
26: output terminal 32: quantum dot
34 tunneling junction 36 output terminal
40: second oxide film 50: polygate
70: metal film

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

The present invention relates to a single electron tunneling inverter circuit and a method of manufacturing the same, and more particularly, to a single electron tunneling inverter circuit operated by one input voltage and a method of manufacturing the same.
The single-electron logic device is a conventional complementary metal oxide semiconductor (Single-Electron Transistor (SET)) capable of adding or subtracting one electron to or from a quantum dot by a coulomb blockade effect. -oxide semiconductor (CMOS) A so-called complementary metal oxide semiconductor type single-electron transistor logic element that uses a voltage-state at the logic level instead of a field-effect transistor (FET) in a logic circuit. (CMOS-type SET Logic device) is typical.

delete

delete

  The conventional single-electron logic device described above may be represented by the following three types, although not specifically illustrated. After the channel is formed, each quantum dot is formed in a spaced position according to the channel shape, and the output is derived from two input voltages. Coulomb oscillation can be used but is not suitable for direct drawing. Another type of device is a dual gate type in which an insulating oxide film is stacked on a conventional metal oxide semiconductor field effect transistor (MOSFET) and a thin wire-shaped gate is formed orthogonal to the channel to form quantum dots in the channel layer. In the single-electron logic device, when a voltage is applied to a thin wire type gate, a tunneling barrier and a quantum dot are formed in a channel layer to control tunneling of electrons by a voltage applied to the gate. However, this method has a disadvantage that the manufacturing process is high because the lamination process is very complicated and unstable, and there are many difficulties in manufacturing a thin wire gate to form a large number of quantum dots. Lastly, it is a logic device using SET in the form of a single quantum dot in which the size of the quantum dot and the tunnel junction is already determined. However, this method has the disadvantage of degrading the functional efficiency as a logic device such as incomplete coulomb blockade, small voltage gain, and increased voltage consumption by co-tunneling.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single electron tunneling inverter circuit capable of driving two single electron transistors using one input voltage by simultaneously forming side gates and an output end portion on the same plane through electron beam etching, and a method of manufacturing the same. It is.
It can improve the functionality of single-electron logic circuits, achieve low power consumption, simplify the process and shorten the process time, and drive two sets using one input voltage to improve device integration and reduce manufacturing costs. It is an object of the present invention to provide a method for manufacturing a single-electron tunneling inverter circuit.
The basic inverter logic circuit can be configured by two sets having side gates that can control the phase of the quantum dots by using a pattern formed by electron beam lithography.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Referring to the manufacturing method of the single-electron tunneling inverter circuit according to the present invention.
1 is a perspective view illustrating a substrate including a first silicon layer, a first oxide layer, and a second silicon layer in a single electron tunneling inverter circuit according to the present invention. As shown in FIG. 1, first, an SOI substrate including a first silicon layer 10, a first oxide layer 11, and a second silicon layer 12 is prepared. In this case, the second silicon layer 12 is a semiconductor layer, and a source, a drain, and an output terminal are formed.
FIG. 2A is a perspective view illustrating a state in which a second silicon layer is etched in the single-electron tunneling inverter circuit according to the present invention, and FIG. 2B is a cross-sectional view of AA shown in FIG. 2A. 2A and 2B, the second silicon layer 12 is etched to form the source 22, the drain 20, the side gate 24, and the output terminal 26 to form an active region. . In this case, the active region is formed by photo-lithography or reactive ion etching (RIE).
The side gate 24 is formed adjacent to the same plane as the quantum dot to change the phase of Coulomb Oscillation of the single-electron transistor. At this time, at least one side gate 24 is formed. In this embodiment, two side gates 24 are formed.
The output terminal 26 is formed so that the output voltage between the single electron transistors can be observed.
3 is a perspective view illustrating a state in which a quantum dot, a tunneling junction and an output terminal are simultaneously formed in a single electron tunneling inverter circuit according to the present invention. As shown in FIG. 3, the active region is formed by etching using electron beam lithography and then etched to simultaneously form the quantum dots 32, the tunneling junction 34, the output terminal 26, and the side gate 24. In this case, two quantum dots 32 are formed between the source 22 and the drain 20. Preferably, the line width of each quantum dot is less than 10 nm, and the line width of the tunneling junction 34 is less than 5 nm so that an improved Coulomb Blockade phenomenon occurs. In addition, the length of the output end 36 between each tunneling junction 34 is preferably 100 nm. In addition, each side gate 24 is formed at both ends of each quantum dot and the distance between each side gate 24 is formed to 100nm or more.
4A is a perspective view illustrating a state in which a second oxide film is formed in the single-electron tunneling inverter circuit according to the present invention, and FIG. 4B is a cross-sectional view of BB shown in FIG. 4A. As shown in FIGS. 4A and 4B, a second oxide film 40 made of a silicon oxide film is formed on the entire upper surface of the etched active region. Preferably, the second oxide film 40 is formed to a thickness of 5nm to 10nm over the entire substrate using a thermal oxidation process. At this time, as the second oxide film 40 is formed through the thermal oxidation process, the size of the quantum dot 32 is further reduced.
5A is a perspective view illustrating a state in which a polygate is formed in the single-electron tunneling inverter circuit according to the present invention, and FIG. 5B is a cross-sectional view of the CC illustrated in FIG. 5A. As shown in FIGS. 5A and 5B, the polygate 50 is formed on the front surface of the substrate using polysilicon. The polygate 50 is formed on the quantum dot 32, the tunneling junction 34, and the output terminal 36 to be used as a channel using photolithography with polysilicon. The polygate 50 is located adjacent to the quantum dots 32 and controls the current flowing through each quantum dot. Preferably, polysilicon has a polygate 50 having a thickness of 50 nm to 150 nm by low pressure chemical vapor deposition.
Source 22 and drain 20 are formed by ion implantation and doping into both channel regions of the polygate 50, and ion implantation and doping of the side gate 24 and output terminal 26 can be used as electrodes. Do it. In addition, the polygate 50 is also doped by the ion implantation process.
After ion implantation doping, a photoresist pattern is formed on the second oxide film 40.
6 is a perspective view illustrating a state in which a second oxide layer and a poly gate are etched in a single electron tunneling inverter circuit according to the present invention. As shown in FIG. 6, the second oxide film 40 is etched using photolithography to expose portions of the source 22, the drain 20, the side gate 24, and the output terminal 26. Form a contact hole. At this time, preferably, the second oxide film 40 is etched by wet etching. In addition, although the second oxide layer 40 does not exist in the polygate 50, a portion of the upper portion of the polygate 50 is etched to form a contact hole in order to deposit a metal layer.
FIG. 7A is a perspective view illustrating a pad formed by depositing a metal film in the single-electron tunneling inverter circuit according to the present invention, and FIG. 7B is a cross-sectional view of DD shown in FIG. 7A. As shown in FIGS. 7A and 7B, contact holes may be buried in an etched polygate 50, two side gates 24, an output terminal 26, a source 22, and a drain 20. The metal film 70 is deposited.
The deposited metal layer 70 is removed together with the photoresist pattern to simultaneously form pads of the source terminal, the drain terminal, the output terminal 26, the side gate 24, and the poly gate 50. Since the method of removing the metal film 70 and the photoresist pattern in the present invention is well known to those skilled in the art, a detailed description thereof will be omitted.
The second oxide film 40 is formed to a thickness of 5 nm to 10 nm by a thermal oxidation process, the polygate 50 is formed to a thickness of 50 nm to 150 nm, and the thickness of the metal film 70 is 200 nm to 500 nm by a thermal deposition process. It is formed to a thickness of.
That is, the single-electron tunneling inverter circuit manufactured as described above forms two single-electron transistors by electron beam lithography, and simultaneously manufactures the two single-electron transistors and the terminal for measuring the output voltage on the same plane. To improve.
According to embodiments of the present invention, electron beam lithography is used to simultaneously form the respective quantum dots 32, the side gates 24 and the output terminals 26 that change the phase of the quantum dots 32.
The polygate 50 according to the present invention applies the same voltage to each single-electron transistor as an input terminal. The side gate 50 is not operated to one single-electron transistor, and the other side gate is operated to the other single-electron transistor 50 to change the Coulomb vibration phase between each single-electron transistor by 180 degrees (out-of-phase). In this case, the logic circuit becomes a complementary single-electron tunneling inverter logic circuit. Using the points having complementary phases, the Coulomb vibrations through the single-electron transistors are arranged in phases with each other, and when the output voltage is changed with respect to the input voltage between the crossing vertices, the drain current Since the peak and the bottom of the in-coulomb vibration cross each other, the phase of the input voltage is also changed, thereby obtaining the phase of the output voltage opposite to that of the input voltage, thereby obtaining the characteristics of the single-electron tunneling inverter circuit.
Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

According to the present invention as described above, by changing the phase difference by the operation of the side gate of the SET according to the same input voltage, not the inverter logic element due to the phase change according to the ON / OFF of each SET gate as in the prior art One output voltage can be derived. In addition, compared to the conventional CMOS type inverter using two types of transistors, N-MOS and P-MOS, only the phase difference is used in the same transistor, thereby simplifying the manufacturing and shortening the manufacturing time. Terminals can be fabricated simultaneously using electron beam lithography to improve directness.
In addition, it can improve the functionality of single-electron logic circuits, achieve low power consumption, simplify the process, and shorten the process time, and drive two single-electron transistors using one input voltage to improve device integration and improve manufacturing costs. Can be reduced.
In addition, a basic inverter logic circuit can be configured by two single-electron transistors having side gates that can control the phase of a quantum dot using a pattern formed by electron beam lithography.

In addition, the present invention is not limited to the above embodiments and can be carried out in various modifications without departing from the technical gist of the present invention.

Claims (8)

Preparing an SOI substrate including a first silicon layer 10, a first oxide layer 11, and a second silicon layer 12 (S10); Etching the second silicon layer 12, which is a semiconductor layer, to form an active region including a drain 20, a source 22, at least one side gate 24, and an output terminal 26 (S20). ; Simultaneously forming a quantum dot (32), a tunneling junction (34), and an output terminal (36) on the same plane between the source (22) and the drain (20) in the active region; Forming a second oxide film 40 on an upper surface of the active region (S40); Forming a polygate (50) from polysilicon so that the quantum dot (32), the tunneling junction (34) and the output end (36) are included (S50); Implanting and doping impurity ions into the polygate (50), the side gate (24), the output terminal (26), the source (22) and the drain (20); Forming a photoresist pattern on the second oxide film 40 (S70); The polygate 50 and the second oxide layer 40 are exposed so that a portion of the polygate 50, the side gate 24, the output terminal 26, the source 22, and the drain 20 are exposed. Etching (S80); Depositing a metal film (70) on the etched polygate (50), the side gate (24), the output terminal (26), the source (22) and the drain (20); And Forming a pad by removing the photoresist (S100); Single electron tunneling inverter circuit manufacturing method comprising a. The method of claim 1, And the quantum dot, tunneling junction, side gate, and output stage forming step are simultaneously formed using electron beam lithography. The method of claim 1, In the second oxide film forming step (S40), the thickness of the second oxide film (40) is 5 ~ 10 nm, characterized in that the single electron tunneling inverter circuit manufacturing method. The method of claim 1, In the metal film deposition step (S90), the thickness of the metal film (70) is 200 ~ 500 nm, characterized in that the single electron tunneling inverter circuit manufacturing method. The method of claim 1, The active region forming step (S20) is a method of manufacturing a single electron tunneling inverter circuit, characterized in that formed by photolithography or reactive ion etching (RIE). The method of claim 1, In the forming of the polygate (S50), the polygate 50 is a single electron tunneling inverter circuit manufacturing method, characterized in that formed in a thickness of 50 ~ 150 nm by low pressure chemical vapor deposition. The method of claim 1, The poly gate and the second oxide layer etching step (S80) is a wet electron tunneling inverter circuit manufacturing method, characterized in that the wet etching. A single electron tunneling inverter circuit, which is manufactured by the manufacturing method according to any one of claims 1 to 7.

Images