KR20020087556A - Method of manufacturing a flash memory cell - Google Patents

Abstract

PURPOSE: A method of manufacturing a flash memory cell is provided to prevent a damage of an anti-reflection coating and to improve the electrical property and reliability of device. CONSTITUTION: A tunnel oxide layer(22) and a first polysilicon layer(23) for a floating gate are sequentially formed on a semiconductor substrate(21). A photoresist pattern is formed on the first polysilicon layer(23). The exposed regions of the tunnel oxide layer(22) and the first polysilicon layer(23) are removed by etching and a first patterning is performed to form the floating gate. A dielectric layer(24), a second polysilicon(25) for a controlling gate, a tungsten silicide layer(26), an anti-reflection coating are sequentially formed and a first photoresist pattern(28) as an etch mask is formed to form the control gate on the anti-reflection coating. As a result, the desired region of anti-reflection coating(27) is exposed.

Description

Method of manufacturing a flash memory cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and in particular, to form a gate of a memory cell, an antireflection film, a tungsten silicide layer, and a polysilicon layer for a control gate are patterned, followed by a poly-alignment film and a floating gate poly The present invention relates to a flash memory cell manufacturing method capable of preventing damage to an anti-reflection film and reducing a process step in the process of patterning a silicon layer.

Generally, the gate of a flash memory cell consists of a first polysilicon layer for a floating gate, a dielectric film, a second polysilicon layer for a control gate, a tungsten silicide layer and an antireflection film.

A manufacturing method of a conventional flash memory cell is described as follows.

Referring to FIG. 1A, after forming a field oxide film (not shown) in a predetermined region of the semiconductor substrate 11, the tunnel oxide film 12 and the first polysilicon layer 13 for floating gate are sequentially formed. After forming a photoresist pattern (not shown) on the first polysilicon layer 13, the exposed regions of the first polysilicon layer 13 and the tunnel oxide layer 12 are removed by an etching process to form a floating gate. First patterning is carried out. FIG. 1A is a cross-sectional view of a direction parallel to the direction in which the first polysilicon layer 13 is patterned, and thus the pattern in which the first polysilicon layer 13 is patterned does not appear.

Subsequently, the dielectric film 14, the second polysilicon layer 15 for the control gate, the tungsten silicide layer 16, and the antireflection film 17 are sequentially formed on the entire surface, and then the control gate is formed on the antireflection film 17. The photoresist pattern 18 is formed as an etching mask for forming a.

Referring to FIG. 1B, the exposed portions of the anti-reflection film 17, the tungsten silicide layer 16, and the second polysilicon layer 15 are removed by an etching process using the dielectric film 14 as an etch stop layer. Thereafter, the photoresist pattern 18 is removed.

Referring to FIG. 1C, the exposed portions of the dielectric film 14, the first polysilicon layer 13, and the tunnel oxide film 12 may be removed by a self-aligned etching process using the anti-reflection film 17 as a hard mask. Patterning is performed. When the tunnel oxide film 12 is removed to expose the surface of the semiconductor substrate 11, an impurity ion implantation process is performed to form the source / drain 19. In this way, a flash memory cell is manufactured.

The self-aligned etching process of the above process step uses the anti-reflection film 17 as a hard mask. In the self-aligned etching process using the anti-reflection film 17 as a hard mask, the etch damage occurs in the anti-reflection film 17, and in some cases, the etch damage A occurs up to the tungsten silicide layer 16.

For this reason, the electrical characteristics of an element may fall, and defects may arise.

Accordingly, in order to solve the above problems, the present invention is directed to solving the above problem, in which the photoresist pattern used in the patterning process of the anti-reflection film, the tungsten silicide layer and the polysilicon layer for the control gate is not removed, and the poly for the dielectric film of the memory cell and the floating gate poly The present invention relates to a flash memory cell manufacturing method capable of protecting an anti-reflective layer by a photoresist pattern to prevent etching damage of the anti-reflective layer and patterning the silicon layer, thereby improving process reliability.

1A to 1C are cross-sectional views of devices sequentially shown to explain a conventional flash memory cell manufacturing method.

2A through 2E are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory cell according to the present invention.

3A to 3C are cross-sectional views of devices sequentially shown to explain another embodiment of a method of manufacturing a flash memory cell according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21, 41: semiconductor substrate 12, 22, 42: tunnel oxide film

13, 23, 43: first polysilicon layer 14, 24, 44: dielectric film

15, 25, 45: second polysilicon layer 16, 26, 46: tungsten silicide layer

17, 27, 47: antireflection film 18, 48: photoresist pattern

28: first photoresist pattern 29: second photoresist pattern

19, 30, 49: source / drain A: anti-reflection film etching damage area

The flash memory cell manufacturing method according to the present invention provides a semiconductor substrate in which a dielectric film, a second polysilicon layer, a tungsten silicide layer, and an antireflection film are sequentially formed after the tunnel oxide film and the first polysilicon layer are patterned through a predetermined process. Forming a first photoresist pattern, and then patterning an anti-reflection film, a tungsten silicide layer, and a second polysilicon layer by an etching process to form a control gate, and performing a hard bake on the first photoresist pattern. Forming a floating gate by patterning a dielectric film, a first polysilicon layer, and a tunnel oxide film in an etching process using a second photoresist pattern, an etching process using the second photoresist pattern as an etching mask, and an impurity ion implantation process. Characterized in that the drain is formed.

According to another embodiment of the method of manufacturing a flash memory cell according to the present invention, a dielectric layer, a second polysilicon layer, a tungsten silicide layer, and an antireflection film are sequentially formed after the tunnel oxide film and the first polysilicon layer are patterned through a predetermined process. After the semiconductor substrate is formed and the photoresist pattern is formed, the anti-reflection film, the tungsten silicide layer, the second polysilicon layer, the dielectric film, the first polysilicon layer, and the tunnel oxide film are sequentially patterned by etching to form floating gates and controls. Forming a gate and forming a source and a drain by an impurity ion implantation process.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2A through 2E are cross-sectional views sequentially illustrating devices for describing a method of manufacturing a flash memory cell according to the present invention.

Referring to FIG. 2A, after forming a field oxide film (not shown) in a predetermined region of the semiconductor substrate 21, the tunnel oxide film 22 and the first polysilicon layer 23 for floating gate are sequentially formed. After forming a photoresist pattern (not shown) on the first polysilicon layer 23, the exposed regions of the first polysilicon layer 23 and the tunnel oxide layer 22 are removed by an etching process to form a floating gate. First patterning is carried out. 2A is a cross-sectional view of the same direction as the direction in which the first polysilicon layer 23 is patterned, and thus the pattern in which the first polysilicon layer 23 is patterned is not shown in FIG. 2A.

Subsequently, the dielectric film 24, the second polysilicon layer 25 for the control gate, the tungsten silicide layer 26, and the antireflection film 27 are sequentially formed on the entire surface, and then the control gate is formed on the antireflection film 27. The first photoresist pattern 28 is formed as an etching mask for forming a. As a result, only a predetermined region of the anti-reflection film 27 is exposed.

Referring to FIG. 2B, the exposed portions of the anti-reflection film 27, the tungsten silicide layer 26, and the second polysilicon layer 25 are removed by an etching process using the dielectric film 24 as an etch stop layer. In this case, etching damage occurs in the first photoresist pattern 27 by an etching process.

Referring to FIG. 2C, a hard bake is performed to compensate for etching damage generated in the first photoresist pattern 27 and then the second photoresist pattern 28 is formed on the first photoresist pattern 27. To form.

Referring to FIG. 2D, exposed portions of the dielectric film 24, the first polysilicon layer 23, and the tunnel oxide film 22 are formed by an etching process using the first and second photoresist patterns 27 and 28 as hard masks. The part is removed and secondary patterning is performed. Secondary patterning is performed to form a gate of the memory cell.

Referring to FIG. 2E, after the first and second photoresist patterns 28 and 29 are removed, the source / drain 30 may be removed by the impurity ion implantation process on the surface of the semiconductor substrate 21 exposed by removing the tunnel oxide layer 22. ). In this way, a flash memory cell is manufactured.

In the above process, by using the dielectric film 24 as an etch stop layer, the exposed portions of the anti-reflection film 27, the tungsten silicide layer 26 and the second polysilicon layer 25 are etched and then the photoresist pattern ( 27 and 28, the antireflection film 27 is etched by removing the exposed portions of the dielectric film 24, the first polysilicon layer 23 and the tunnel oxide film 22 to form a gate. This does not occur.

Another embodiment of the flash memory cell manufacturing method according to the present invention will be described below.

3A to 3C are cross-sectional views of devices sequentially shown to explain another embodiment of a method of manufacturing a flash memory cell according to the present invention.

Referring to FIG. 3A, after forming a field oxide film (not shown) in a predetermined region of the semiconductor substrate 41, the tunnel oxide film 42 and the first polysilicon layer 43 for floating gate are sequentially formed. After forming a photoresist pattern (not shown) on the first polysilicon layer 43, the exposed regions of the first polysilicon layer 43 and the tunnel oxide layer 42 are removed by an etching process to form a floating gate. First patterning is carried out. 2A is a cross-sectional view of the same direction as the direction in which the first polysilicon layer 43 is patterned, and thus the pattern in which the first polysilicon layer 43 is patterned is not shown in FIG. 2A.

Subsequently, the dielectric film 44, the second polysilicon layer 45 for the control gate, the tungsten silicide layer 46, and the antireflection film 47 are sequentially formed on the entire surface, and then the control gate is formed on the antireflection film 47. The photoresist pattern 48 is formed by using an etching mask to form a. As a result, only a predetermined region of the anti-reflection film 47 is exposed.

Referring to FIG. 3B, the anti-reflection film 47, the tungsten silicide layer 46, the second polysilicon layer 45, the dielectric film 44, the first polysilicon layer 43, and the tunnel oxide film 42 are etched in an etching process. Patterning is performed by removing the exposed part of As a result, a gate of the memory cell is formed.

Referring to FIG. 3C, after the photoresist pattern 48 is removed, the source / drain 49 may be formed on the exposed surface of the semiconductor substrate 41 by removing the photoresist pattern 48 by an impurity ion implantation process. In this way, a flash memory cell is manufactured.

Conventionally, by using a dielectric film as an etch stop layer, exposed portions of the anti-reflection film, the tungsten silicide layer and the second polysilicon layer are removed by an etching process, a photoresist pattern is removed, and a self-aligned etching process using the anti-reflection film as a hard mask. The gate oxide is formed by removing the exposed portions of the dielectric film, the first polysilicon layer and the tunnel oxide film. By sequentially etching to remove, it is possible to simplify the process and to prevent the etching damage to the anti-reflection film.

As described above, the present invention protects the anti-reflection film with the photoresist pattern during the self-aligned etching process, thereby preventing the etching damage from occurring in the anti-reflection film, thereby improving the reliability of the process, the electrical characteristics of the device, and minimizing the defects. .

Claims (2)

Providing a semiconductor substrate in which a dielectric film, a second polysilicon layer, a tungsten silicide layer, and an anti-reflection film are sequentially formed after the tunnel oxide film and the first polysilicon layer are patterned through a predetermined process; Forming a control gate by patterning the anti-reflection film, the tungsten silicide layer, and the second polysilicon layer by an etching process after forming a first photoresist pattern; Forming a second photoresist pattern on the first photoresist after hard baking; Forming a floating gate by patterning the dielectric layer, the first polysilicon layer, and the tunnel oxide layer in an etching process using the second photoresist pattern as an etching mask; A method of manufacturing a flash memory cell, comprising forming a source and a drain by an impurity ion implantation process. Providing a semiconductor substrate in which a dielectric film, a second polysilicon layer, a tungsten silicide layer, and an anti-reflection film are sequentially formed after the tunnel oxide film and the first polysilicon layer are patterned through a predetermined process; After forming the photoresist pattern, the anti-reflection film, the tungsten silicide layer, the second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer are sequentially patterned to form a floating gate and a control gate. Forming a and Forming a source and a drain by an impurity ion implantation process.