KR20020084879A - Method of Fabricating Semiconductor Device Using Ultraviolet Rays Exposure Technique - Google Patents
Method of Fabricating Semiconductor Device Using Ultraviolet Rays Exposure Technique Download PDFInfo
- Publication number
- KR20020084879A KR20020084879A KR1020010024340A KR20010024340A KR20020084879A KR 20020084879 A KR20020084879 A KR 20020084879A KR 1020010024340 A KR1020010024340 A KR 1020010024340A KR 20010024340 A KR20010024340 A KR 20010024340A KR 20020084879 A KR20020084879 A KR 20020084879A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- trench
- forming
- film
- pattern
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title description 11
- 238000007687 exposure technique Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000001678 irradiating effect Effects 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract 2
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 21
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 자외선 조사 기술을 사용한 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using ultraviolet irradiation technology.
반도체 장치의 제조에 있어서, 플라즈마 건식 식각의 방법이 사용된다. 상기 플라즈마 건식식각의 방법은 이온 상태의 원자핵에 전계를 인가하여 가속시킨 후, 물질막의 표면에 충돌시킴으로써 상기 물질막을 식각하는 방법이다. 그런데 상기 플라즈마 식각은 식각된 물질막에 트랩된 전하를 발생시키는 문제를 갖는다.In the manufacture of semiconductor devices, a method of plasma dry etching is used. The plasma dry etching is a method of etching the material film by applying an electric field to an atomic nucleus in an ionic state and then accelerating the surface of the material film. However, the plasma etching has a problem of generating charge trapped in the etched material layer.
상기 물질막에 트랩된 전하는 불필요한 전기장을 형성하여, 소자의 불안정한 전기적 특성을 유발한다.Charges trapped in the material film create an unnecessary electric field, causing unstable electrical properties of the device.
본 발명이 이루고자 하는 기술적 과제는 플라즈마 식각 후 발생하는 전하 트랩의 문제점을 해결하는 반도체 장치의 제조 방법을 제공하는 데 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device that solves the problem of the charge trap generated after plasma etching.
도 1은 본 발명에 따른 반도체 장치의 제조방법을 설명하기 위한 공정 흐름도이다.1 is a flowchart illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2 내지 도 4는 본 발명의 바람직한 실시예에 따른 반도체장치의 제조방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
상기한 기술적 과제를 달성하기 위하여, 본 발명은 전하가 트랩된 물질막에 대해 자외선을 조사하는 반도체장치의 제조 방법을 제공한다. 이 방법은 반도체기판 상에 물질막을 형성하고, 상기 물질막을 플라즈마 건식식각의 방법으로 식각한 후, 상기 식각된 물질막을 포함하는 반도체기판을 자외선으로 조사하는 단계를 포함한다.In order to achieve the above technical problem, the present invention provides a method of manufacturing a semiconductor device for irradiating ultraviolet rays to the material film trapped charge. The method includes forming a material film on the semiconductor substrate, etching the material film by a plasma dry etching method, and then irradiating the semiconductor substrate including the etched material film with ultraviolet rays.
이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 여기서 설명되어지는 실시예에 한정되지 않고 다른 형태로 구체화될 수도 있다. 오히려, 여기서 소개되는 실시예는 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이다. 또한 층이 다른 층 또는 기판 상에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나 또는 그들 사이에 제 3의 층이 개재될 수도 있다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.
도 1은 본 발명에 따른 반도체 장치의 제조방법을 설명하기 위한 공정 흐름도이다.1 is a flowchart illustrating a method of manufacturing a semiconductor device according to the present invention.
도 1을 참조하면, 반도체기판 상에 물질막을 형성한다(10). 상기 물질막을플라즈마 건식식각의 방법으로 식각한다(20). 상기 식각된 물질막을 포함하는 반도체기판에 자외선을 조사한다(30).Referring to FIG. 1, a material film is formed on a semiconductor substrate (10). The material film is etched by the plasma dry etching method (20). Ultraviolet rays are irradiated to the semiconductor substrate including the etched material layer (30).
상기 물질막을 형성하는 단계와 상기 플라즈마 건식식각의 단계 사이에는 상기 물질막 상에 포토레지스트 패턴을 형성하는 단계가 더 포함될 수도 있다.The method may further include forming a photoresist pattern on the material film between the forming of the material film and the plasma dry etching step.
도 2 내지 도 4는 본 발명의 바람직한 실시예에 따른 반도체장치의 제조방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
도 2를 참조하면, 반도체기판(100) 상에 차례로 적층된 패드산화막 및 실리콘질화막을 형성한다. 그 후, 상기 실리콘질화막을 패터닝하여 트렌치마스크 패턴(120)을 형성한다. 상기 트렌치마스크 패턴(120)을 식각 마스크로 사용하여 상기 패드산화막 및 상기 반도체기판(100)을 차례로 식각함으로써, 패드산화막 패턴(110) 및 트렌치(130) 영역을 형성한다.Referring to FIG. 2, a pad oxide film and a silicon nitride film that are sequentially stacked on the semiconductor substrate 100 are formed. Thereafter, the silicon nitride film is patterned to form a trench mask pattern 120. The pad oxide film pattern and the semiconductor substrate 100 are sequentially etched using the trench mask pattern 120 as an etch mask, thereby forming regions of the pad oxide film pattern 110 and the trench 130.
상기 트렌치(130) 영역 형성을 위한 식각 공정은 이방성 식각이 바람직하다. 이때, 상기 이방성 식각에 의해 발생하는 트렌치 내벽의 손상을 치유하기 위해, 상기 트렌치 내벽에 열산화막(140)을 더 형성해주는 열공정을 실시하는 것이 바람직하다.The etching process for forming the trench 130 region is preferably anisotropic etching. In this case, in order to cure damage to the inner wall of the trench generated by the anisotropic etching, it is preferable to perform a thermal process of further forming a thermal oxide film 140 on the inner wall of the trench.
그런데, 상기 트렌치(130) 영역 및 상기 트렌치 마스크 패턴(120)에 의해 둘러싸이는 영역은 통상의 소자분리막 매립 기술로 매립하기에는 어려운 정도의 큰 종횡비를 갖는다. 이를 해결하기 위한 방법에는 매립특성이 좋은 물질막을 증착한 후, 전면식각하여 상기 트렌치 영역의 하부에만 잔존하게 함으로써, 매립해야할 영역의 종횡비를 감소시키는 방법이 있다.However, the region surrounded by the trench 130 and the trench mask pattern 120 has a large aspect ratio that is difficult to fill by the conventional device isolation technology. In order to solve this problem, there is a method of reducing the aspect ratio of the region to be filled by depositing a material film having good embedding characteristics and then etching the entire surface and remaining only in the lower portion of the trench region.
도 3을 참조하면, 상기 열산화막(140)이 형성된 반도체기판 전면에 다결정실리콘막을 형성한다. CVD 방식에 의해 형성되는 상기 다결정실리콘막은 우수한 스텝커버리지(step coverage) 특성으로 인해, 상기 트렌치(130) 영역을 공극없이 채울 수 있다.Referring to FIG. 3, a polysilicon film is formed on the entire surface of the semiconductor substrate on which the thermal oxide film 140 is formed. The polysilicon film formed by the CVD method may fill the trench 130 without voids due to excellent step coverage characteristics.
상기 다결정실리콘막을 플라즈마 건식식각의 방법으로 전면식각하여, 상기 트렌치(130) 영역에 잔존하는 하부 소자분리막 패턴(150)을 형성한다. 상기 하부 소자분리막 패턴(150)은 상기 반도체기판(100)의 상부면보다 낮은 것을 특징으로 한다.The polysilicon layer is etched entirely by plasma dry etching to form a lower device isolation layer pattern 150 remaining in the trench 130. The lower device isolation layer pattern 150 is lower than the upper surface of the semiconductor substrate 100.
상기 플라즈마 건식식각에 의해 상기 하부소자분리막 패턴(150)에는 이온들이 트랩된다. 상기 트랩된 이온들에 의해 발생한 전기장은 소자의 문턱전압의 변화 또는 문턱전압의 넓은 분포 특성을 갖게하는 등의 문제점을 유발한다. 이와 같은 문제점이 발생하는 것을 방지하기 위해, 상기 플라즈마 건식식각 후, 식각된 반도체기판에 대하여 자외선(155)을 조사한다. 상기 자외선(155)을 조사시키면 하부소자분리막 패턴(150) 내에 트랩된 전하들은 반도체기판(100)으로 이동한다. 상기 자외선(155)은 단위 시간 및 단위 면적당 10 ~ 50 ㎽/㎠의 에너지로 1000 ~ 5000초간 조사되는 것이 바람직하다.Ions are trapped in the lower device isolation layer pattern 150 by the plasma dry etching. The electric field generated by the trapped ions causes problems such as a change in the threshold voltage of the device or a wide distribution characteristic of the threshold voltage. In order to prevent such a problem from occurring, ultraviolet light 155 is irradiated to the etched semiconductor substrate after the plasma dry etching. When the ultraviolet light 155 is irradiated, charges trapped in the lower device isolation layer pattern 150 move to the semiconductor substrate 100. The ultraviolet ray 155 is preferably irradiated for 1000 to 5000 seconds at an energy of 10 to 50 mW / cm 2 per unit time and unit area.
도 4를 참조하면, 상기 자외선(155) 조사가 끝난 반도체기판 전면에 소자분리 산화막을 형성한다. 상기 소자분리 산화막을 전면 식각하여 상기 트렌치마스크 패턴(120)을 노출시킴으로써 상부 소자분리막 패턴(160)을 형성한 후, 상기 트렌치마스크 패턴(120) 및 상기 패드산화막 패턴(110)을 차례로 제거한다.Referring to FIG. 4, a device isolation oxide film is formed on the entire surface of the semiconductor substrate where the ultraviolet rays 155 are irradiated. After etching the entire device isolation oxide layer to expose the trench mask pattern 120, the upper device isolation layer pattern 160 is formed, and then the trench mask pattern 120 and the pad oxide layer pattern 110 are sequentially removed.
상기 하부 소자분리막 패턴(150)에 의해 상기 트렌치(130) 영역의 일부가 채워짐에 따라, 매립해야할 영역의 종횡비는 감소한다. 따라서, 통상의 CVD 방법에 의해서도 상기 소자분리 산화막은 상기 하부 소자분리막 패턴(150) 상부의 트렌치(130) 영역을 쉽게 매립할 수 있다. 또한 상기 상부 소자분리막 패턴(160)은 다결정실리콘으로 이루어진 상기 하부 소자분리막 패턴(150)을 열산화시켜서 형성할 수도 있다.As a portion of the trench 130 is filled by the lower device isolation layer pattern 150, the aspect ratio of the region to be buried decreases. Therefore, the device isolation oxide layer may easily fill the trench 130 region on the lower device isolation layer pattern 150 even by a conventional CVD method. In addition, the upper device isolation layer pattern 160 may be formed by thermally oxidizing the lower device isolation layer pattern 150 made of polycrystalline silicon.
상기 하부소자분리막 패턴(150)은 비록 다결정실리콘으로 형성될지라도, 상기 상부 소자분리막 패턴(160) 및 열산화막(140)에 의해 둘러싸여서 전기적으로 절연된다. 이것은 플래쉬 메모리의 부유게이트와 같은 상태이다. 즉, 상기 자외선(155) 조사의 단계가 없다면, 상기 하부 소자분리막 패턴(150) 내에 트랩된 전하는 계속 잔존하여 소자 특성에 악영향을 미치게된다.Although the lower device isolation layer pattern 150 is formed of polycrystalline silicon, the lower device isolation layer pattern 150 is surrounded by the upper device isolation layer pattern 160 and the thermal oxide layer 140 to be electrically insulated. This is the same state as the floating gate of the flash memory. That is, if there is no step of irradiating the ultraviolet light 155, the charge trapped in the lower device isolation layer pattern 150 remains and thus adversely affects device characteristics.
본 발명은 플라즈마 건식식각의 방법으로 식각된 물질막에 대해, 자외선을 조사하는 반도체 장치의 제조방법을 제공한다. 그 결과, 플라즈마 건식식각에 의해 물질막에 전하가 트랩됨으로써 발생하는 소자특성 악화의 문제를 해결한다.The present invention provides a method of manufacturing a semiconductor device that irradiates ultraviolet rays to a material film etched by a plasma dry etching method. As a result, the problem of deterioration of device characteristics caused by trapping charge on the material film by plasma dry etching is solved.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010024340A KR20020084879A (en) | 2001-05-04 | 2001-05-04 | Method of Fabricating Semiconductor Device Using Ultraviolet Rays Exposure Technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010024340A KR20020084879A (en) | 2001-05-04 | 2001-05-04 | Method of Fabricating Semiconductor Device Using Ultraviolet Rays Exposure Technique |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020084879A true KR20020084879A (en) | 2002-11-13 |
Family
ID=27703713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010024340A KR20020084879A (en) | 2001-05-04 | 2001-05-04 | Method of Fabricating Semiconductor Device Using Ultraviolet Rays Exposure Technique |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020084879A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8058187B2 (en) | 2009-01-05 | 2011-11-15 | Samsung Electronics Co., Ltd. | Trap charge equalizing method and threshold voltage distribution reducing method |
| CN111785631A (en) * | 2019-04-03 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
-
2001
- 2001-05-04 KR KR1020010024340A patent/KR20020084879A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8058187B2 (en) | 2009-01-05 | 2011-11-15 | Samsung Electronics Co., Ltd. | Trap charge equalizing method and threshold voltage distribution reducing method |
| CN111785631A (en) * | 2019-04-03 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN111785631B (en) * | 2019-04-03 | 2023-10-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100729911B1 (en) | Method of manufacturing a semiconductor device | |
| KR100845103B1 (en) | Method of fabricating the semiconductor device | |
| KR101098062B1 (en) | Method of forming a semiconductor device | |
| JP2000049112A (en) | Formation of self-alignment contact of semiconductor device | |
| KR20040080551A (en) | Semiconductor device having layer for absorbing photon and method for manufacturing the same | |
| JP2005101602A (en) | High-breakdown voltage field-effect transistor and method of forming the same | |
| KR20020084879A (en) | Method of Fabricating Semiconductor Device Using Ultraviolet Rays Exposure Technique | |
| KR20070053842A (en) | Method of fabricating the trench isolation for the semiconductor device | |
| KR100480236B1 (en) | Method for manufacturing semiconductor device | |
| JPH1022270A (en) | Manufacture of semiconductor device | |
| KR100226739B1 (en) | Method of manufacturing a semiconductor device | |
| KR100670748B1 (en) | Method for fabricating the same of semiconductor device with recess gate | |
| KR100649321B1 (en) | Method of fabricating the flash memory device | |
| KR100403317B1 (en) | Manufacturing method for semiconductor device | |
| KR100835471B1 (en) | manufacturing method of semiconductor device | |
| KR100425998B1 (en) | shallow trench isolation forming method of silicon substrate | |
| KR100761647B1 (en) | Method of manufacturing a flash memory cell | |
| KR100261328B1 (en) | Method of forming contact hole in semiconductor device | |
| KR100842507B1 (en) | Method for manufacturing device isolation layer of semiconductor device | |
| KR100345515B1 (en) | a manufacturing method of a semiconductor device | |
| KR100773673B1 (en) | Method of manufacturing a flash memory device | |
| KR100885287B1 (en) | Method for forming the semiconductor device | |
| KR101159721B1 (en) | Method for forming semiconductor device | |
| KR100678320B1 (en) | Mathode of manufacturing semiconductor device | |
| KR20060134320A (en) | Trench isolation layer and method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |