KR20020082395A - Land grid array type semiconductor device and method of mounting the same - Google Patents

Land grid array type semiconductor device and method of mounting the same Download PDF

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Publication number
KR20020082395A
KR20020082395A KR1020010080426A KR20010080426A KR20020082395A KR 20020082395 A KR20020082395 A KR 20020082395A KR 1020010080426 A KR1020010080426 A KR 1020010080426A KR 20010080426 A KR20010080426 A KR 20010080426A KR 20020082395 A KR20020082395 A KR 20020082395A
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South Korea
Prior art keywords
external electrode
semiconductor device
substrate
pad
grid array
Prior art date
Application number
KR1020010080426A
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Korean (ko)
Other versions
KR100457029B1 (en
Inventor
오카다마키오
카사타니야스시
하시모토토모아키
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미쓰비시덴키 가부시키가이샤
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Publication of KR20020082395A publication Critical patent/KR20020082395A/en
Application granted granted Critical
Publication of KR100457029B1 publication Critical patent/KR100457029B1/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE: To provide a land grid array semiconductor device which is reformed to improve the positioning accuracy of the external electrode of a mounting board. CONSTITUTION: An external electrode 11 is arranged in an area array form on one side of the board 2. The external electrode 11 includes an external electrode pad 11a and a external electrode wire 6. The external electrode pad 11a includes a first pad layer 12 made in a columnar form, and a second pad layer 13 made conically to cover the surface of the first pad layer 12.

Description

랜드 그리드 어레이형 반도체장치 및 그의 실장방법{LAND GRID ARRAY TYPE SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING THE SAME}LAND GRID ARRAY TYPE SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING THE SAME}

본 발명은, 일반적으로, 랜드 그리드 어레이형 반도체장치에 관한 것으로, 보다 특정적으로는, 실장기판측의 전극부에 대한 실장시의 위치결정 정밀도의 향상과, 그것에 따른 실장후의 실장기판과의 접합 신뢰성을 향상시킬 수 있도록 개량된 랜드 그리드 어레이형 반도체장치에 관한 것이다. 본 발명은, 또한, 그와 같은 랜드 그리드 어레이형 반도체장치의 실장방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to land grid array semiconductor devices, and more particularly, to improve the positioning accuracy at the time of mounting to the electrode portion on the mounting substrate side, and thereby to join the mounting substrate after mounting. The present invention relates to a land grid array type semiconductor device improved to improve reliability. The present invention also relates to a method of mounting such a land grid array semiconductor device.

도 9는 종래의 랜드 그레이 어레이형 반도체장치의 단면도이고, 도 10은 그것의 저면도이다.9 is a sectional view of a conventional land gray array type semiconductor device, and FIG. 10 is a bottom view thereof.

이들 도면을 참조하면, 반도체장치(7)는 기판(2)을 구비한다. 기판(2)의 한쪽 면에 외부전극(3)이 설치되고, 기판(2)의 다른쪽 면에 글래스 에폭시 수지 등의재료로 형성된 반도체 소자 등을 봉지하는 봉지부(1)가 설치되어 있다. 기판(2)의 표면 및 내부에는, 반도체 소자와 전기적, 물리적인 접합을 형성하는 구리 등으로 구성된 전극배선이 형성되어 있다. 외부전극(3)은, 도시된 것과 같이, 기판(2)의 봉지부(1)와 대향하는 다른쪽측의 표면에 노출되어 있다. 외부전극(3)은, 실장기판과 전기적, 물리적인 접합을 형성하는 구리 등으로 구성되어 있다.Referring to these drawings, the semiconductor device 7 includes a substrate 2. An external electrode 3 is provided on one side of the substrate 2, and an encapsulation portion 1 for encapsulating a semiconductor element or the like formed of a material such as glass epoxy resin is provided on the other side of the substrate 2. On the surface and inside of the substrate 2, electrode wirings made of copper or the like which form electrical and physical junctions with the semiconductor elements are formed. The external electrode 3 is exposed to the surface of the other side which opposes the sealing part 1 of the board | substrate 2 as shown. The external electrode 3 is made of copper or the like which forms an electrical and physical junction with the mounting substrate.

외부전극(3)은, 원주 형태로 표면이 평활한 외부 전극패드(4)와, 기판(2)의 내부에서 스루홀(5)을 거쳐 외부로 인출된 외부 전극배선(6)으로 구성된다. 외부전극(3)은, 기판의 봉지부(1)와 대향하는 측에, 격자 형태로, 즉 에리어 어레이(area array) 형태로 배치되어 있다.The external electrode 3 is composed of an external electrode pad 4 having a circumferentially smooth surface and an external electrode wiring 6 drawn out through the through hole 5 from the inside of the substrate 2. The external electrodes 3 are arranged in a lattice form, that is, in an area array form, on the side opposite to the encapsulation portion 1 of the substrate.

외부전극(3)이 평면 내에서 격자 형태로 배치되어 있기 때문에, 전극간 피치가 넓어도, 부품면적당의 전극수는 더욱 많이 확보할 수 있는 점에서, 구조상 유리한 구조로 되어 있다.Since the external electrodes 3 are arranged in a lattice form in a plane, even if the pitch between electrodes is wide, the number of electrodes per component area can be ensured more, which is a structurally advantageous structure.

다음에, 종래의 랜드 그리드 어레이형 반도체장치의 동작에 대해 설명한다.Next, the operation of the conventional land grid array semiconductor device will be described.

도 11을 참조하면, 여기에서는, 반도체장치(7)를 실장기판(8)에 실장하는 동작에 대해 설명한다. 실장기판(8)은 글래스 에폭시 수지 등의 재료로 구성된다. 실장기판(8)의 표면에는, 도시하지 않았지만, 반도체장치(7)와 전기적, 물리적인 접합을 형성하는 구리 등으로 구성된 전극배선이 설치되어 있다. 기판 외부전극(9)은, 실장기판(8)의 표면에 노출되어 있으며, 반도체장치(7)와 전기적, 물리적인 접합을 형성하는 구리 등으로 구성되어 있다. 기판 외부전극(9)은, 실장기판(8)의 표면 상에 있어서, 반도체장치(7)의 외부전극(3)과 대향하는 위치에, 에리어 어레이형태로 배치된다. 접합매체(10)는, 땜납 페이스트 등으로 구성되어, 기판 외부전극(9)의 위에, 인쇄법, 디스펜스법 등에 의해 인쇄, 도포된다.Referring to FIG. 11, an operation of mounting the semiconductor device 7 on the mounting substrate 8 will be described. The mounting substrate 8 is made of a material such as glass epoxy resin. Although not shown, an electrode wiring made of copper or the like for forming an electrical and physical junction with the semiconductor device 7 is provided on the surface of the mounting substrate 8. The substrate external electrode 9 is exposed on the surface of the mounting substrate 8 and is made of copper or the like which forms an electrical and physical junction with the semiconductor device 7. The substrate external electrodes 9 are arranged on the surface of the mounting substrate 8 in an area array form at positions facing the external electrodes 3 of the semiconductor device 7. The bonding medium 10 is made of solder paste or the like, and is printed and applied onto the substrate external electrode 9 by a printing method, a dispensing method, or the like.

종래의 반도체장치(7)의 실장 동작은 다음과 같다. 즉, 미리 접합매체(10)를 실장기판(8)의 기판 외부전극(9)에 인쇄, 도포한다. 그 상태에서, 반도체장치(7)를 실장기판(8) 위에 탑재한다. 다음에, 반도체장치(7)의 외부 전극패드(4)를 접합매체(10)에 눌러, 이들을 고착시킨다. 더구나, 반도체장치(7)가 탑재된 상태의 실장기판(8)을 접합매체(10)의 융점 이상의 온도에서 리플로우한다. 이것에 의해, 접합매체(10)가 용융하여, 반도체장치(7)와 실장기판(8)이 전기적, 물리적으로 접합된다.The mounting operation of the conventional semiconductor device 7 is as follows. That is, the bonding medium 10 is printed and coated on the substrate external electrode 9 of the mounting substrate 8 in advance. In this state, the semiconductor device 7 is mounted on the mounting substrate 8. Next, the external electrode pad 4 of the semiconductor device 7 is pressed against the bonding medium 10 to fix them. In addition, the mounting substrate 8 with the semiconductor device 7 mounted thereon is reflowed at a temperature equal to or higher than the melting point of the bonding medium 10. As a result, the bonding medium 10 is melted, and the semiconductor device 7 and the mounting substrate 8 are electrically and physically bonded to each other.

종래의 반도체장치는 이상과 같이 구성되어 있기 때문에, 도 11을 참조하여, 실장기판(8) 위에 반도체장치(7)를 탑재할 때에, 접합매체(10)의 공급량의 변동 및 반도체장치(7)의 휘어짐에 의한 실장 높이의 변동 등에 의해, 외부 전극패드(4)와 접합매체(10)가 충분히 고착되지 않아, 리플로우 후에, 전부 또는 일부의 외부 전극패드(4)가 기판 외부전극(9)과 접합되지 않는다는 문제점이 있었다.Since the conventional semiconductor device is configured as described above, when the semiconductor device 7 is mounted on the mounting substrate 8 with reference to FIG. 11, the supply amount of the bonding medium 10 and the semiconductor device 7 are changed. The external electrode pad 4 and the bonding medium 10 do not sufficiently adhere to each other due to a change in the mounting height due to the bending of the substrate. Thus, after reflow, all or part of the external electrode pad 4 is exposed to the substrate external electrode 9. There was a problem that it is not bonded with.

본 발명은 상기한 것과 같은 문제점을 해결하기 위해 이루어진 것으로, 기판 실장시에 있어서, 실장기판과 반도체장치의 위치결정 정밀도의 향상을 도모할 수 있도록 개량된, 랜드 그리드 어레이형 반도체장치를 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and provides a land grid array type semiconductor device, which is improved so that the positioning accuracy of the mounting substrate and the semiconductor device can be improved during substrate mounting. The purpose.

본 발명의 또 다른 목적은, 실장후에 있어서, 실장기판과 반도체장치의 접합신뢰성을 향상시킬 수 있도록 개량된, 랜드 그리드 어레이형 반도체장치를 제공함에 있다.It is still another object of the present invention to provide a land grid array type semiconductor device which is improved to improve the bonding reliability of the mounting substrate and the semiconductor device after mounting.

본 발명의 또 다른 목적은, 그와 같은 랜드 그리드 어레이형 반도체장치의 실장방법을 제공함에 있다.Another object of the present invention is to provide a method of mounting such a land grid array semiconductor device.

도 1은 실시예 1에 관한 랜드 그리드 어레이형 반도체장치의 단면도이고,1 is a sectional view of a land grid array semiconductor device according to Embodiment 1,

도 2는 실시예 1에 관한 랜드 그리드 어레이형 반도체장치의 저면도이며,Fig. 2 is a bottom view of the land grid array semiconductor device according to the first embodiment,

도 3은 실시예 1에 관한 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태의 단면도이고,3 is a cross-sectional view of a state in which the land grid array semiconductor device according to the first embodiment is mounted on a mounting substrate,

도 4는 실시예 2에 관한 랜드 그리드 어레이형 반도체장치의 단면도이며,4 is a cross-sectional view of the land grid array semiconductor device according to the second embodiment;

도 5는 실시예 2에 관한 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태의 단면도이고,Fig. 5 is a sectional view of a state in which the land grid array semiconductor device according to the second embodiment is mounted on a mounting substrate.

도 6은 실시예 3에 관한 랜드 그리드 어레이형 반도체장치의 단면도이며,6 is a sectional view of a land grid array type semiconductor device according to the third embodiment;

도 7은 실시예 3에 관한 랜드 그리드 어레이형 반도체장치의 저면도이고,7 is a bottom view of the land grid array semiconductor device according to the third embodiment,

도 8은 실시예 3에 관한 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태를 나타낸 단면도이며,8 is a sectional view showing a state in which the land grid array semiconductor device according to the third embodiment is mounted on a mounting substrate,

도 9는 종래의 랜드 그리드 어레이형 반도체장치의 단면도이고,9 is a cross-sectional view of a conventional land grid array semiconductor device,

도 10은 종래의 랜드 그리드 어레이형 반도체장치의 저면도이며,10 is a bottom view of a conventional land grid array type semiconductor device,

도 11은 종래의 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태를 나타낸 단면도이다.11 is a cross-sectional view showing a state in which a conventional land grid array type semiconductor device is mounted on a mounting substrate.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1: 봉지부2: 기판1: Encapsulation Part 2: Substrate

5: 스루홀6: 외부 전극배선5: Through Hole 6: External Electrode Wiring

12: 외부 전극패드의 제 1 패드층12: first pad layer of the external electrode pad

13: 외부 전극패드의 제 2 패드층13: second pad layer of the external electrode pad

14: 접합매체14: bonding medium

본 발명의 제 1 국면에 따른 랜드 그리드 어레이형 반도체장치는, 에리어 어레이 형태로 외부전극이 배치되어 있다. 상기 외부전극은, 외부 전극패드와, 상기 기판의 내부로부터 스루홀을 거쳐 외부로 인출된 외부 전극배선을 포함한다. 상기 외부 전극패드는, 원주 형태 또는 각주 형태로 형성된 제 1 패드층과, 이 제 1 패드층의 표면을 덮도록 설치되고, 원추 형태 또는 각추 형태로 형성된 제 2 패드층을 포함한다.In the land grid array semiconductor device according to the first aspect of the present invention, external electrodes are arranged in an area array form. The external electrode includes an external electrode pad and an external electrode wiring drawn out from the inside of the substrate through a through hole. The external electrode pad includes a first pad layer formed in a circumferential form or a foot form, and a second pad layer formed to cover the surface of the first pad layer and formed in a conical form or a pyramidal form.

본 발명의 바람직한 실시예에 따르면, 상기 제 2 패드층의 표면에는, 오목부가 형성되어 있다.According to a preferred embodiment of the present invention, a recess is formed on the surface of the second pad layer.

본 발명의 더욱 바람직한 실시예에 따르면, 상기 오목부는, 원추 형태 또는 각추 형태로 형성된 요홈이다.According to a further preferred embodiment of the present invention, the recess is a recess formed in the form of a cone or a pyramid.

본 발명의 더욱 바람직한 실시예에 따르면, 상기 기판의 한쪽의 면에는, 상기 외부 전극패드와는 다른 형상을 갖고, 이 외부 전극패드와 전기적으로 물리적으로 도통하고 있지 않은 더미전극이 더 설치되어 있다.According to a further preferred embodiment of the present invention, one side of the substrate is further provided with a dummy electrode having a shape different from the external electrode pad and not electrically connected to the external electrode pad.

본 발명의 더욱 바람직한 실시예에 따르면, 상기 더미전극은, 원주 형태 또는 각주 형태로 형성된 제 1 층과, 이 제 1 층의 표면을 덮도록 설치되고, 원추 형태 또는 각추 형태로 형성된 제 2 층을 포함한다.According to a more preferred embodiment of the present invention, the dummy electrode is provided with a first layer formed in the form of a column or a foot, and a second layer formed to cover the surface of the first layer and formed in the form of a cone or a pyramid. Include.

본 발명의 제 2 국면에 따른 랜드 그리드 어레이형 반도체장치의 제조방법에 있어서는, 우선, 기판과, 상기 기판의 한쪽 면에, 에리어 어레이 형태로 배치된 외부전극을 구비하고, 상기 외부전극은, 외부 전극패드와, 상기 기판의 내부로부터 스루홀을 거쳐 외부로 인출된 외부 전극배선을 포함하며, 상기 외부 전극패드는, 원주 형태 또는 각주 형태로 형성된 제 1 패드층과, 이 제 1 패드층의 표면을 덮도록 설치되고, 원추 형태 또는 각추 형태로 형성된 제 2 패드층을 포함하는 랜드 그리드 어레이형 반도체장치를 준비한다. 기판 외부전극과, 이 기판 외부전극의 표면을 덮도록 설치된 접합매체를 갖는 실장기판을 준비한다. 상기 랜드 그리드 어레이형 반도체장치의 상기 제 2 패드층을 상기 실장기판의 상기 접합매체에 눌러넣어, 상기 실장기판에 상기 랜드 그리드 어레이형 반도체장치를 고착시킨다. 상기 랜드 그리드 어레이형 반도체장치가 탑재된 상기 실장기판을 상기 접합매체의 융점 이상의 온도로 어닐링한다.In the method for manufacturing a land grid array semiconductor device according to the second aspect of the present invention, first, a substrate and an external electrode arranged in an area array form on one surface of the substrate are provided. An electrode pad and an external electrode wiring drawn out from the inside of the substrate through a through hole, wherein the external electrode pad includes a first pad layer formed in a circumferential form or a footnote form, and the surface of the first pad layer. A land grid array type semiconductor device is installed to cover the gap, and includes a second pad layer formed in a cone shape or a pyramidal shape. A mounting substrate having a substrate external electrode and a bonding medium provided to cover the surface of the substrate external electrode is prepared. The second pad layer of the land grid array semiconductor device is pressed into the bonding medium of the mounting substrate to fix the land grid array semiconductor device to the mounting substrate. The mounting substrate on which the land grid array semiconductor device is mounted is annealed at a temperature equal to or higher than the melting point of the bonding medium.

본 발명의 바람직한 실시예에 따르면, 상기 제 2 패드층의 표면에는, 오목부가 형성되어 있다.According to a preferred embodiment of the present invention, a recess is formed on the surface of the second pad layer.

본 발명의 더욱 바람직한 실시예에 따르면, 상기 오목부는, 원추 형태 또는 각추 형태로 형성된 요홈이다.According to a further preferred embodiment of the present invention, the recess is a recess formed in the form of a cone or a pyramid.

[실시예]EXAMPLE

이하, 본 발명의 실시예를 도면을 참조하여 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the drawings.

실시예 1:Example 1:

도 1은 본 실시예에 관한 랜드 그리드 어레이형 반도체장치의 단면도이고, 도 2는 그것의 하측 방향에서 본 저면도이다. 이때, 상기한 종래예와 동일한 부분에는, 동일한 도면부호를 붙여, 그것의 설명을 반복하지 않는다.1 is a cross-sectional view of a land grid array semiconductor device according to the present embodiment, and FIG. 2 is a bottom view seen from the lower direction thereof. At this time, the same reference numerals are given to the same parts as the above-described conventional examples, and the description thereof will not be repeated.

이들 도면을 참조하면, 반도체장치(15)는 기판(2)을 구비한다. 외부전극(11)은, 기판(2)의 봉지부(1)와 대향하는 측의 표면에 노출되어 있다. 외부전극(11)은, 실장기판과 전기적, 물리적인 접합을 형성하기 위한 것이다. 외부전극(11)은, 외부 전극패드(11a)와, 기판(2)의 외부로부터 스루홀(5)을 통해 외부로 인출되는 외부 전극배선(6)을 포함한다. 외부 전극패드(11a)는, 원주 형태로 형성된 제 1 패드층(12)과, 제 1 패드층(12)의 표면을 덮도록 설치되고, 각추형으로 형성된 제 2 패드층(13)을 포함한다. 제 1 패드층(12)은, 동박 또는 동박에 구리 도금을 적층한 것으로 이루어지고, 그것의 두께는 12㎛∼32㎛의 범위 내에 있다. 제 2 패드층(13)은, 구리 도금을 적층한 것으로, 정점까지의 높이는 12㎛∼62㎛의 범위 내에 있다.Referring to these drawings, the semiconductor device 15 includes a substrate 2. The external electrode 11 is exposed on the surface of the side opposite to the encapsulation portion 1 of the substrate 2. The external electrode 11 is for forming an electrical and physical junction with the mounting substrate. The external electrode 11 includes an external electrode pad 11a and an external electrode wiring 6 drawn out to the outside through the through hole 5 from the outside of the substrate 2. The external electrode pad 11a includes a first pad layer 12 formed in a circumferential shape and a second pad layer 13 formed in a pyramidal shape to cover the surface of the first pad layer 12. . The 1st pad layer 12 consists of what laminated | stacked copper plating on copper foil or copper foil, and the thickness is in the range of 12 micrometers-32 micrometers. The second pad layer 13 is formed by laminating copper plating, and the height to the apex is in the range of 12 µm to 62 µm.

제 2 패드층(13)의 표면에, 이 제 2 패드층(13)의 표면의 산화를 방지하기 위한 녹방지매체(14)가 형성되어 있다. 녹방지매체(14)는, 기판을 실장할 때의 접합매체와의 접합을 촉진하기 위한 역할도 한다. 녹방지매체(14)는, 플럭스(flux) 또는 니켈 도금과 금 도금의 적층으로 이루어진다.On the surface of the second pad layer 13, an antirust medium 14 for preventing oxidation of the surface of the second pad layer 13 is formed. The anti-rust medium 14 also serves to promote bonding with the bonding medium when mounting the substrate. The antirust medium 14 consists of a flux or a lamination of nickel plating and gold plating.

외부전극(11)은, 기판(2)의 봉지부(1)와 대향하는 측에 에리어 어레이 형태로 배치되지만, 그것의 배치방법에 대해서는 특별히 한정되지 않는다. 또한, 상기한 실시예에서는, 제 1 패드층(12)이 원주 형태인 경우를 예시하였지만, 각주이어도 된다. 또한, 제 2 패드층(13)이 원추인 경우를 예시하였지만, 각추라도 된다. 더구나, 각주, 각추에 대해서, 그것의 면수는 특히 한정되지 않는다.Although the external electrode 11 is arrange | positioned in the area array form at the side facing the sealing part 1 of the board | substrate 2, it does not specifically limit about the arrangement method. In addition, in the above-mentioned embodiment, although the case where the 1st pad layer 12 is a cylindrical form was illustrated, a footnote may be sufficient. In addition, although the case where the 2nd pad layer 13 is a cone was illustrated, you may have a pyramid. Moreover, for footnotes and pyramids, the number of facets thereof is not particularly limited.

다음에, 동작에 대해 설명한다.Next, the operation will be described.

도 3은 실시예 1에 관한 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태의 단면도이다. 이때, 종래예와 동일부분에는, 동일한 참조부호를 붙여, 그것의 설명을 반복하지 않는다.3 is a cross-sectional view of a land grid array type semiconductor device according to the first embodiment, mounted on a mounting substrate. At this time, the same reference numerals are given to the same parts as the conventional example, and the description thereof will not be repeated.

반도체장치(15)를 실장기판(8)에 실장함에 있어서, 미리 접합매체(10)를 실장기판(8)의 기판 외부전극(9) 위에 인쇄, 도포한다. 그 상태에서, 반도체장치(15)를 실장기판(8) 위에 탑재한다. 이때, 녹방지매체(14)로 덮인 외부 전극패드(13)를 실장기판(8) 위에 탑재한다. 이때, 녹방지매체(14)로 덮인 외부 전극패드(13)를 기판 외부전극(9) 위에 형성된 접합매체(10)에 눌러넣어, 이들을 고착시킨다. 더구나, 반도체장치(15)가 탑재된 상태의 실장기판(8)을 접합매체(10)의 융점 이상의 온도에서 리플로우한다. 이것에 의해, 접합매체(10)가 용융하여, 반도체장치(15)와 실장기판(8)이 전기적, 물리적으로 접합된다.In mounting the semiconductor device 15 on the mounting substrate 8, the bonding medium 10 is printed and coated on the substrate external electrode 9 of the mounting substrate 8 in advance. In this state, the semiconductor device 15 is mounted on the mounting substrate 8. At this time, the external electrode pad 13 covered with the rust preventing medium 14 is mounted on the mounting substrate 8. At this time, the external electrode pad 13 covered with the rust preventing medium 14 is pressed into the bonding medium 10 formed on the substrate external electrode 9 to fix them. In addition, the mounting substrate 8 with the semiconductor device 15 mounted thereon is reflowed at a temperature equal to or higher than the melting point of the bonding medium 10. As a result, the bonding medium 10 melts, and the semiconductor device 15 and the mounting substrate 8 are electrically and physically bonded to each other.

본 발명의 실시예에 따르면, 반도체장치(15)의 외부 전극패드(13)를 원추 또는 각추 형태로 형성하는 것에 의해, 실장기판(8) 위에 반도체장치를 실장할 때에, 외부 전극패드(13)와 접합매체(10)의 고착성이 향상된다. 이것에 의해, 반도체장치(15)의 외부전극(11)과 실장기판(8)의 기판 외부전극(9)의 위치결정 정밀도가 향상되고, 더구나, 실장 후의 실장기판(8)과 반도체장치(15)와의 접합 신뢰성을 향상시킬 수 있는 효과를 나타낸다.According to the embodiment of the present invention, when the semiconductor device is mounted on the mounting substrate 8 by forming the external electrode pad 13 of the semiconductor device 15 in the form of a cone or a pyramid, the external electrode pad 13 And adhesion of the bonding medium 10 are improved. As a result, the positioning accuracy of the external electrode 11 of the semiconductor device 15 and the substrate external electrode 9 of the mounting substrate 8 is improved, and furthermore, the mounted substrate 8 and the semiconductor device 15 after mounting are improved. The effect which can improve the joining reliability with () is shown.

실시예 2:Example 2:

도 4는, 실시예 2에 관한 랜드 그리드 어레이형 반도체장치의 단면도이다. 이때, 이 도면에 있어서, 실시예 1에 관한 장치와 동일 부분에는, 동일한 참조번호를 붙여, 그것의 설명을 반복하지 않는다.4 is a sectional view of the land grid array semiconductor device according to the second embodiment. At this time, in this figure, the same reference numerals are given to the same parts as the apparatus according to the first embodiment, and the description thereof is not repeated.

도 4를 참조하면, 외부 전극패드(13)의 표면에, 요홈(16)이 형성되어 있다. 요홈(16)은, 원추 또는 각추의 형상을 갖고, 내부를 향해 연장되어 있다. 외부 전극패드(13)의 표면에는, 녹방지매체(14)가 설치되어 있다. 이때, 요홈(16)의 위치, 수량은 특히 한정되지 않는다.Referring to FIG. 4, the groove 16 is formed on the surface of the external electrode pad 13. The groove 16 has the shape of a cone or a pyramid and extends toward the inside. An antirust medium 14 is provided on the surface of the external electrode pad 13. At this time, the position and the number of the grooves 16 are not particularly limited.

다음에, 동작에 대해 설명한다.Next, the operation will be described.

도 5는, 실시예 2에 관한 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태를 나타낸 단면도이다. 이때, 본 실시예 1에 관한 장치와 동일 부분에는, 동일한 참조번호를 붙여, 그것의 설명을 반복하지 않는다.5 is a cross-sectional view showing a state in which the land grid array semiconductor device according to the second embodiment is mounted on a mounting substrate. At this time, the same reference numerals are given to the same parts as the apparatus according to the first embodiment, and the description thereof is not repeated.

반도체장치(17)를 실장기판(8)에 실장함에 있어서, 미리 접합매체(10)를 실장기판(8)의 기판 외부전극(9) 위에 인쇄, 도포해 놓는다. 그 상태에서, 반도체장치(17)를 실장기판(8) 위에 탑재한다. 이때, 녹방지매체(14)에 덮이고, 표면에 요홈(16)이 형성된 외부 전극패드(13)를 기판 외부전극(9) 위의 접합매체(10)에 눌러넣어, 이들을 고착시킨다. 더구나, 반도체장치(17)가 탑재된 상태의 실장기판(8)을 접합매체(10)의 융점 이상의 온도에서 리플로우한다. 이것에 의해, 접합매체(10)가용융하여, 반도체장치(17)와 실장기판(8)이 전기적, 물리적으로 접합된다.In mounting the semiconductor device 17 on the mounting substrate 8, the bonding medium 10 is printed and coated on the substrate external electrode 9 of the mounting substrate 8 in advance. In this state, the semiconductor device 17 is mounted on the mounting substrate 8. At this time, the external electrode pad 13 covered with the rust preventing medium 14 and the groove 16 formed on the surface thereof is pressed into the bonding medium 10 on the substrate external electrode 9 to fix them. In addition, the mounting substrate 8 with the semiconductor device 17 mounted thereon is reflowed at a temperature equal to or higher than the melting point of the bonding medium 10. As a result, the bonding medium 10 is melted, and the semiconductor device 17 and the mounting substrate 8 are electrically and physically bonded to each other.

본 발명의 실시예에 따르면, 외부 전극패드(13)의 표면에, 원추 또는 각추 형태의 요홈(16)이 형성되어 있기 때문에, 실장기판(8) 위에 반도체장치(17)를 실장할 때에, 외부 전극패드(13)와 접합매체(10)의 고착성이 향상된다. 이것에 의해, 반도체장치(17)의 외부전극(11)과 실장기판(8)의 기판 외부전극(9)의 위치결정 정밀도가 향상된다. 더구나, 실장 후의 실장기판(8)의 반도체장치(17)의 접합 신뢰성을 향상된다.According to the embodiment of the present invention, since the groove 16 in the form of a cone or a pyramid is formed on the surface of the external electrode pad 13, when mounting the semiconductor device 17 on the mounting substrate 8, the external The adhesion between the electrode pad 13 and the bonding medium 10 is improved. As a result, the positioning accuracy of the external electrode 11 of the semiconductor device 17 and the substrate external electrode 9 of the mounting substrate 8 is improved. Moreover, the bonding reliability of the semiconductor device 17 of the mounting board 8 after mounting is improved.

실시예 3:Example 3:

도 6은, 실시예 3에 관한 랜드 그리드 어레이형 반도체장치의 단면도이며, 도 7은 그것의 하측에서 본 저면도이다. 도면 중에서, 상기한 실시예에 관한 장치와 동일 부분에는 동일한 참조번호를 붙여, 그것의 설명을 반복하지 않는다.6 is a cross-sectional view of the land grid array type semiconductor device according to the third embodiment, and FIG. 7 is a bottom view of the land grid array semiconductor device. In the drawings, the same reference numerals are given to the same parts as the apparatus according to the above embodiment, and the description thereof will not be repeated.

이들 도면을 참조하면, 반도체장치(22)는 기판(2)을 구비한다. 더미전극(18)이 기판(2)의 봉지부(1)와 대향하는 측의 표면에 설치되어 있다. 더미전극(18)은, 외부전극(11)과는 다른 형상을 갖고, 외부전극(11)과는 전기적, 물리적으로 도통하고 있지 않다.Referring to these drawings, the semiconductor device 22 includes a substrate 2. The dummy electrode 18 is provided on the surface of the side opposite to the encapsulation portion 1 of the substrate 2. The dummy electrode 18 has a different shape from the external electrode 11 and is not electrically and physically connected to the external electrode 11.

더미전극(18)은, 서로 중첩되도록 형성된 제 1 외부 전극패드(19)와 제 2 외부 전극패드(20)를 포함한다. 제 1 외부 전극패드(19)는, 본 실시예에서는 원주의 형상을 갖지만, 각주의 형상이어도 된다. 제 1 외부 전극패드(19)의 두께는, 12㎛∼32㎛의 범위 내에 있다. 제 1 외부 전극패드(19)는, 동박 또는 동박에 구리 도금을 적층한 것으로 이루어진다. 제 2 외부 전극패드(20)는, 제 1 외부전극 패드(19)의 표면 전체면을 덮도록 형성되어 있다. 제 2 외부 전극패드(20)는 본 실시예에서는, 원추이지만, 각추의 형태를 갖더라도 된다. 제 2 외부 전극패드(20)의 정점까지의 높이는, 12㎛∼62㎛의 범위 내에 있다. 제 2 외부 전극패드(20)는, 구리 도금을 적층한 것으로 구성된다. 녹방지매체(21)는, 외부 전극패드(20)의 표면의 산화를 방지하고, 기판을 실장할 때의 접합매체와의 접합을 촉진하기 위해 설치되어 있다. 녹방지매체(21)는, 플럭스 또는 니켈 도금과 금 도금의 적층으로 이루어진다. 더미전극(18)은, 기판(2)의 봉지부(1)와 대향하는 측에 배치되지만, 배치방법과 그것의 개수에 대해서는 특별히 한정되지 않는다. 또한, 본 실시예에 있어서, 각주, 각추에 대해서는 그것의 면수를 특별히 한정하지 않는다.The dummy electrode 18 includes a first external electrode pad 19 and a second external electrode pad 20 formed to overlap each other. Although the 1st external electrode pad 19 has a columnar shape in a present Example, the shape of a footnote may be sufficient. The thickness of the 1st external electrode pad 19 exists in the range of 12 micrometers-32 micrometers. The 1st external electrode pad 19 consists of laminated | stacked copper plating on copper foil or copper foil. The second external electrode pad 20 is formed to cover the entire surface of the first external electrode pad 19. In the present embodiment, the second external electrode pad 20 is a cone, but may have the form of a pyramid. The height to the apex of the second external electrode pad 20 is in the range of 12 µm to 62 µm. The second external electrode pad 20 is formed by laminating copper plating. The antirust medium 21 is provided to prevent oxidation of the surface of the external electrode pad 20 and to promote bonding with the bonding medium when mounting the substrate. The antirust medium 21 consists of a stack of flux or nickel plating and gold plating. Although the dummy electrode 18 is arrange | positioned on the side opposite to the sealing part 1 of the board | substrate 2, it does not specifically limit about an arrangement method and its number. In addition, in a present Example, about footnote and a pyramid, it does not specifically limit the number of surface.

다음에, 동작에 대해 설명한다.Next, the operation will be described.

도 8은, 실시예 3에 관한 랜드 그리드 어레이형 반도체장치를 실장기판에 실장한 상태를 나타낸 단면도이다. 본 도면에 있어서, 상기한 실시예에 관한 장치와 동일 부분에는 동일한 참조번호를 붙여, 그것의 설명을 반복하지 않는다.8 is a cross-sectional view showing a state in which the land grid array semiconductor device according to the third embodiment is mounted on a mounting substrate. In the figure, the same reference numerals are given to the same parts as the apparatus according to the above embodiment, and the description thereof will not be repeated.

도 8을 참조하면, 반도체장치(22)를 실장기판(8)에 실장함에 있어서, 미리, 접합매체(10)를 실장기판(8)의 기판 외부전극(9) 위에 인쇄, 도포하여 놓는다. 그 상태에서, 반도체장치(22)를 실장기판(8) 상에 탑재한다. 이때, 녹방지매체 14에 덮인 외부 전극패드 13(외부전극(11)측)과 녹방지매체 21에 덮인 외부 전극패드 20(더미전극(18)측)을 기판 외부전극(9) 상의 접합매체(10)에 눌러넣어, 이들을 고착시킨다. 더구나, 반도체장치(22)가 탑재된 상태의 실장기판(8)을 접합매체(10)의 융점 이상의 온도에서 리플로우한다. 이것에 의해, 접합매체(10)가 용융하여, 반도체장치(22)와 실장기판(8)이 전기적, 물리적으로 접합된다.Referring to FIG. 8, in mounting the semiconductor device 22 on the mounting substrate 8, the bonding medium 10 is printed and coated on the substrate external electrode 9 of the mounting substrate 8 in advance. In this state, the semiconductor device 22 is mounted on the mounting substrate 8. At this time, the external electrode pad 13 (external electrode 11 side) covered by the rust-proof medium 14 and the external electrode pad 20 (dummy electrode 18 side) covered by the rust-proof medium 21 are bonded to the substrate external electrode 9 ( 10), and fix them. In addition, the mounting substrate 8 with the semiconductor device 22 mounted thereon is reflowed at a temperature equal to or higher than the melting point of the bonding medium 10. As a result, the bonding medium 10 is melted, and the semiconductor device 22 and the mounting substrate 8 are electrically and physically bonded to each other.

본 실시예에 따르면, 외부전극(11)측의 외부 전극패드 13에 덧붙여, 더미전극(18)측에 외부 전극패드(20)를 형성하는 것에 의해, 실장기판(8)에 반도체장치(22)를 실장할 때에, 더미전극(18)측의 외부 전극패드(20)가 외부전극(11)과 접합매체(10)와의 고착성을 조장시킨다. 그 결과, 외부전극(11)과 접합매체(10)의 고착성이 향상되고, 이것에 의해, 반도체장치(22)의 외부전극(11)과 실장기판(8)의 기판 외부전극(9)의 위치결정 정밀도가 향상된다. 더구나, 실장후의 실장기판(8)과 반도체장치(22)와의 접합 신뢰성이 향상된다.According to the present embodiment, in addition to the external electrode pad 13 on the external electrode 11 side, the external electrode pad 20 is formed on the dummy electrode 18 side, whereby the semiconductor device 22 is mounted on the mounting substrate 8. When mounting, the external electrode pad 20 on the dummy electrode 18 side promotes adhesion between the external electrode 11 and the bonding medium 10. As a result, the adhesion between the external electrode 11 and the bonding medium 10 is improved, whereby the position of the external electrode 11 of the semiconductor device 22 and the substrate external electrode 9 of the mounting substrate 8 are improved. Decision precision is improved. In addition, the bonding reliability between the mounting substrate 8 and the semiconductor device 22 after mounting is improved.

이때, 외부전극(11)측의 외부 전극패드(13) 또는 더미전극(18)측의 외부 전극패드(20)에 어느 한 개의 표면, 또는 그것의 양쪽의 표면에, 전술한 요홈(16)을 형성하여도, 더욱 양호한 효과가 얻어진다.At this time, the above-described groove 16 is formed on any one surface or both surfaces thereof on the external electrode pad 13 on the external electrode 11 side or the external electrode pad 20 on the dummy electrode 18 side. Even if it forms, a more favorable effect is acquired.

이번에 개시된 실시예는 모든 점에서 예시를 들기 위한 것으로 제한적인 것은 아니라고 생각해야 할 것이다. 본 발명의 범위는 전술한 설명이 아니라 특허청구범위에 의해 표시되며, 특허청구범위와 균등의 의미 및 범위 내에서 모든 변형을 포함하는 것이 의도된다.The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the claims rather than the foregoing description, and is intended to include all modifications within the meaning and range of equivalency of the claims.

이상 설명한 것과 같이, 본 발명의 제 1 국면에 따른 랜드 그리드 어레이형반도체장치에 따르면, 반도체장치의 외부전극과 실장기판의 기판 외부전극과의 위치결정 정밀도가 향상된다. 더구나, 실장 후의 실장기판과 반도체장치의 접합 신뢰성이 향상된다.As described above, according to the land grid array semiconductor device according to the first aspect of the present invention, the positioning accuracy of the external electrode of the semiconductor device and the substrate external electrode of the mounting substrate is improved. In addition, the bonding reliability of the mounted substrate and the semiconductor device after mounting is improved.

또한, 본 발명의 제 2 국면에 따른 랜드 그리드 어레이형 반도체장치의 실장방법에 따르면, 반도체장치의 외부전극과 실장기판의 기판 외부전극의 위치결정 정밀도가 향상된다. 더구나, 실장 후의 실장기판과 반도체장치의 접합 신뢰성이 향상된다.Further, according to the mounting method of the land grid array semiconductor device according to the second aspect of the present invention, the positioning accuracy of the external electrode of the semiconductor device and the substrate external electrode of the mounting substrate is improved. In addition, the bonding reliability of the mounted substrate and the semiconductor device after mounting is improved.

Claims (3)

기판(2)과,The substrate 2, 상기 기판(2)의 한쪽 면에, 에리어 어레이 형태로 배치된 외부전극(11)을 구비하고,On one side of the substrate 2, an external electrode 11 disposed in the form of an area array is provided, 상기 외부전극(11)은, 외부 전극패드(11a)와, 상기 기판(2)의 내부로부터 스루홀(5)을 거쳐 외부로 인출된 외부 전극배선(6)을 포함하며,The external electrode 11 includes an external electrode pad 11a and an external electrode wiring 6 drawn out from the inside of the substrate 2 through the through hole 5, and 상기 외부 전극패드(11a)는, 원주 형태 또는 각주 형태로 형성된 제 1 패드층(12)과, 이 제 1 패드층(12)의 표면을 덮도록 설치되고, 원추 형태 또는 각추 형태로 형성된 제 2 패드층(13)을 포함하는 랜드 그리드 어레이형 반도체장치.The external electrode pad 11a is provided to cover the surface of the first pad layer 12 and the first pad layer 12 formed in the circumferential form or the circumferential form, and the second electrode formed in the form of a cone or pyramid. Land grid array type semiconductor device comprising a pad layer (13). 제 1항에 있어서,The method of claim 1, 상기 제 2 패드층(13)의 표면에는, 오목부(16)가 형성되어 있는 것을 특징으로 하는 랜드 그리드 어레이형 반도체장치.A land grid array type semiconductor device, characterized in that a concave portion (16) is formed on the surface of the second pad layer (13). 기판(2)과, 상기 기판(2)의 한쪽 면에, 에리어 어레이 형태로 배치된 외부전극(11)을 구비하고, 상기 외부전극(11)은, 외부 전극패드(11a)와, 상기 기판(2)의 내부로부터 스루홀(5)을 거쳐 외부로 인출된 외부 전극배선(6)을 포함하며, 상기외부 전극패드(11a)는, 원주 형태 또는 각주 형태로 형성된 제 1 패드층(12)과, 이 제 1 패드층(12)의 표면을 덮도록 설치되고, 원추 형태 또는 각추 형태로 형성된 제 2 패드층(13)을 포함하는 랜드 그리드 어레이형 반도체장치를 준비하는 공정과,The board | substrate 2 and the external electrode 11 arrange | positioned in the area array form on one surface of the said board | substrate 2 are provided, The said external electrode 11 is the external electrode pad 11a and the said board | substrate ( 2) an external electrode wiring 6 drawn out from the inside through the through-hole 5 from the inside, wherein the external electrode pad 11a includes a first pad layer 12 formed in a circumferential form or a footnote form; Preparing a land grid array semiconductor device including a second pad layer 13 formed to cover the surface of the first pad layer 12 and formed in a cone shape or a pyramidal shape; 기판 외부전극(9)과, 이 기판 외부전극(9)의 표면을 덮도록 설치된 접합매체(14)를 갖는 실장기판(8)을 준비하는 공정과,Preparing a mounting substrate 8 having a substrate external electrode 9 and a bonding medium 14 provided to cover the surface of the substrate external electrode 9; 상기 랜드 그리드 어레이형 반도체장치의 상기 제 2 패드층(13)을 상기 실장기판(8)의 상기 접합매체(14)에 눌러넣어, 상기 실장기판(8)에 상기 랜드 그리드 어레이형 반도체장치를 고착시키는 공정과,The land pad array semiconductor device is fixed to the mounting substrate 8 by pressing the second pad layer 13 of the land grid array semiconductor device onto the bonding medium 14 of the mounting substrate 8. Process to let 상기 랜드 그리드 어레이형 반도체장치가 탑재된 상기 실장기판(8)을 상기 접합매체(14)의 융점 이상의 온도로 어닐링하는 공정을 구비한 것을 특징으로 하는 랜드 그리드 어레이형 반도체장치의 제조방법.And annealing the mounting substrate (8) on which the land grid array semiconductor device is mounted at a temperature equal to or higher than the melting point of the bonding medium (14).
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