KR20020076935A - Method for manufacturing thin film transistor lcd - Google Patents
Method for manufacturing thin film transistor lcd Download PDFInfo
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- KR20020076935A KR20020076935A KR1020010017170A KR20010017170A KR20020076935A KR 20020076935 A KR20020076935 A KR 20020076935A KR 1020010017170 A KR1020010017170 A KR 1020010017170A KR 20010017170 A KR20010017170 A KR 20010017170A KR 20020076935 A KR20020076935 A KR 20020076935A
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
- G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1341—Filling or closing of cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
Description
본 발명은 박막 트랜지스터 액정표시장치 제조방법에 관한 것으로, 보다 구체적으로는 어레이 기판 제조 공정에서 하프톤 노광 기술을 이용하여 감광막 스페이서를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of forming a photosensitive film spacer using a halftone exposure technique in an array substrate manufacturing process.
일반적으로, 박막 트랜지스터(THIN FILM TRANSISTOR: TFT) 액정표시장치는 어레이 기판과 컬러 필터 기판이 액정층을 사이에 두고 합착된 구조를 가지고 있다. 이러한, 액정표시장치는 어레이 기판 상에 배치된 화소 전극에 그래픽 신호가 인가되면, 상기 컬러 필터 기판에 배치된 상대 전극과의 사이에서 전계가 발생하여, 액정 분자들을 트위스트 시키게 되고, 상기 트위스트된 액정 분자들에의해 편광된 빛의 투과율이 조절되어, 그래픽 신호를 디스플레이하게 된다.In general, a thin film transistor (THIN FILM TRANSISTOR) liquid crystal display device has a structure in which an array substrate and a color filter substrate are bonded to each other with a liquid crystal layer interposed therebetween. In the liquid crystal display, when a graphic signal is applied to a pixel electrode disposed on an array substrate, an electric field is generated between the counter electrode disposed on the color filter substrate, thereby twisting liquid crystal molecules, and twisting the liquid crystal. The transmittance of polarized light by the molecules is controlled to display the graphic signal.
따라서, 액정표시장치의 어레이 기판과 컬러 필터 기판 간의 셀 갭을 일정하게 유지시키기 위하여, 상기 어레이 기판 상에 플라스틱 재질로된 볼 모양의 스페이서를 산포한 상태로, 두 기판을 합착한다.Therefore, in order to maintain a constant cell gap between the array substrate and the color filter substrate of the liquid crystal display device, the two substrates are bonded to each other in a state in which a ball-shaped spacer made of a plastic material is distributed on the array substrate.
이하 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the drawings will be described in detail.
도 1a는 종래 기술에 따른 박막 트랜지스터 액정표시장치의 평면도이고, 도 1b는 상기 도 1a의 A-A`부분을 수직 절단한 단면도이다.FIG. 1A is a plan view of a thin film transistor liquid crystal display device according to the related art, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A.
도 1a를 참조하면, 데이터 라인(7a)과 게이트 버스 라인(1a)이 수직으로 교차되어 단위 화소 영역이 한정된다. 상기 화소 영역에는 전계를 발생시키는 화소 전극(9)이 배치된다. 상기 게이트 버스 라인(1a)과 데이터 라인(7a)의 교차부에는 스위칭 소자인 TFT가 형성되어 있다.Referring to FIG. 1A, the data line 7a and the gate bus line 1a cross vertically to define a unit pixel area. The pixel electrode 9 generating an electric field is disposed in the pixel region. A TFT, which is a switching element, is formed at the intersection of the gate bus line 1a and the data line 7a.
도 1b를 참조하면, 게이트 전극(1b)을 포함한 게이트 버스 라인(1a)이 형성되어 있는 유리 기판(50)의 전 영역 상에 게이트 절연막(13)이 형성된다. 상기 게이트 절연막(13) 상에는 액티브층(5)과 소오스/드레인 전극(7b, 3)을 포함하는 TFT가 형성되고, 상기 TFT 상에 보호막(11)이 도포된다. 상기 보호막(11) 상에는 전계 발생을 위한 화소 전극(9)이 상기 드레인 전극(3)과 콘텍하도록 형성된다.Referring to FIG. 1B, the gate insulating layer 13 is formed on the entire region of the glass substrate 50 on which the gate bus line 1a including the gate electrode 1b is formed. A TFT including an active layer 5 and source / drain electrodes 7b and 3 is formed on the gate insulating film 13, and a protective film 11 is coated on the TFT. On the passivation layer 11, a pixel electrode 9 for generating an electric field is formed to contact the drain electrode 3.
상기와 같은 구조의 어레이 기판 상에는 일정한 셀 갭을 유지하기 위하여, 볼 모양의 스페이서가 산포되고, 그후에 상기 어레이 기판과 컬러 필터 기판이 합착된다.In order to maintain a constant cell gap on the array substrate of the above structure, a ball-shaped spacer is spread, and then the array substrate and the color filter substrate are bonded.
그러나, 플라스틱 재질로된 볼 모양의 스페이서는 액정 분자의 정상적인 배향을 방해하여 빛샘 현상을 유발하며, 아울러, 외부적인 충격이나 진동에 의하여 일정한 위치에 산포되지 못하는 단점이 있다.However, a ball-shaped spacer made of plastic material may interfere with the normal alignment of liquid crystal molecules to cause light leakage, and also may not be dispersed at a predetermined position due to external shock or vibration.
또한, 스페이서의 산포과정에서 뭉침현상이 발생할 경우, 일정한 셀 갭 유지가 어려운 문제점이 있다.In addition, when agglomeration occurs in the dispersion process of the spacer, it is difficult to maintain a constant cell gap.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 하프 톤 노광 기술을 이용하여 감광막 스페이서를 형성하는 박막 트랜지스터 액정표시장치 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor liquid crystal display device in which a photosensitive film spacer is formed using a halftone exposure technique.
도 1a는 종래 기술에 따른 박막 트랜지스터 액정표시장치의 평면도.1A is a plan view of a thin film transistor liquid crystal display device according to the prior art.
도 1b는 상기 도 1a의 A-A`부분을 수직 절단한 단면도.1B is a cross-sectional view taken along the line A-A 'of FIG. 1A;
도 2a 내지 도 2d는 본 발명에 따른 스페이서 제조 공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a spacer manufacturing process according to the present invention.
도 3은 본 발명에 따라 스페이서가 형성되는 위치를 표시한 평면도.Figure 3 is a plan view showing the position where the spacer is formed in accordance with the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1b: 게이트 전극 3: 드레인 전극1b: gate electrode 3: drain electrode
5: 액티브 층 7b: 소오스 전극5: active layer 7b: source electrode
8: ITO 금속막 9: 화소 전극8: ITO metal film 9: pixel electrode
11: 보호막 13: 게이트 절연막11: protective film 13: gate insulating film
15: 하프톤 패턴 16: 제 2 감광막 패턴15: halftone pattern 16: second photosensitive film pattern
17: 감광막 스페이서 20: 제 1 감광막 패턴17 photosensitive film spacer 20 first photosensitive film pattern
50: 유리 기판50: glass substrate
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 게이트 버스 라인 및 데이터 버스 라인이 형성되고, 게이트 전극, 게이트 절연막, 액티브층,및 소오스/드레인 전극을 포함하는 박막 트랜지스터가 형성된 유리기판 상에 보호막을 도포하고, 상기 보호막을 식각하여 상기 박막 트랜지스터의 소정 부분을 노출시키는 단계; 상기 보호막 상에 노출된 박막 트랜지스터 부분과 콘텍되도록 ITO 금속막을 증착하는 단계; 상기 ITO 금속막 상에 감광막을 도포하고, 하프톤 마스크를 사용하여 노광하는 단계; 상기 노광된 감광막을 현상하여, 상대적으로 두꺼운 하프톤 패턴을 갖는 제 1 감광막 패턴과, 하프톤 패턴을 갖지않는 제 2 감광막 패턴을 형성하는 단계; 상기 제 1 감광막 패턴을 마스크로 사용하여, 상기 ITO 금속막을 식각하는 것에 의해 화소 영역에 화소 전극을 형성하는 단계; 상기 제 2 감광막 패턴을 제거함과 동시에 제 1 감광막 패턴의 하프톤 패턴을 잔류시켜 감광막 스페이서를 형성하고, 상기 감광막 스페이서는 게이트 버스 라인의 상부에 형성하며, 상기 하프톤 패턴은 화소를 하나 또는 하나 이상 건너서 형성하고, 상기 감광막 스페이서는 3.5 ~4㎛ 높이로 형성하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention, the gate bus line and the data bus line is formed on the glass substrate on which a thin film transistor including a gate electrode, a gate insulating film, an active layer, and a source / drain electrode is formed. Applying a passivation layer to the substrate, and etching the passivation layer to expose a predetermined portion of the thin film transistor; Depositing an ITO metal film to be in contact with the exposed portion of the thin film transistor on the passivation layer; Applying a photosensitive film on the ITO metal film and exposing using a halftone mask; Developing the exposed photoresist to form a first photoresist pattern having a relatively thick halftone pattern, and a second photoresist pattern having no halftone pattern; Forming a pixel electrode in the pixel region by etching the ITO metal film using the first photoresist pattern as a mask; The second photoresist pattern is removed and a halftone pattern of the first photoresist pattern is left to form a photoresist spacer. The photoresist spacer is formed on the gate bus line, and the halftone pattern includes one or more pixels. It is formed across, the photosensitive film spacer is characterized in that it is formed to a height of 3.5 ~ 4㎛.
본 발명에 의하면, 어레이 기판 제조 공정중에 하프톤 노광 기술을 이용해서, 감광막 패턴으로 스페이서를 형성하기 때문에, 스페이서의 위치 변동은 발생되지 않으며, 특히, 셀 갭을 일정하게 유지할 수 있다.According to the present invention, since the spacers are formed in the photosensitive film pattern using the halftone exposure technique during the array substrate manufacturing process, the positional variation of the spacers does not occur, and in particular, the cell gap can be kept constant.
(실시예)(Example)
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2d는 본 발명에 따른 감광막 스페이서를 포함한 박막 트랜지스터 액정표시장치 제조 공정을 도시한 단면도이고, 도 3은 본 발명에 따라 스페이서가 형성되는 위치를 표시한 평면도이다.2A to 2D are cross-sectional views illustrating a process of manufacturing a thin film transistor liquid crystal display device including a photosensitive film spacer according to the present invention, and FIG. 3 is a plan view showing a position where a spacer is formed according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 공지된 5-마스크 공정의 제 3-마스크 공정까지 수행하여, 유리기판(50) 상에 게이트 전극(1b)과, 게이트 절연막(13), 액티브층(5) 및 소오스/드레인 전극(7b, 3)을 포함하는 박막 트랜지스터를 형성하고, 상기 박막 트랜지스터는 보호막(11)을 유리기판(50)의 전체 상부에 도포한다. 그런다음, 제 4-마스크 공정을 수행하여 박막 트랜지스터의 드레인 전극(3)을 노출시키고, 상기 보호막(11) 상에 노출된 드레인 전극(3)과 콘텍하도록 ITO 금속막(8)을 증착한다.First, as shown in FIG. 2A, the gate electrode 1b, the gate insulating layer 13, and the active layer 5 are performed on the glass substrate 50 by performing the third mask process of the known 5-mask process. ) And a source / drain electrodes 7b and 3 to form a thin film transistor, and the thin film transistor applies the protective film 11 to the entire upper portion of the glass substrate 50. Thereafter, a fourth mask process is performed to expose the drain electrode 3 of the thin film transistor, and the ITO metal film 8 is deposited on the passivation layer 11 so as to contact the exposed drain electrode 3.
다음으로, 도 2b에 도시한 바와 같이, 상기 ITO 금속막(8) 상에 감광막을 도포한 후, 하프 톤 마스크(도시하지 않음)를 사용하여 상기 감광막을 노광하고, 상기 노광된 감광막을 현상하여, 화소 전극 및 스페이서가 형성될 ITO 금속막 부분 상에 하프톤 패턴(15)를 포함한 제 1 감광막 패턴(20)을 형성한다. 여기서, 상기 하프톤 패턴(15)의 높이는 그 이외의 제 1 감광막 패턴(20) 부분 보다 상대적으로 두껍다. 또한, 스페이서가 형성됨이 없이 화소 전극이 형성될 영영 상에는 하프톤 패턴(15)이 없는 제 2 감광막(16)이 형성된다.Next, as shown in FIG. 2B, after the photoresist film is applied on the ITO metal film 8, the photoresist film is exposed using a halftone mask (not shown), and the exposed photoresist film is developed. The first photosensitive film pattern 20 including the halftone pattern 15 is formed on the portion of the ITO metal film on which the pixel electrode and the spacer are to be formed. Here, the height of the halftone pattern 15 is relatively thicker than the portion of the first photosensitive film pattern 20 other than that. In addition, the second photosensitive layer 16 having no halftone pattern 15 is formed on the region where the pixel electrode is to be formed without forming the spacer.
도 2c에 도시한 바와 같이, 하프톤 패턴(15)을 갖는 제 1 감광막 패턴(20)과 하프톤 패턴이 없는 감광막 패턴(16)을 마스크로 사용하여 ITO 금속막(8)을 식각함으로써, 화소 전극(9)을 형성한다.As shown in FIG. 2C, the ITO metal film 8 is etched by using the first photoresist pattern 20 having the halftone pattern 15 and the photoresist pattern 16 without the halftone pattern as a mask. The electrode 9 is formed.
그다음, 도 2d에 도시한 바와 같이, 제 1 감광막 패턴과 제 2 감광막 패턴에 대한 에싱을 수행한다. 이때, 제 1 감광막 패턴의 하프톤 패턴(15)은 그이외 붑분 및 제 2 감광막 패턴 보다 상대적으로 두껍기 때문에, 상기 하프톤 패턴을 제외한제 1 감광막 패턴 부분과 제 2 감광막 패턴은 제거되는 반면, 상기 하프톤 패턴은 일부높이가 잔류되며, 이때, 잔류된 하프톤 패턴에의해 감광막 스페이서(17)가 형성된다.Then, as illustrated in FIG. 2D, ashing is performed on the first photoresist pattern and the second photoresist pattern. In this case, since the halftone pattern 15 of the first photoresist pattern is relatively thicker than the other photoresist and the second photoresist pattern, the first photoresist pattern portion and the second photoresist pattern except for the halftone pattern are removed. The height of the halftone pattern remains, and at this time, the photosensitive film spacer 17 is formed by the remaining halftone pattern.
상기에서, 제 1 및 제 2 감광막 패턴에 대한 에싱은 O2기체를 사용한다. 일반적으로 TFT의 전기적 특성을 향상시키기 위하여, 어레이 공정이 완료된 후 열처리 공정을 열처리 공정을 수행하게 되는데, 이러한, 열처리 공정은 감광막 스페이서의 열적 손상을 방지하기 위하여 액티브 패터닝 후부터 ITO 금속막 증착후 사이의 공정에서 행한 다음, 화소 전극과 감광막 스페이서(17)를 형성할 수 있다.In the above, ashing for the first and second photoresist patterns uses O 2 gas. In general, in order to improve the electrical characteristics of the TFT, the heat treatment process is performed after the array process is completed, such a heat treatment process between the active patterning and after the deposition of the ITO metal film to prevent thermal damage of the photoresist spacer After the process, the pixel electrode and the photoresist spacer 17 can be formed.
한편, 상기 감광막 스페이서(17)의 높이는 3.5 ~4㎛로 형성함이 바람직하며, 개구율을 높이기 위하여 게이트 버스 라인의 상부에 형성함이 바람직하다.On the other hand, the height of the photosensitive film spacer 17 is preferably formed to 3.5 ~ 4㎛, it is preferable to form on the upper portion of the gate bus line in order to increase the aperture ratio.
도 3은 본 발명에 따라 스페이서가 형성되는 위치를 표시한 평면도이다. 도시한 바와 같이, 감광막 스페이서(17)는 화소 하나 혹은, 그 이상 건너서 게이트 버스 라인 상에 형성됨이 바람직하다. 도시하였지만, 설명하지 않은 부호 30은 어레이 기판.3 is a plan view showing a position where a spacer is formed according to the present invention. As shown, the photoresist spacer 17 is preferably formed on the gate bus line across one or more pixels. Although not shown, reference numeral 30 denotes an array substrate.
상기와 같은 방법으로 형성된 감광막 스페이서는 외부의 충격이나, 진동에 의해서 위치가 변하지 않으며, 셀갭을 일정하게 유지할 수 있어 종래의 볼 모양의 스페이서를 산포하여 발생하는 문제점을 제거할 수 있다.The photoresist spacer formed by the above method does not change its position due to external shock or vibration, and can maintain a constant cell gap, thereby eliminating a problem caused by scattering a conventional ball-shaped spacer.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 액정표시장치의 제조시에, 스페이서 산포 공정을 생략할 수 있다. 또한, 감광막 스페이서는 외부의 진동이나 충격에 의하여 위치가 변경되지 않아 일정한 셀 갭을 유지할 수 있다.As described in detail above, according to the present invention, the spacer spreading process may be omitted in the manufacture of the liquid crystal display. In addition, since the photoresist spacer is not changed in position due to external vibration or impact, a constant cell gap can be maintained.
게다가, 감광막 스페이서는 기존의 공정에서 사용되는 감광막과 마스크 공정을 사용하여 형성할 수 있으므로, 새로운 시설 장비가 추가 되지 않는다.In addition, the photoresist spacer can be formed using the photoresist and mask process used in the existing process, so that no new facility equipment is added.
아울러, 스페이서의 불균일한 산포에 의하여 액정 분자의 배향이 흐트러져 빛샘이 발생하는 현상을 방지할 수 있다.In addition, it is possible to prevent the phenomenon in which light leakage occurs due to the disorientation of the liquid crystal molecules due to the nonuniform dispersion of the spacer.
본 발명은 상기한 실시 예에 한정되지 않고, 이하 청구 범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040040086A (en) * | 2002-11-06 | 2004-05-12 | 삼성전자주식회사 | Thin film transistor array panel and liquid crystal display divice |
| KR100862536B1 (en) * | 2002-11-07 | 2008-10-09 | 엘지디스플레이 주식회사 | Liquid Crystal Display Panel And Fabricating Method Thereof |
| KR101029409B1 (en) * | 2004-05-28 | 2011-04-14 | 엘지디스플레이 주식회사 | Lcd and method for manufacturing lcd |
| KR101130873B1 (en) * | 2003-12-22 | 2012-03-28 | 엘지디스플레이 주식회사 | Method of fabricating liquid crystal display panel |
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| JP3391485B2 (en) * | 1992-12-10 | 2003-03-31 | セイコーエプソン株式会社 | Manufacturing method of liquid crystal element |
| JPH11190851A (en) * | 1997-12-26 | 1999-07-13 | Canon Inc | Liquid crystal element and its production |
| JPH11218770A (en) * | 1998-01-29 | 1999-08-10 | Denso Corp | Liquid crystal cell and its manufacture |
| KR100625027B1 (en) * | 1999-03-19 | 2006-09-20 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display Device And Method Thereof |
| JP3498020B2 (en) * | 1999-09-29 | 2004-02-16 | Ｎｅｃ液晶テクノロジー株式会社 | Active matrix substrate and manufacturing method thereof |
| KR100413668B1 (en) * | 2001-03-29 | 2003-12-31 | 엘지.필립스 엘시디 주식회사 | A method for fabricating array substrate for liquid crystal display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040040086A (en) * | 2002-11-06 | 2004-05-12 | 삼성전자주식회사 | Thin film transistor array panel and liquid crystal display divice |
| KR100862536B1 (en) * | 2002-11-07 | 2008-10-09 | 엘지디스플레이 주식회사 | Liquid Crystal Display Panel And Fabricating Method Thereof |
| KR101130873B1 (en) * | 2003-12-22 | 2012-03-28 | 엘지디스플레이 주식회사 | Method of fabricating liquid crystal display panel |
| KR101029409B1 (en) * | 2004-05-28 | 2011-04-14 | 엘지디스플레이 주식회사 | Lcd and method for manufacturing lcd |
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