KR100309213B1 - A method for manufacturing an lcd using a diffarctive expos ure - Google Patents

Abstract

The present invention provides a gate insulating film in a method of manufacturing a liquid crystal display device, in which a substrate in which a gate insulating film, a semiconductor layer, and a protective layer are laminated is partially changed in a single mask process using a diffraction exposure technique. And a method of protecting the gate metal under the gate insulating layer by minimizing etching thereof. According to the present invention, a photoresist is applied to a substrate on which a gate insulating layer, a semiconductor layer, and a protective layer are stacked, and the first portion and the lattice pattern are applied to the photoresist and the photoresist remains as it is. Forming a second portion in which the photoresist remains less than half of the first portion, and a third portion in which the photoresist is not left at all; and a plasma etchant containing only F group as the main component. Etching until the layer is removed, removing the photoresist and the passivation layer of the second portion and removing the gate insulating layer of the third portion with a plasma etchant including O ₂ and F groups; Manufacturing a liquid crystal display device comprising removing only the semiconductor layer in the second and third portions with a plasma etchant comprising It provides the law.

Description

A method for manufacturing a liquid crystal display using a diffraction exposure technique {A METHOD FOR MANUFACTURING AN LCD USING A DIFFARCTIVE EXPOS URE}

The present invention relates to a method of manufacturing a liquid crystal display by etching using a diffraction exposure technique. In particular, in the manufacturing of the liquid crystal display device, in the manufacturing method of partially etching the substrate in which the gate insulating film, the semiconductor layer, and the protective film three layers are laminated using a diffraction exposure technique in a single mask process. A method of protecting the gate metal under the gate insulating film by minimizing the gate insulating film is etched.

Among the display devices that display image information on the screen, the CRT (or Cathode Ray Tube (CRT)) has been the most used so far, which is inconvenient to use because it is bulky and heavy compared to the display area. Therefore, even if the display area is large, the thin film type flat panel display device which has a small thickness and can be easily used in any place has been developed, and is gradually replacing the CRT display device. In particular, the liquid crystal display (or liquid crystal display) has the highest resolution than other flat panel displays, and the quality of the moving picture is faster than that of CRT. to be.

The driving principle of the liquid crystal display device is to use the optical anisotropy and polarization property of the liquid crystal. Since the structure is thin and long, the direction of the molecular arrangement can be controlled by artificially applying an electromagnetic field to liquid crystal molecules having directionality and polarization in the molecular arrangement. Therefore, if the alignment direction is arbitrarily adjusted, light can be transmitted or blocked according to the alignment direction of the liquid crystal molecules by optical anisotropy of the liquid crystal, and thus it is applied to a screen display device. Nowadays, the active matrix liquid crystal display device in which a thin film transistor (or TFT) and pixel electrodes connected thereto are arranged in a matrix manner is excellent in providing image quality and natural colors. The structure of the liquid crystal panel, which is a basic component of a general liquid crystal display, will be described in detail as follows. 1 is a perspective view illustrating a general structure of a liquid crystal panel, and FIG. 2 is a diagram illustrating a cross section of a liquid crystal panel taken by cutting line II-II of FIG. 1.

In the liquid crystal panel, two panels 3 and 5 provided with various elements are attached to each other and the liquid crystal layer 10 is sandwiched therebetween. One panel of the liquid crystal display includes elements that implement color. This is often called "color filter panel 3". In the color filter panel 3, red (R), green (G), and blue (B) color filters 7 are sequentially arranged along the positions of pixels designed in a matrix arrangement on the first transparent substrate 1a. have. Between these color filters 7, a very fine black matrix 9 is formed. This prevents the appearance of mixed colors between each color. And the common electrode 8 which covers the color filter 7 is formed. The common electrode 8 serves as one electrode forming an electric field applied to the liquid crystal 10.

On the other panel of the liquid crystal display, switch elements and wirings for generating an electric field for driving the liquid crystal are formed. This is often referred to as "active panel 5". In the active panel 5, a pixel electrode 41 is formed along a position of a pixel designed in a matrix manner on the second transparent substrate 1b. The pixel electrode 41 faces the common electrode 8 formed on the color filter panel 3 and serves as the other electrode forming an electric field applied to the liquid crystal 10. The signal wires 13 are formed along the horizontal array direction of the pixel electrodes 41, and the data wires 23 are formed along the vertical array direction. In the active matrix liquid crystal display device, a thin film transistor 19 which is a switch element for applying an electric field signal to the pixel electrode 41 is formed in one corner of the pixel electrode 41. In the case of an active matrix liquid crystal display device, the gate electrode 11 of the thin film transistor 19 is connected to the signal wiring 13 (hence, the signal wiring is also referred to as "gate wiring"), and the source electrode ( 21 is connected to the data line 23 (hence the data line is also referred to as the "source line"). The drain electrode 31 of the thin film transistor 19 is connected to the pixel electrode 41. In the thin film transistor 19, a semiconductor layer 33 is formed between the source electrode 21 and the drain electrode 31, and the source electrode 21, the semiconductor layer 33, the drain electrode 31, and the semiconductor layer are formed. 33 each make an ohmic contact. At the ends of the gate wiring 13 and the source wiring 23, gate pads 15 and source pads 25, which are terminal terminals (or terminals) for receiving signals applied from the outside, are formed, respectively. Further, a gate pad terminal 57 and a source pad terminal 67 are further formed on the gate pad 15 and the source pad 25, respectively.

When an external electrical signal applied to the gate pad 15 is applied to the gate electrode 11 along the gate wiring 13, image information applied to the source pad 25 is source electrode 21 along the source wiring 23. Is applied to the drain electrode 31. On the other hand, when no signal is applied to the gate wiring 13, the source electrode 21 and the drain electrode 31 are disconnected. Therefore, whether the data signal is applied to the drain electrode 31 can be determined by adjusting the signal of the gate electrode 11. Therefore, the data signal can be artificially transferred to the pixel electrode 41 connected to the drain electrode 31. That is, the thin film transistor 19 serves as a switch for driving the pixel electrode. A gate insulating film 17 is formed between the layer on which the gate wiring 13 and the like are formed and the layer on which the source wiring 23 and the like are formed, and a protective film for protecting the device even on the layer on which the source wiring 23 and the like are formed. (37) is formed.

The two panels thus made (the color filter panel 3 and the active panel 5) are opposed to each other at a predetermined interval (referred to as "cell gap"), and the liquid crystal material ( 10) is filled. In order to keep the cell gap between the two panels 3 and 5 constant and to prevent the liquid crystal material from leaking out, the edge portions of the two substrates are sealed with a seal 81 such as epoxy. Thus, the liquid crystal panel which is the main part of the liquid crystal display device is completed.

In such a liquid crystal panel, an active panel having a TFT and a pixel electrode, which are a switching element that plays a key role in driving liquid crystal, is most important. Therefore, how the active panel is made or the performance of the active panel has a decisive influence on the overall quality of the liquid crystal panel. Therefore, almost all technologies related to liquid crystal display devices are focused on how to make an active panel. The invention also relates to a method of making an active substrate, in particular a method of making it in a four mask process using a diffraction exposure technique. The conventional method for producing an active substrate using the diffraction exposure technique according to the present invention and its problems are as follows. For the sake of understanding, a conventional method of manufacturing an active substrate will be described with reference to FIG. 3, which is a plan view of the active panel, and FIG.

Aluminum or an aluminum alloy is deposited on the transparent glass substrate 1 and patterned to form a gate wiring 13 connecting the gate electrode 11 and the gate electrode 11. A gate pad 15 is formed at an end of the gate wiring 13. The gate electrode 11 is disposed at one corner of the designed pixel, and the gate wiring 13 is arranged in the row direction. (11) are connected (FIGS. 3 and 4A).

A gate insulating layer including an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 1 on which the gate material (gate electrode 11, gate wiring 13, and gate pad 15) is formed ( 17), a semiconductor material 33a such as intrinsic amorphous silicon, an impurity semiconductor material such as amorphous silicon to which impurities are added, and a metal such as chromium, molybdenum or the like are successively deposited. The metal layer is patterned to form a source electrode 21, a drain electrode 31, a source wiring 23, and a source pad 25. The impurity semiconductor material is also etched simultaneously when the source-drain material (the source electrode 21, the drain electrode 31, and the source wiring 23) is formed to be formed under the source electrode 21 and the drain electrode 31. An impurity semiconductor layer 35 in ohmic contact with the semiconductor material 33a is formed. The source electrode 21 and the drain electrode 31 are formed so as to overlap both sides of the gate electrode 11 (FIGS. 3 and 4B).

A protective layer 37 including an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the substrate 1 on which the source-drain material is formed. In the first portion where the source electrode 21 and the drain electrode 31 are formed by using a diffraction exposure technique, all materials below the protective layer 37 remain as they are, and the protective layer is formed on the second portion where the gate wiring 13 is formed. 37 and the semiconductor material 33a are etched so that only the gate insulating film 17 remains, and the other third portion of the protective film 37, the semiconductor material 33a, and the gate insulating film 17 are all etched away. Let (1) be exposed. The fourth portion, which is a part of the drain electrode 31, removes the passivation layer 37 to form a drain contact hole 71 exposing the drain electrode 31. The diffraction exposure technique is used to change the degree of etching according to the portion in one mask process.

The detailed technique is as follows. First, the photoresist 91 is coated on the protective film 37 by about 2 μm. The photoresist 91 is covered with a mask 93 and then exposed to light such as ultraviolet rays. In one example, the first portion is fully open because the photoresist must remain completely, and the second portion has a lattice opening pattern 95 to leave the photoresist only a small thickness. The part should be free of photoresist, so it is exposed using a mask completely masked. The grating open pattern 95 has a grating spacing suitable for the diffraction exposure technique. That is, it has a grid space | interval narrower than the resolution of the light source used for photosensitive. After the photoresist development, the photoresist 91 remains about 2 μm in the first part, and the photoresist 91 is about the same thickness as the gate insulating film 17 by using a diffraction exposure technique in the second part. Adjust from 2000 to 4000Å left. The protective film is exposed to the third and fourth portions without the photoresist 91 as it is. In this case, in order to expose a part of the drain electrode 31, the photoresist 91 should not be present on a part of the protective film 37 covering the drain electrode (FIGS. 3 and 4C).

When etching is performed in this state, while the protective film 37, the semiconductor material 33a, and the gate insulating film 17 are etched in the third part, the photoresist 91, the protective film 37, and the semiconductor material 33a in the second part. ) Is etched, and only the photoresist 91 is etched in the first portion, leaving only about 2000 to 5000 microns. On the other hand, the protective film 37 which covers the 4th part which is a part of drain electrode 31 is removed. Since the drain portion 31 is a metal after the fourth portion is etched away, the etching solution for etching the passivation layer 37, the semiconductor material 33a, and the gate insulating layer 17 is not affected. As a result, a semiconductor layer 33 is formed in the gate electrode 11 portion, the gate wiring 13 is insulated and protected by the gate insulating film 17, and the drain contact hole 71 exposing the drain electrode 31. Is formed. Then, the gate contact hole 51 exposing the gate pad 15 and the source contact hole 61 exposing the source pad 25 are formed. (FIGS. 3 and 4D).

Indium tin oxide (ITO), which is a transparent conductive material, is deposited and patterned to form a pixel electrode 41 contacting the drain electrode 31 through the drain contact hole 71. The pixel electrode 41 is formed in direct contact with the glass substrate 1. In addition, a gate pad terminal 57 contacting the gate pad 15 through the gate contact hole 51 and a source pad terminal 67 contacting the source pad 25 through the source contact hole 61. ) Is formed (FIGS. 3 and 4E).

By using the diffraction exposure technique, the number of mask processes can be reduced by continuously etching the protective film, the semiconductor material, and the gate insulating film while varying the degree of partial etching as necessary. However, the protective film using the diffraction exposure technique. When the semiconductor layer and the gate insulating layer are patterned, the three layers are similar to each other, but the etching rate is slightly different, so the pattern is not formed as designed. In particular, some of the gate insulating film covering the gate wiring may be etched to some extent while the gate insulating film covering the gate pad is etched to form the gate contact hole exposing the gate pad. The thinned gate insulating film does not completely protect the gate metal material such as the gate wiring under it, and the gate material may be attacked and eroded by the etchant. As a result, a problem such as shorting of the gate wiring may occur in a subsequent process. These problems eventually cause various kinds of deterioration of the quality of the liquid crystal display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method in which a gate insulating film is not etched at a portion using a diffraction exposure in a liquid crystal display device manufacturing method so that the original thickness can be maintained as it is. Another object of the present invention is to provide a method of minimizing the amount of etching of the gate insulating film in the portion using the diffraction exposure. It is still another object of the present invention to provide a method in which the gate insulating film maintains its original thickness almost in the portion where diffraction exposure is used so that the underlying gate material can be completely protected from erosive materials such as etchant. .

1 is a perspective view illustrating a structure of a general liquid crystal display device.

2 is a cross-sectional view illustrating a structure of a general liquid crystal display device.

3 is a plan view illustrating a general liquid crystal display device.

4 is a cross-sectional view illustrating a conventional method for manufacturing a liquid crystal display using a diffraction exposure technique.

5 is a plan view showing a liquid crystal display device according to the present invention.

6 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display using the diffraction exposure technique according to the present invention.

<Description of the reference numerals for the main parts of the drawings>

1, 101: substrate 11, 111: gate electrode

13, 113: gate wiring 15, 115: gate pad

17, 117: gate insulating film 21, 121: source electrode

23, 123: source wiring 25, 125: source pad

31 and 131: drain electrodes 33 and 133: semiconductor layer

35, 135: impurity semiconductor layers 37, 137: protective film

41, 141: pixel electrode 51, 151: gate contact hole

57, 157: gate pad terminals 61, 161: source contact holes

67 and 167: source pad terminals 71 and 171: drain contact hole

91, 191: photoresist 93, 193: mask

195 grid pattern

In order to achieve the above object, the present invention applies a photoresist to a substrate on which a gate insulating film, a semiconductor layer, and a protective film are stacked, and is exposed and developed with a mask including a lattice-opening pattern. And the lattice pattern is applied to form a second portion of the photoresist remaining less than half of the first portion and a third portion in which the photoresist is not left at all, and to minimize the oxygen content and mainly include the F group. Etching the substrate on which the photoresist is formed with an etchant until the insulating layer and the semiconductor layer of the third portion are removed by a plasma dry etching method; and dry etching the plasma substrate with a plasma etchant including O ₂ and F groups to form the second portion. Removing the photoresist and the protective film, and removing the gate insulating film of the third portion; The plasma etchant Trojan dry etching comprises providing a liquid crystal display device manufacturing method comprising the step of removing the second portion and a semiconductor layer only on the third portion. In particular, the etching process of the three steps of the present invention is achieved by changing the etching etchant in one continuous etching process. Hereinafter, a method of manufacturing a liquid crystal display device according to an embodiment and the present invention will be described with reference to FIGS. 5 and 5. It will be described in detail with reference to Figure 6 which is a cross-sectional view taken along the cutting line VI-VI.

Aluminum or an aluminum alloy is deposited on the transparent glass substrate 101 and patterned to form a gate wiring 113 connecting the gate electrode 111 and the gate electrode 111. In addition, a gate pad 115 is formed at an end of the gate line 113. The gate electrode 111 is disposed at one corner of the designed pixel, and the gate wiring 113 connects the gate electrodes 111 arranged in the row direction.

A gate insulating layer including an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 101 on which the gate material (gate electrode 111, gate wiring 113, and gate pad 115) is formed. 117, a semiconductor material 133a such as intrinsic amorphous silicon, an impurity semiconductor material such as amorphous silicon to which impurities are added, and a metal such as chromium, molybdenum, and the like are successively deposited. The metal layer is patterned to form a source electrode 121, a drain electrode 131, and a source wiring 123. The impurity semiconductor material is also etched at the same time when the source-drain material (the source electrode 121, the drain electrode 131, and the source wiring 123) is formed, under the source electrode 121 and the drain electrode 131. An impurity semiconductor layer 135 in ohmic contact with the semiconductor material 133a is formed. The source electrode 121 and the drain electrode 131 are formed to overlap both sides of the gate electrode 111, respectively.

A protective layer 137 including an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the substrate 101 on which the source-drain material is formed. All materials below the passivation layer 137 remain in the first portion where the source electrode 121 and the drain electrode 131 are formed, and the passivation layer 137 and the semiconductor material 133a in the second portion where the gate wiring 113 is formed. ) Is etched so that only the gate insulating layer 117 remains, and the other third portion of the protective layer 137, the semiconductor material 133a, and the gate insulating layer 117 are etched to expose the glass substrate 101. The fourth portion, which is a part of the drain electrode 131, removes the passivation layer 137 to form a drain contact hole 171 exposing the drain electrode 131. The diffraction exposure technique is used to change the degree of etching according to the portion in one mask process. The detailed method is as follows. First, the photoresist 191 is coated on the protective film 137 by about 2 μm. The photoresist 191 is covered with a mask 193 and then exposed to light such as ultraviolet rays. For example, the photoresist 191 must be completely left in the first part, so that the photoresist 191 is fully open, and the second part has a lattice opening pattern 195 to leave the photoresist 191 only a little thickness. The third and fourth portions should be free of photoresist and are then exposed using a fully shielded mask 193. The lattice opening pattern 195 has a lattice spacing narrower than the resolution of a light source used for dimming so as to have a lattice spacing suitable for diffraction exposure technique. After the photoresist 191 is developed, the first portion of the photoresist 191 remains about 2 μm, and in the second portion, the photoresist 191 is formed using the diffraction exposure technique. Adjust it to about a thousand millimeters (4000 to 5000 millimeters) of 1/4 of the thickness. Up to now, it is the same as a conventional manufacturing process, and has a form like FIG. 4C (FIG. 5, FIG. 6A).

Then, the substrate on which the photoresist is formed is inserted into a dry etching chamber, and the etching process is performed in three steps as follows. First, the protective film 137 and the semiconductor material 133a are drawn in the third portion, and the protective film 137 is removed in the fourth portion, using a plasma etchant containing almost no O ₂ component and mainly containing F groups. . A drain contact hole 171 exposing the drain electrode is formed in the fourth portion. At this time, since there is almost no O ₂ component, there is almost no change in the thickness of the photoresist 191 (FIGS. 5 and 6B).

Then, the photoresist 191 and the protective film 137 are removed in the second part and the gate insulating film 117 in the third part with a plasma etchant containing O ₂ and F groups. The photoresist 191 is ashed and removed by the oxygen plasma, and the protective film 137 and the gate insulating film 117 are removed by the plasma of F group. As a result, the gate contact hole 151 exposing the gate pad 115 is formed in the third portion. At this time, the photoresist 191 of the first portion is also ashed by O ₂ , and the thickness is removed to some extent (FIGS. 5 and 6C).

Finally, the semiconductor layer of the second portion is removed with a plasma etchant containing little O ₂ and containing F and Cl groups. At this time, since the etchant contains little O ₂ , the photoresist 191 remains in the first portion. After removing the remaining photoresist 191, the drain contact hole 171 exposing the drain electrode 131, the source contact hole 161 exposing the source pad 125, and the gate pad 115 are removed. An exposed gate contact hole 151 is formed (FIGS. 5 and 6D).

The three-step etching process is performed at once by using only different plasma etchant for each step in the same etching chamber.

Indium tin oxide (ITO), which is a transparent conductive material, is deposited and patterned to form a pixel electrode 141 contacting the drain electrode 131 through the drain contact hole 171. The pixel electrode 141 is formed in direct contact with the glass substrate 101. In addition, a gate pad terminal 157 that contacts the gate pad 115 through the gate contact hole 151 and a source pad terminal 167 that contacts the source pad 125 through the source contact hole 161. ) Is formed (FIGS. 5 and 6E).

The present invention relates to a method of manufacturing a liquid crystal display device in which the number of mask steps is shortened to four steps by using diffraction exposure, so that the gate insulating film is not thinned and remains almost at its original thickness. The diffraction exposure technique provides a method of etching the three layers differently using only one mask process to simultaneously pattern the passivation layer, the semiconductor layer, and the gate insulating layer. At this time, the gate insulating film is overetched to become thinner than the original thickness, and thus the gate insulating film does not completely protect the gate material under it. In the present invention, a method of leaving the gate insulating film close to the original thickness by applying three etching processes using different etching etchant in patterning the protective film, the semiconductor layer and the gate insulating film in one mask process by diffraction exposure technique. To provide. According to the present invention, the gate material can be completely protected from the etchant by the gate insulating film. Therefore, in the present invention, defects and problems in which the gate material is broken do not occur.

Claims (5)

Forming a gate material from the first metal on the substrate; Continuously depositing a first insulating material, a semiconductor material, and a second metal on the gate material, and patterning the second metal to form a source-drain material; Forming a second insulating material over the source-drain material; Applying a photoresist on the second insulating material, and using a diffraction exposure, a first portion where the photoresist remains completely, a second portion where the photoresist remains about 1/4 to 1/2, and the photo Forming a third portion from which the resist has been completely removed; After removing the protective layer, the second insulating material and the semiconductor material in the third portion with a first etchant, the photoresist and the second insulating material in the second portion with a second etchant and the first insulation in the third portion. After removing the material, removing the semiconductor material from the second portion with a third etchant to complete the thin film transistor. The method of claim 1, And forming a pixel electrode connected to the drain electrode of the thin film transistor with a conductive material on the substrate on which the thin film transistor is completed. The method of claim 1, The first etchant O ₂ is scarcely contained, the liquid crystal display device manufacturing method characterized in that a plasma etchant, including an open F. The method of claim 1, And the second etchant is a plasma etchant comprising O ₂ and F groups. The method of claim 1, The third etchant is a plasma etchant containing almost no O ₂ and comprising a F group and a Cl group.