KR20020075486A - Multi chip package for semiconductor - Google Patents

Abstract

PURPOSE: A multi-chip package for a semiconductor is provided to reduce an error rate in a package fabrication process by providing the multi-chip package for semiconductor bonded with an inner lead of a lead frame. CONSTITUTION: The first semiconductor chip(120) is adhered on a paddle including a lead frame(110) and a substrate by using an adhesive. The second semiconductor chip(130) is adhered on an upper face of the first semiconductor chip(120) by using the adhesive. A plurality of metal pads(150,155) are arranged on each edge of the first and the second semiconductor chips(120,130), respectively. The metal pad(150) of the first semiconductor chip(120) has a shape of right-angled tetragon. The metal pad(155) of the second semiconductor chip(130) has a shape of a regular quadrilateral. The metal pad(155) of the second semiconductor chip(130) is bonded with the metal pad(150) of the first semiconductor chip(120) by using a metal line.

Description

Multi-chip package for semiconductors {MULTI CHIP PACKAGE FOR SEMICONDUCTOR}

The present invention relates to a multi-chip package for a semiconductor, and more particularly, to a semiconductor chip in which a plurality of semiconductor chips are mounted in a structure in which chips are stacked on a chip having a different size (chip on chip structure). It's about packages.

As is already known, a technology of manufacturing a plurality of semiconductor chips into one package may be largely classified into a chip to chip structure and a chip on chip structure.

1A and 1B are longitudinal cross-sectional views and cross-sectional views of a semiconductor multi-chip package according to a first embodiment of the present invention, and correspond to a chip-to-chip structure.

In the multi-chip package 10 according to the present exemplary embodiment, the first semiconductor chip 12 and the second semiconductor chip 13 are disposed on the same surface on the paddle 18 including the lead frame 11 and the substrate. It is attached by this adhesive (Adhesive) 14. A plurality of metal pads 15 for electrical connection to the outside are arranged at the edges of the first and second semiconductor chips 12 and 13, and the metal pads 15 are lead frames 11 with respective metal wires 16. Wire bonds with the inner leads 11a of the < RTI ID = 0.0 >), < / RTI > the inner leads 11a are electrically connected to the outside by the outer leads 11b formed integrally therewith. Each of the devices is encapsulated and protected by an EMC (Epoxy Molding Compound) 17.

However, in the chip-to-chip multi chip package described above, in order to mount a plurality of semiconductor chips on a paddle, the paddle size must be larger than the size of single chip pads, and sagging at the edge facing another semiconductor chip. Metal pads cannot be arranged due to problems such as sweeping and sweeping.

Therefore, the size of the package must be relatively large, and when applied to a package having a large number of pins, the metal pad pitch becomes small, which causes difficulty in manufacturing the package.

In the current trend of thin and short semiconductor products, a new structure of multi-chip package that can reduce the package mounting area is required. In this regard, the chip-on-chip multi-chip package has the advantage of miniaturizing the package. Has

2A and 2B are longitudinal cross-sectional views and cross-sectional views of a multi-chip package for a semiconductor according to a second exemplary embodiment, and correspond to a chip-on-chip structure. In addition, the same reference numerals are designated for the same components as the multi-chip package of FIG. 1 for better understanding of the description.

In the multi-chip package 10 according to the present exemplary embodiment, the first semiconductor chip 12 is attached to the upper surface of the paddle 18 including the lead frame 11 and the substrate by the adhesive 14, and the first semiconductor chip ( 12) The second semiconductor chip 13 of smaller size is attached to the upper surface of the first semiconductor chip 12 with an adhesive 14. A plurality of metal pads 15 for electrical connection to the outside are arranged at the edges of the first and second semiconductor chips 12 and 13, and the metal pads 15 are lead frames 11 with respective metal wires 16. Wire bonds with the inner leads 11a of the < RTI ID = 0.0 >), < / RTI > the inner leads 11a are electrically connected to the outside by the outer leads 11b formed integrally therewith. Each of the elements is encapsulated and protected by the EMC 17.

However, the above-described multi-chip package of chip-on-chip structure according to the prior art has to make very low loop control, higher wire loop and longer wire length during wire bonding of the second semiconductor chip, thereby creating EMC molding. Problems such as sagging of wires and sweeping phenomenon appear. In addition, since the metal pads of the first and second semiconductor chips are connected to the internal leads, respectively, the number of the external pins increases, which leads to difficulties in manufacturing the external pins and high manufacturing costs.

The present invention has been proposed to solve such a conventional problem, and a plurality of semiconductor chips having different sizes are mounted in a chip-on-chip structure, and a metal pad of a semiconductor chip mounted on the upper side is a metal of the semiconductor chip mounted on the lower side. By providing a multi-chip package for semiconductors wire-bonded to the inner lead of the lead frame via pads, the package can be made thin and short, and the process can be simplified, and the defects in manufacturing a semiconductor package according to the prior art are eliminated. There is this.

In the multi-chip package for a semiconductor according to the present invention for realizing the above object, a plurality of semiconductor chips in which a plurality of metal pads for the electrical connection to the outside is arranged on the edge of a paddle including a lead frame and a substrate A multi-chip package, comprising: a first semiconductor chip attached to an upper surface of the paddle with an adhesive, and a second semiconductor chip having a smaller size than the first semiconductor chip attached to the upper surface of the first semiconductor chip; The metal pad of the second semiconductor chip is wire-bonded to the metal pad of the first semiconductor chip with a metal wire to make an electrical connection, and the metal pad of the first semiconductor chip is wire-bonded to the inner lead of the paddle to be electrically connected to the outside. Make a connection.

1 is a longitudinal cross-sectional view and a cross-sectional view of a multi-chip package for a semiconductor according to a first embodiment of the present invention;

2 is a longitudinal cross-sectional view and a cross-sectional view of a multi-chip package for a semiconductor according to a second embodiment of the present invention;

3 is a longitudinal sectional view and a cross sectional view of a multi-chip package for a semiconductor according to a first embodiment of the present invention;

4 is a longitudinal cross-sectional view and a cross-sectional view of a multi-chip package for a semiconductor according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200: multi-chip package 110: lead frame

111: internal lead 112: external lead

120,130,201: semiconductor chip 140: adhesive

150,155: metal pad 160: metal wire

161: ball 170: EMC

180: paddle

There may be a plurality of embodiments of the present invention. Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. This embodiment allows for a better understanding of the objects, features and advantages of the present invention.

3A and 3B are longitudinal cross-sectional and cross-sectional views of a multi-chip package for a semiconductor according to a first embodiment of the present invention.

In the multi-chip package 100 according to the present exemplary embodiment, the first semiconductor chip 120 is attached to the upper surface of the paddle 180 including the lead frame 110 and the substrate by the adhesive 140, and the first semiconductor chip ( A second semiconductor chip 130 having a smaller size than 120 is attached to the top surface of the first semiconductor chip 120 with an adhesive 140. Here, the second semiconductor chip 130 is attached to be spaced apart by at least 50 μm or more from the arrangement position of the metal pad 150 of the first semiconductor chip 120, and used when attaching the first and second semiconductor chips 120 and 130. The adhesive 140 is a polymer series having electrical and thermal non-conductivity, and in particular, the adhesive 140 attaching the second semiconductor chip 130 protrudes within 25 μm from the outer circumference of the second semiconductor chip 130.

Here, the adhesive 140 is an adhesive mounting thin film that is bonded during curing so that the thin film used in the wafer mount can be used as it is.

Thus, by stacking and mounting a plurality of semiconductor chips (120, 130) in a paddle of a small size, the package size is reduced compared to the conventional chip-to-chip structure, it is possible to manufacture a standard substrate to reduce the cost.

The plurality of metal pads 150 and 155 for electrical connection to the outside are arranged at edges of the first and second semiconductor chips 120 and 130, and the metal pads 150 of the first semiconductor chip 120 have a rectangular shape on a plane basis. In other words, the length of the short side is 50 μm or more, and the length of the long side is 150 μm or more, and the balls 155 of the wire bonding are arranged side by side.

In addition, the metal pads 150 of the first semiconductor chip 120 are arranged such that the long sides thereof are horizontal or vertical to the metal pad arrangement rows. Preferably, the metal pads 150 of the first semiconductor chip 120 are horizontal or vertical depending on the number of pins of the first or second semiconductor chips 120 and 130. Arranged vertically.

In detail, when the packaging of the small number of pins or the size of the second semiconductor chip 130 is large, the metal pad 150 of the first semiconductor chip 120 is horizontally aligned with the long-sided metal pad arrangement sequence as shown in FIG. 4B. If the size of the packaging or the number of the second semiconductor chip 130 is small, the metal pad 150 of the first semiconductor chip 120 has a long side of the metal pad arrangement sequence as shown in FIG. It is arranged to be vertical.

In addition, the metal pad 155 of the second semiconductor chip 130 has a square shape on a planar basis and is 50 μm × 50 μm to 100 μm × 100 μm when the size is expressed as “horizontal × vertical”. And the thicknesses of the second semiconductor chips 120 and 130 are 5 mm to 15 mm.

In addition, the metal pads 150 and 155 of the first and second semiconductor chips 120 and 130 may have a diameter of the ball 161 of the wire bonding of 40 μm to 90 μm, and a diameter of the ball of the stitch bonding (not shown) of 40 μm to 85 μm. Μm. In addition, the metal pads 155 of the second semiconductor chip 130 are wire-bonded to the metal pad 150 of the first semiconductor chip 120 by a metal wire 160 to make an electrical connection, and the first semiconductor chip 120 The metal pad 150 is wire-bonded to the inner lead 111 of the lead frame 110 to be electrically connected to the outside through an external lead 112 integrated with the inner lead 111.

Here, preferably, the wire loop height bonded to the metal pad 150 of the first semiconductor chip 120 is 6 mil or more, and the wire loop height bonded to the metal pad 155 of the second semiconductor chip 130 is 4 mil or more. .

As such, the present invention prevents wire sagging and sweeping during EMC molding by inter-chip wire bonding, and ensures reliability of substrate design. In addition, since the second semiconductor chip 130 avoids direct connection with the internal lead 111, the process simplification and defects are eliminated, and the electrical connection of the second semiconductor chip 130 can be connected with a short wire so that the high Signal characteristics are secured.

Each of the devices is sealed and protected by the EMC 170.

4A and 4B are longitudinal cross-sectional views and cross-sectional views of a multi-chip package for a semiconductor according to a second embodiment of the present invention. For the sake of understanding, the same components as those of the multi-chip package of FIGS. 3A and 3B are referred to. The sign is specified.

In the multi-chip package 200 according to the present exemplary embodiment, the first to third semiconductor chips 120, 130, and 201 may be stacked as described above with reference to FIGS. 3A and 3B, as can be easily understood through comparison with FIGS. 3A and 3B. The pads 180 are attached to the furnace paddle 180, and the metal pads 150 and 155 are also wire bonded to the inner lead 111 by the connection structure described above with reference to FIGS. 3A and 3B. As described above, the multi-chip package of the present invention can stack not only two or three semiconductor chips described with reference to FIGS. 3A, 3B, 4A, and 4B but also a larger number of semiconductor chips.

As described above, the present invention reduces the package size compared to the conventional chip-to-chip structure, and can reduce the cost by manufacturing a standard substrate.

In addition, it prevents wire sagging and sweeping during EMC molding, ensures reliability of substrate design, eliminates process simplification and defects, and secures high signal characteristics of the device.

Claims (12)

In a multi-chip package in which a plurality of semiconductor chips with a plurality of metal pads for electrical connection to the outside are mounted on one paddle including a lead frame and a substrate: A first semiconductor chip is adhesively attached to an upper surface of the paddle, and a second semiconductor chip of a smaller size than the first semiconductor chip is adhesively attached to an upper surface of the first semiconductor chip; The metal pad of the second semiconductor chip is wire-bonded to the metal pad of the first semiconductor chip with a metal wire to make an electrical connection, and the metal pad of the first semiconductor chip is wire-bonded to the inner lead of the paddle to be electrically connected to the outside. Multi chip package for semiconductors. The method of claim 1, wherein the metal pads of the first and second semiconductor chips, The ball diameter of wire bonding is 40 micrometers-90 micrometers, and the ball diameter of stitch bonding is 40 micrometers-85 micrometers, The chip package for semiconductors characterized by the above-mentioned. The method of claim 1, wherein the metal pad of the first semiconductor chip, The multi-chip package for a semiconductor, characterized in that the ball of the wire bonding is arranged side by side with a rectangular shape on a plane basis. The method of claim 3, wherein the metal pad, A short side has a length of 50 μm or more, and a long side has a length of 150 μm or more. The method of claim 3, wherein the metal pad, A multi-chip package for semiconductors, wherein the long sides are arranged to be horizontal or vertical to the metal pad arrangement rows. The method of claim 5, wherein the metal pad, The multi-chip package for a semiconductor, characterized in that arranged in a horizontal or vertical according to the number of pins of the first or second semiconductor chip. The method of claim 1, wherein the metal pad of the second semiconductor chip, A semiconductor chip having a square shape on a planar basis and having a size of "width x length", which is 50 µm x 50 µm to 100 µm x 100 µm. The method of claim 1, wherein the thickness of the first and second semiconductor chips, A multi-chip package for semiconductors, characterized in that 5mm to 15mm. The method of claim 1, wherein the second semiconductor chip, The semiconductor package of claim 1, wherein the first semiconductor chip is attached at least 50 μm apart from the metal pad arrangement position. The method of claim 1, wherein the adhesive, A multi-chip package for semiconductors, which is a polymer series which is electrically and thermally non-conductive. The adhesive according to claim 1, wherein the adhesive to attach the second semiconductor chip is The multi-chip package for a semiconductor, characterized in that protruding within 25㎛ from the outer circumference of the second semiconductor chip. The method of claim 1, The height of the wire loop bonded to the metal pad of the first semiconductor chip is 6mil or more, and the height of the wire loop bonded to the metal pad of the second semiconductor chip is 4mil or more.