KR20020059777A - Preparation of data for a reed-solomon decoder - Google Patents

Abstract

The present invention relates to a method and apparatus for preparing data for a Reed-Solomon decoder, and more particularly, to a method and apparatus for an intelligent buffer (IBUF) in front of a RAM member DVD Reed-Solomon decoder. In particular it relates to a method and apparatus for an intelligent buffer (IBUF) which is also used as a first pass correction storage of an ECC-block. In such a method, the Reed-Solomon decoder will not obtain a disordered ECC block through an intelligent buffer (IBUF) that leads to a high performance and less required RAM of a complete circuit. The intelligent buffer IBUF is also used as the first pass correction storage of the Reed Solomon decoder.

Description

Apparatus and method for preparing data for a Reed-Solomon decoder {PREPARATION OF DATA FOR A REED-SOLOMON DECODER}

Conventional pre-processing buffers and Reed-Solomon use a common RAM to process corrupted data. Such apparatus and processing are used, for example, to correct data stored on optical information media such as DVDs for playback. It is desirable to apply corrupted data to the Reed-Solomon decoder, to use RAM to store ECC blocks, and to avoid several faulty reads that reduce the speed of the data path. DVD stands for Digital Versatile Disc, and ECC stands for Error Correction Code, an electronic method of checking data integrity.

The data of the ECC is organized hierarchically into pieces of the data stream. The highest unit is the ECC-block, which is divided into a number of sectors. Each sector consists of a number of rows with a fixed length. In order to enable correction of the stream, a number of parity bytes are appended to each row, and the number of additional bytes determines the number of correctable fault faults per row. In addition to this horizontal correction function, the same calculation is performed vertically for all bytes of the ECC-block at the same position in one row, and the result is organized in additional rows of the ECC-block.

In order to control the order of the sectors, the first byte contains identification information. The blocks in front of the buffer and Reed-Solomon part acquire a stream within the frame, where two frames constitute a row, the identification of the frame order is evaluated, and the result is made available to the buffer by the appropriate sync-signal. .

Conventional apparatus stores data in a common RAM for identification control results before the Reed-Solomon decoder begins to correct the corrupted data bytes. Replacing faulty data in memory will require significant processing costs and will significantly reduce system performance.

RAM stands for random access memory. It is a temporary storage area that the processor uses to run programs and maintain data. Reed Solomon is a technical term for a forward error correction code used to offset the effects of bit errors in the receive bit stream. Reed-Solomon code is special and widely implemented because it is almost perfect in that no bits are wasted because the number of extra redundant data added by the encoder is minimal for any level of error correction. .

The present invention relates to a method and apparatus for preparing data for a Reed-Solomon decoder, and more particularly, to a method and apparatus for an intelligent buffer in front of the Reed-Solomon decoder that requires less RAM and guarantees high performance. It is about.

1 is a block diagram of an intelligent buffer in front of a RAM member DVD Reed-Solomon decoder, with some drive circuitry.

2 is a schematic diagram of a forward jump when addr_in> addr_out.

3 is a schematic diagram of a forward jump when addr_in <addr_out.

4 is a schematic diagram of a backward jump when addr_in> addr_out.

5 is a schematic diagram of a backward jump when addr_in <addr_out.

Fig. 6 shows the input-address and the output-address in case of jump in sector ID.

SUMMARY OF THE INVENTION An object of the present invention is a method and apparatus for a Reed-Solomon decoder that guarantees high performance while requiring less RAM by avoiding data replacement in memory that would significantly reduce the performance of the system while requiring processing costs. To provide. The features mentioned in the independent claim solve this problem. The dependent claims disclose preferred embodiments. According to one aspect of the invention, there is provided a method and apparatus for an intelligent buffer in front of a Reed-Solomon decoder, such as a DVD Reed-Solomon decoder, in which data is analyzed based on incoming sync-signals. The data is buffered at the appropriate buffer location, as long as the incoming ECC-block can be recovered by the Reed-Solomon decoder. If the ECC-block cannot be corrected, the Reed-Solomon decoder obtains a reset signal to cancel the first processing step. An address control block and a buffer form the intelligent buffer.

In the case of a Reed Solomon decoder without RAM, i.e. in the case of a so-called RAM-free Reed Solomon according to the invention, the front-end circuit is adapted to transmit a complete incoming ECC-block as a continuous data stream to the Reed-Solomon decoder. There is no way to save earlier. If no precaution is taken, the Reed-Solomon decoder will acquire many chaotic ECC-blocks that the decoder cannot correct. This leads to poor performance of the complete circuit. The intelligent buffer in front of the Reed-Solomon-decoder according to the present invention attempts to keep the structure of the data intact, eliminates small defects, and if the defects cause corrupted data, the Reed-Solomon block and the microcontroller are corrupted. You will be notified about the data. Since the RAM member Reed-Solomon block used has scalable parameters, the Reed-Solomon buffer interface is effective in other situations. The classification of data and lack of motivation is also valid for other block codes. The buffer is a small room for data storage. The buffer is located between two units that exchange data with each other. The function of the buffer is to provide a room for temporarily storing data from one unit in situations where the other unit is not ready to receive data. The buffer holds these data for a while and then delivers them as soon as the receiver is ready to receive them. In the case of a DVD-player, for example, data coming from the acquirer must be buffered before it can be passed to the Reed-Solomon correction block to compensate for minor defects in the PLL. PLL is an acronym for phase locked loop. For this reason, the acquisition section decodes the sector identification and frame header from the incoming HF-signal and sends the information along with the data to the buffer section. In such a manner, the buffer is generally necessarily present in front of the Reed Solomon decoder, which is advantageously used according to the invention.

The buffer block must be able to resynchronize the data stream at the frame and sector boundaries in order to prevent inappropriate frame lengths from damaging Reed-Solomon. In the case of a non-correctable jump, the buffer block stops the current first pass internal / external correction of the Reed-Solomon decoder and then resynchronizes at the ECC-block boundary. The Reed-Solomon-Buffer interface must be reset in case of a physical jump. In an improved embodiment, an intelligent buffer is used for Reed Solomon correction of the first stage of processing rows of ECC-blocks. Only some constraints on allowed jump areas should be considered. In that manner, a RAM-based Reed-Solomon decoder is advantageously performed that has high performance but requires less RAM-memory.

The invention will now be described with reference to the accompanying drawings.

In FIG. 1, the following three parts are shown to illustrate the function of the intelligent buffer IBUF in front of the RAM member Reed Solomon decoder, not shown.

The first part is an acquisition block (ACQ) that provides a clock (byte_clk) of incoming data, data (data_in) on the data line, and synchronization information.

The second part is an address control block (ADC) which generates an address and a control signal from the synchronization signal provided from the acquisition block (ACQ), which includes an address for the input data stream on the data line (data_in) and a buffer (BUF). There is an address of a control-output-signal (ctrl_out) for output data (data_out) that is transmitted from Rep.

The third part is a buffer BUF configured as a storage array with dual ports for processing independent time structures for output data (data_out) and incoming data (data_in) on data lines. It can also be configured as an IO-port if the input-data stream and the output-data stream are properly disconnected.

The address control block ADC and the buffer BUF form a so-called intelligent buffer IBUF according to the present invention. The other block represents a generator (clk_gen) for generating an independent clock (out_clk) used for the output data (data_out) stream. This task represents part of the Reed-Solomon decoder, not shown.

As shown in FIG. 1, the generator clk_gen is connected to an address control block ADC and a buffer BUF to provide an independent clock out_clk, and the independent clock out_clk is unloaded from the buffer BUF. It is also used to read data into the Reed Solomon block shown. Another clock byte_clk of incoming data (data-in) is derived from the acquisition-block (ACQ) and applied to the address control block (ADC), and also to the buffer (BUF) through the AND-gate (&). The other input of the AND-gate (&) is connected to the output of an address control block ADC which provides a buffer-input-enable signal in_en, which is the buffer-input-enable signal in_en. The input terminal of the buffer BUF is input through the AND-gate (&) by a masked byte clock signal byte_clk_msk, which is formed by the AND-gate (&) and applied to a corresponding input terminal of the buffer BUF. Enable it. The data line data_in connects the corresponding output terminal of the acquisition block ACQ with the corresponding input terminal of the buffer BUF to provide the data to the buffer BUF when the data is generated in the acquisition block. The acquisition block ACQ and the address control block ADC are also the frame start signal nxfr, the frame address signal fr_addr decoded by the acquisition block ACQ, and the sector identifier also decoded by the acquisition block ACQ. (SID), next sector start signal (nxt_SID), valid sector identifier signal (SID_valid) indicating that the transmitted sector identifier (SID) has been correctly decoded by the acquisition block (ACQ), and in case of serious optical problems When there is a stop flag (stop_flag) for asynchronous stop of operation requested by the internal micro-controller, it is connected to each other to provide several signals for the address control block (ADC). The address control block ADC is connected to the buffer BUF, and a control-input signal ctrl_in including ECC-start, sector-start and frame-start, which are three-bit signals of the incoming data data_in through the data line. ), A buffer input address signal addr_in for input data, a buffer output address signal addr_out for output data data_out, and a read data data_out from the buffer BUF to a Reed Solomon decoder (not shown). The output operation enable signal out_en is provided to the buffer BUF. The address control block ADC also provides a signal RST_RS to stop or reset the Reed Solomon decoder in case of an illegal jump. The buffer BUF provides a control-output-signal ctrl_out including ECC-start, sector-start, and frame-start, which are three-bit signals of the output data data_out provided to the Reed Solomon decoder.

Acquisition block (ACQ) as shown in Fig. 1 represents an acquisition portion of a channel circuit called a channel IC, in which data for synchronization and several control signals must be extracted.

As an example, from a bit stream coming from the optical part of a DVD device, not shown, this block decodes the sector number identified by data (data_in), byte clock (byte_clk), frame address (fr_addr), and sector identifier (SID). do. If the frame number is disordered, the sequence representing the fault is replaced as in the current version of the acquisition part. The limited decoding of the sector identifier SID is classified by the valid sector identifier signal SID_valid equal to 1-pulse, regardless of the frame address decoding. This information is used to resynchronize the frame address to zero, even if the order is corrupted.

The address control block (ADC) as shown in FIG. 1 must perform major tasks. Three steps are used to generate the address for the buffer BUF:

First step: generating an expected frame address fr_addr and a sector identifier SID. Following the synchronization signal from the acquisition block ACQ, a counter for the expected frame address fr_addr and the sector identifier SID is set in the address control block ADC and incremented regardless of the current input in case of a fault. do. To follow the jump track, an internal expected ECC-counter is also used, which ideally should follow the ECC block of incoming data. This internal counter is incremented or decremented when the sector number exceeds zero. If the acquisition block ACQ provides only incomplete frame address fr_addr and a limited sector identifier SID and no ECC number, the most likely change in the expected address is assumed when a jump occurs. If a complete sector identifier (SID) is used, the most significant bit may also synchronize the ECC-counter.

The rules for how to handle jumps are:

If there is a destruction of a frame or sector, it does not jump more than half the frame / sector-length from its current position.

The following cases are possible to evaluate the ratio of the current length to the standard length when n is a properly chosen integer:

A. 0) The frame length is suitable, ie length / standard length = 1

1) The frame length is too long, n <length / standard length ≤ n + 1/2

2) The frame length is too long, n + 1/2 <length / standard length ≤ n + 1

3) Frame length is too short, 0 <length / standard length ≤ 1/2

4) Frame length is too short, 1/2 <length / standard length <1

B. 0) Frame address is appropriate

1) The frame address is invalid

C. 0) Sector identifier (SID) is appropriate

1) In the current ECC-block, the sector identifier (SID) is too small

2) In the next ECC-block, the sector identifier (SID) is too small

3) In the current ECC-block, the sector identifier (SID) is too large

4) In the previous ECC-block, the sector identifier (SID) is too large

D. 0) Sectors are good

1) Sector too short

2) The sector is too long.

If the acquisition block ACQ cannot find the frame address fr_addr in time, the acquisition block ACQ inserts one. If the next valid frame address is not found during the first half frame length, no frame address indicator is sent. This is the reason why different cases have been made in A with respect to a nominal length of 1/2. Some of these combinations may not occur in order to reduce the number of bits with a small number of combinations.

Step 2: Generate a buffer-input-address signal addr_in to write data to the buffer BUF.

Based on the expected address for the first stage ECC-block, sector identifier (SID), and frame address fr_addr, the circular counter for the input address is incremented over a range of buffer sizes. In the case of a jump, different methods must be performed according to the jump direction, the size of the jump, and the current address of the output stream, as will be described in detail below.

The process must be able to perform a jump, be able to interrupt the input until an address is reached, or be able to resynchronize the overall process until a new ECC-block starts.

Step 3: Generating an output address for reading the output data data_out from the buffer BUF to the Reed-Solomon decoder, not shown.

To ensure proper addressing, it is assumed that the independent output clock out_clk is faster than the input clock byte_clk. The input signal from the data line data_in and the output data data_out form a corresponding stream controlled by the enable-signal, and the output address addr_out will follow the input address addr_in at a distance. In an embodiment, a distance that is half the buffer size is used.

In the first restart case, when the output address corresponding to the buffer output address signal addr_out is set to 0, in this case, when the distance between the input address addr_in and the output address addr_out is smaller than the default distance. The output address addr_out process waits until its default distance is reached. If, due to the jump, the input address addr_in continues to increase the distance to the output address, addr_out is generated at the maximum output clock out_clk speed until the default distance is again reached.

In order to properly handle the jump, this process must be able to interrupt the operation either immediately or at a given address to perform address generation at full speed and resynchronize to zero as described below.

The buffer BUF as shown in FIG. 1 is a defined size RAM with dual ports in order to be able to be written and read asynchronously, or alternatively prevents input- and output-requests from occurring simultaneously. It consists of a control logic and one IO-port, which is necessary because the two clocks (clock_clk) and clock (out_clk) are completely independent of each other. Both inputs and outputs can be disabled to make clocking easier. When sync-data is acquired in an acquiring block (ACQ) and passed to the address control block (ADC), the sync data must be transferred to the Reed Solomon block followed by the RAM address generator block, so that the sync data is It must also be stored and transmitted synchronously with the output data (data_out).

The generator clk_gen is a generator of the independent clock out_clk for the output data data_out, and the output data data_out should have a frequency higher than the maximum frequency of the incoming data, that is, the clock byte_clk. The generation of the independent clock out_clk can be achieved by dividing the system clock used in the implementation by appropriate factors.

Jump processing:

The address jumps described above were categorized into data section boundaries. In order to find the best strategy for buffer addressing, a different classification than above should be used, because

The relevance of the current input and output buffer addresses,

A jump offset, meaning that the jump has compromised the integrity of the buffer data,

The amount of data transmitted for a while to the Reed-Solomon decoder in response to a request of whether the current ECC-block can be corrected anyway,

How soon the next synchronization occurs

This is because it must be considered from the viewpoint of.

Forward jump FWDJ is processed according to FIGS. 2 and 3, and reverse jump BKWJ is processed according to FIGS. 4 and 5.

These figures show a data axis 1 with markers ECC0, ECC1, ECC2 for ECC-boundary, and a buffer axis parallel to the data axis 1 with a start and end address indicated in area 5. 2) is shown. Arrows indicate the buffer range and buffer portion under output 6, which is empty for input 7. Also shown are a snapshot of the input address before the jump is requested 9 and an output address located at a nominal distance to the input address 8.

2 and 3 show that under a situation where the buffer-input-addr_in is higher than the buffer-output-addr_out as shown in FIG. 2, the buffer-input-addr_in is in FIG. As shown, the situation for the requested forward jump FWDJ is lower than the buffer-output-address addr_out. The requested first jump 3 will be aimed at any area, which will not compromise the above described integrity of the stored data as opposed to the second jump 4 which is longer than the first jump. Therefore, the latter case will not be performed, but the output must be accelerated until the next requested address is outside the forbidden range 6, or the complete ECC-block must be dropped. The decision depends on the progress and jump distance in completing the ECC-block.

4 and 5 show that under the situation where the buffer-input-addr_addr is higher than the buffer-output-addr_out as shown in FIG. 4, the buffer-input-addr_addr_in is in FIG. As shown, the configuration for a reverse jump (BKWJ) request under a situation lower than the buffer-output-address (addr_out) is shown. The shorter first jump 3 can continue the input towards the permitted range, but must stop the output until the distance between the input-address and the output-address is nominal. In the case of the longer second jump 4, the next requested input address of the buffer-input-address signal addr_in is directed towards the area not yet transmitted from the buffer BUF, if the last data has been corrupted, The output is stopped and the area of the output data is overwritten. Another strategy is to stop the input and output of the buffer BUF until the input-address of the buffer in the address signal addr_in is directed to the allowed area. In both strategies, possibly corrupted data 10 is already transmitted.

6 illustrates the operation of the embodiment and the output address for several jumps in input. 6 demonstrates that most jumps are smoothed.

6 shows the address range AR of the buffer BUF on the time axis t. The input address of the buffer in the address signal addr_in causes the output address of the buffer output address signal addr_out to follow at a certain distance despite a jump such as JMP that is clearly smoothed.

In the case of a physical jump, no use of the sector currently read will be made. In this case, the stop flag stop_flag is activated as shown in FIG. This does not matter whether the sector currently being read is complete or not. The address-process will be completely restarted in that case, and the signal RST_RS is generated to reset the Reed Solomon operation.

In the second, not shown embodiment, the buffer BUF is used simultaneously as a correction buffer for the first stage of the Reed Solomon decoder. The only difference from the above-described embodiment is that a single output address of the buffer-output-address signal addr_out in the first embodiment is

Calculate and perform a first stage internal correction of the Reed-Solomon decoder using the data stored in the buffer (BUF),

Calculate the syndrome of the first external correction,

Outputting corrected data in internal mode

There is a more limited range for jumps, as it must be considered that it is divided into three addresses that are dedicated.

The terms internal and external corrections relate to known correction modes within the Reed Solomon decoder.

Therefore, the decision made in the previous embodiment regarding the output address of the buffer-output-address signal addr_out must now be made on the maximum limit for this address. The implementation requires a more restrictive time structure as required by the Reed Solomon decoder.

In such a method, the Reed-Solomon decoder has not acquired a disordered ECC block through an intelligent buffer (IBUF) that leads to less essential RAM and complete circuit high performance. The intelligent buffer IBUF according to this embodiment is also used as the first pass correction storage of the Reed Solomon decoder. The methods and apparatus described herein are provided merely as illustrative, and one skilled in the art can implement other embodiments of the present invention within the scope of the present invention. The intelligent buffer (IBUF) according to the present invention is particularly advantageous in that it can be easily used in various types of error correction systems.

As described above, the present invention provides an apparatus and method for preparing data for a Reed-Solomon decoder, i.e., a method and apparatus for an intelligent buffer in front of a Reed-Solomon decoder that requires less RAM and ensures high performance. Available to

Claims (23)

An apparatus for preparing data for a Reed-Solomon decoder, An intelligent buffer (IBUF) in front of the Reed-Solomon decoder, wherein in the intelligent buffer (IBUF), The received data is analyzed based on the incoming sync-signal, which data is buffered in a buffer BUF at an appropriate address as long as the incoming ECC-block (ECC) can be recovered by the Reed-Solomon decoder, If the ECC-block (ECC) cannot be corrected, providing a reset signal (RST_RS) to cancel the first step of processing the ECC-block (ECC), Apparatus for preparing data for the Reed-Solomon decoder. 2. The frame address signal of claim 1, wherein the buffer BUF is connected to an acquisition block ACQ through a data line data_in, as well as a sector identifier SID and a frame address signal for integrity having an ECC block length lgth. an apparatus for preparing data for a Reed-Solomon decoder, connected to an address control block (ADC) to evaluate (fr_addr). The read-out circuit of claim 1, wherein the intelligent buffer IBUF is controlled by an independent clock out_clk having a frequency higher than a maximum frequency of incoming data on a data line data_in supplied to the buffer BUF. Device for preparing data for Solomon decoder. 2. The apparatus of claim 1, wherein the intelligent buffer (IBUF) is a storage medium generally used in front of a Reed Solomon decoder of a DVD-player. 2. The Reed-Solomon decoder of claim 1, wherein the intelligent buffer IBUF can stop the current first pass internal / external correction of the Reed-Solomon decoder and then resynchronize at the ECC block boundary ECC1. Device for preparing data for the. 2. The apparatus of claim 1, wherein the intelligent buffer (IBUF) is used for Reed Solomon correction of the first step of processing a row of ECC-blocks. 10. The apparatus of claim 1, wherein the buffer BUF has dual ports to process independent time structures for output data data_out and incoming data data_in on data lines so that they can be written and read asynchronously. An apparatus for preparing data for a Reed-Solomon decoder, which is configured as a storage array or, alternatively, consists of one IO-port and a control logic to prevent input and output requests from occurring simultaneously. The clock byte_clk of the incoming data data_in is derived from the acquisition-block ACQ and applied to the address control block ADC, and the AND-gate (['] & [']). And is also supplied to the buffer (BUF) by a buffer-input-enable signal (in_en) provided by the address control block (ADC). 3. A counter according to claim 2, wherein the counters for the expected frame address fr_addr and the sector identifier SID follow the synchronization signal from the acquisition block ACQ and are incremented or decremented regardless of the current input in case of a fault. , Apparatus for preparing data for the Reed-Solomon decoder. A method for preparing data for a Reed-Solomon decoder, Analyzing the data based on the incoming sync signal; Buffering the data provided by the address control block (ADC) to an appropriate address in the buffer BUF as long as the Reed-Solomon decoder can recover the incoming ECC-block (ECC), In case the ECC-block (ECC) cannot be corrected, providing a reset signal RST_RS to cancel the first processing step of processing the ECC-block (ECC). And a method for preparing data for a Reed-Solomon decoder. The data analysis step of claim 10, wherein the data analysis step assumes a jump or the most likely change in the expected address when only an incomplete frame address (fr_addr) and a limited sector identifier (SID) are detected and no ECC-block number is detected. And a frame address (fr_addr), a sector identifier (SID) and an ECC-block number to be decoded by an acquisition block (ACQ). 12. The method according to claim 11, wherein if the complete sector identifier (SID) is available, the most significant bit of the sector identifier (SID) is used to synchronize an internal counter in the address control block (ADC). How to prepare your data. 11. The read of claim 10, wherein the jumping of continuous data in the event that the frame or sector is damaged does not affect the integrity of the ECC-block (ECC) if the distance is not longer than the predetermined distance. -Method for preparing data for the Solomon decoder. 15. The method of claim 13, wherein the distance is no longer than half the free buffer length. 15. The method of claim 13, wherein if no next valid frame address is found during the first half frame length, no frame address indicator is provided. The buffer counter of claim 13, wherein the circular counter for the input address in the address control block ADC is based on the expected address for the ECC-block ECC, the sector identifier SID, and the frame address fr_addr. A method for preparing data for a Reed-Solomon decoder, which is increased / decreased over a buffer size range. 14. The output address corresponding to the buffer output address signal addr_out is set to zero in the first resynchronization case, and in this case, the distance between the input address addr_in and the output address addr_out. Is smaller than the default distance, the output address addr_out processing waits until the default distance is reached, and if the distance increases due to the jump of the input address addr_in, the output address until the default distance is reached again. A method for preparing data for a Reed-Solomon decoder, wherein (addr_out) is generated at the maximum output clock (out_clk) rate. 14. The storage of claim 13, wherein in the case of forward jump FWDJ, if jump 3 targets an unblocked area of the buffer having a length, new storage does not impair the integrity of the already stored data. If, in contrast, a jump 4 in a blocked storage area of a buffer having a length is requested, the jump will not be performed, but then the requested input address is in a prohibited range ( 6) A method for preparing data for a Reed-Solomon decoder, which is accelerated until it is outside. 14. The storage of claim 13, in the case of a reverse jump BKWJ, if the jump 3 targets an unblocked area of the buffer having a length, the new store will not compromise the integrity of the stored data. The input can continue, but the output must be stopped until the distance between the input-address and the output-address is nominal and, in contrast, in the blocked storage area of the buffer with length If a jump 4 of is requested, the input address of the buffer-input-address signal addr_in is updated, but no data is stored until the buffer-input-address signal addr_in is directed to the allowed buffer region. Method for preparing data for a Reed-Solomon decoder. The stop flag stop_flag is activated regardless of whether or not the currently read sector is completed. The process is completely restarted and a signal (RST_RS) is generated to reset the Reed Solomon operation. 11. The method of claim 10, further comprising: generating an expected frame address fr_addr and a sector identifier SID, and based on the expected address for an ECC-block ECC, sector identifier SID, and frame address fr_addr. Generating a buffer input address signal addr_in to write data to a buffer BUF; and generating the output address to read output data data_out from the buffer BUF to the Reed-Solomon decoder. And preparing data for the Reed-Solomon decoder. A method for preparing data for a Reed-Solomon decoder, Buffering incoming data at the appropriate address in the buffer BUF as long as an incoming ECC-block (ECC) can be recovered by the Reed Solomon decoder. . The method of claim 22, wherein the single output address of the buffer output address signal addr_out of the buffer BUF is Calculate and perform a first stage internal correction of the Reed-Solomon decoder using the data stored in the buffer BUF, Calculate a syndrome of the first external correction, A method for preparing data for a Reed-Solomon decoder, extended to three addresses dedicated for outputting corrected data in the internal correction mode.