CN1233097C

CN1233097C - Preparation of data for Reed-Solomon decoder

Info

Publication number: CN1233097C
Application number: CNB008171726A
Authority: CN
Inventors: 洛萨·弗雷斯曼
Original assignee: Thomson Licensing SAS
Current assignee: Thomson Licensing SAS
Priority date: 1999-12-15
Filing date: 2000-12-12
Publication date: 2005-12-21
Anticipated expiration: 2020-12-12
Also published as: AU778986B2; KR100754905B1; EP1256175A1; JP2003517238A; AU2364801A; CN1409896A; WO2001045271A1; PL355602A1; KR20020059777A; MXPA02005110A

Abstract

The present invention relates to a method and an arrangement for preparation of data for a Reed - Solomon decoder and more particularly to a method and an arrangement for an intelligent buffer (IBUF) in front of a ramless DVD Reed - Solomon decoder and further on particularly to a method and an arrangement for an intelligent buffer (IBUF) used also as a first pass correction storage of ECC- blocks.In such a way, the Reed - Solomon decoder will not get disordered ECC blocks by an intelligent buffer (IBUF) that leads to less necessary RAM and a high performance of the complete circuitry. The intelligent buffer (IBUF) is used as a first pass correction storage of the Reed Solomon decoder too.

Description

The data of Reed-Solomon decoder are prepared

Technical field

The present invention relates to the method and apparatus that a kind of data that are used for Reed-Solomon (Reed-Solomon) decoder are prepared, more specifically, relate to a kind of method and apparatus that is used for the intelligent buffer before Reed-Solomon decoder, it needs less RAM and has guaranteed high-performance.

Background technology

Traditional preliminary treatment buffer and Reed-Solomon decoder use common RAM to handle impaired data.For example, such device and processing are used to error correction and are stored in such as the data on the optical data media of DVD to be used to reproduce purpose.What people expected is to avoid impaired data are provided to Reed-Solomon decoder or use RAM to store the ECC piece or read defect part several times---these have reduced the speed of data path.DVD is the initial curtail word of a digital multi-purpose CD, and ECC is the initial curtail word of error correcting code, and error correcting code is to check the electronic method of data integrity.

The data of ECC hierarchically are organized as a plurality of data flow.The highest unit is an ECC piece that is divided into a plurality of sections (sector).Each section comprises the row of several regular lengths.In order can error correction to flow, a plurality of parity bytes are affixed to every row; The quantity of extra byte has been determined the quantity of the repairable mistake of every row.Except this horizontal error correction, identical calculating is vertically carried out all bytes at the ECC piece of the same position of delegation; The result is organized in the additional row of this ECC piece.

In order to control the order of section, each first byte comprises identification information.It is the stream of unit that piece before buffer and Reed-Solomon part obtains with the frame, and wherein two constitute delegation; The sign of frame sequential is evaluated, and the result is provided to buffer by suitable synchronizing signal.

Traditional device before Reed-Solomon decoder begins to carry out error correction to impaired data byte, according to the identification control result with storage in common RAM.The misdata of replacing in the memory will need processing expenditure, and this expense can accumulate and reduce significantly the performance of system.

RAM is the initial curtail word of random access storage device.It is an interim storage area, and processor uses it to come executive program and keeps data.Reed-Solomon is the technical term of a forward error correction, and it is used to offset the influence of bit error in the bit stream that receives.Reed-Solomon code is special in widely used because from for the error correction of any grade the extra redundant data that adds by encoder be minimum aspect, they almost are perfectly, therefore do not waste any bit.

The IEEE ISSCC, the U.S., IEEE Inc. (02-1998) XP862225 discloses a Reed-Solomon decoder chip, and it comprises two frame buffer controllers, they and two and chip separate buffer interface, one of them handles input data.

Summary of the invention

One object of the present invention is to provide a kind of to be needed less RAM and has guaranteed the high performance method and apparatus that is used for Reed-Solomon decoder by the data of avoiding replacing in the memory, and the expense that the data in the replacement memory need be handled, this expense can be accumulated and be reduced systematic function significantly.

Solved this problem in the feature described in the independent claims.Dependent claims discloses preferred embodiment.

According to one aspect of the present invention, a kind of method and apparatus that is used at the preceding intelligent buffer of Reed-Solomon decoder (for example being the DVD Reed-Solomon decoder) is provided, wherein as long as the ECC piece of input can be by the Reed-Solomon decoder reparation, then analyze data, and data are cushioned in suitable buffer positions according to the synchronizing signal of input.Under the ECC piece can not be by the situation of error correction, Reed-Solomon decoder obtained the phase I that a reset signal is cancelled processing.Address controll block and buffer have constituted described intelligent buffer.

Under situation according to Reed-Solomon decoder that does not have a RAM of the present invention or so-called no RAM Reed-Solomon decoder, front-end circuit had no idea to store it before complete input ECC piece is sent to described Reed-Solomon decoder as continuous data flow.Under the situation without any precautionary measures, described Reed-Solomon decoder will obtain many described decoders can not ECC piece error correction, unordered.This causes the poor-performing of entire circuit.

Attempt to keep the tissue of data complete as far as possible according to the intelligent buffer before Reed-Solomon decoder of the present invention, and eliminate minor error; To cause under the impaired data conditions in described mistake, Reed-Solomon piece and microprocessor will be apprised of data and be damaged.Because employed no RAM Reed-Solomon piece has extendible (scalable) parameter, so this Reed-Solomon decoder buffer interface also can be used in other environment.Classification of Data also is same for other block codes with lacking synchronously.Buffer is the little space of storage.This buffer is placed between the unit of two swap datas.The function of this buffer is under the unripe reception data conditions in another unit, provides the space to be used for temporary data from a unit.In case this buffer keeps these data a period of time and pay them when the recipient is ready to receive them.

According to another aspect of the present invention, a kind of device is provided, comprising: Reed-Solomon decoder; Buffer (BUF) in the data flow upstream of described Reed-Solomon decoder is analyzed the integrality of the data of reception in described buffer (BUF), can be repaired by Reed-Solomon decoder to determine whether described data; And

Be connected to the address controll block (ADC) of described buffer (BUF), be used to described buffer (BUF) that address and control signal are provided, avoided having the data corruption Reed-Solomon decoding of inappropriate frame length.

Under the situation of for example DVD player, must before can being provided for the Reed-Solomon error correction block, they be cushioned to compensate the minor error of PLL from obtaining partial data.PLL is the abbreviation of phase-locked loop.For this reason, obtain frame headers and the section sign of partial decoding of h, and this information and date is sent to bumper portion together from the HF signal of input.

By this way, generally need a buffer in the Reed-Solomon decoder front, it is advantageously used according to the present invention.

Buffer block should be damaged Reed-Solomon to avoid unsuitable frame length in frame and section boundaries synchronous data flow again.Under the situation of incorrect redirect, buffer block stops the first current logical inside/outside error correction of Reed-Solomon decoder, and synchronous again at next ECC block boundary.The Reed-Solomon buffer interface must be reset under the situation of physics redirect.

In an improved embodiment, intelligent buffer is used to handle the first step Reed-Solomon error correction of the row of ECC piece.Only need to be concerned about some restrictions about the redirect zone that is allowed to.By this way, no RAM Reed-Solomon decoder is advantageously carried out, and it has high-performance and needs less RAM memory capacity.

Description of drawings

Referring now to description of drawings the present invention, wherein:

Fig. 1 is at the intelligent buffer of the DVD of no RAM Reed-Solomon decoder front and the block diagram of some drive circuits,

Fig. 2 is the schematic diagram in the situation ventrocephalad redirect of addr_in＞addr_out,

Fig. 3 is the schematic diagram in the situation ventrocephalad redirect of addr_in＜addr_out,

Fig. 4 is a back schematic diagram to redirect under the situation of addr_in＞addr_out,

Fig. 5 be under the situation of addr_in＜addr_out the back to the schematic diagram of redirect and

Fig. 6 shows the input and output address of the situation lower bumper of redirect in section ID.

Embodiment

In Fig. 1, show necessary three parts of function of the intelligent buffer IBUF of explanation before unshowned no RAM Reed-Solomon decoder.

-first obtains piece ACQ, and it provides a clock byte_clk entering data, in the data data_in and the synchronizing information of data wire.

-second portion is address controll block ADC, and it is from producing address and control signal by obtaining the synchronizing signal that piece ACQ provides; Have in the address of the data flow data_in of data wire input with for address and the control output signal ctrl_out of the data data_out of the output that sends from buffer BUF to Reed-Solomon decoder.

-third part is buffer BUF, and it is configured as the storage array that has two ports to handle the independently time scheme (time scheme) for dateout data_out and the input data data_in on data wire.If it also can be constructed to have an input/output port---the input and output data flow is by suitably decoupling zero.

Address controll block ADC and buffer BUF constitute so-called intelligent buffer IBUF according to the present invention.

Another piece shows a generator clk_gen and produces an independently clock out_clk, the data data_out that is used to export stream.This task has been represented the part of unshowned Reed-Solomon decoder.

As scheme shown in the l, generator clk_gen is connected with buffer BUF with address controll block ADC, is used to provide independently clock out_clk, and it also is used to from buffer BUF to unshowned Reed-Solomon piece reading of data.

Another clock byte_clk of input data data_in obtains from obtaining piece ACQ, and be applied to address controll block ADC and through one with a door “ ﹠amp; " arrival buffer BUF.Described and a door “ ﹠amp; " another input be connected with the output of address controll block ADC, be used to provide buffer input enable signal in_en, this signal is via described and a door “ ﹠amp; ", by the input of a mask byte clock signal byte_clk_msk enable buffer BUF, described mask byte clock signal byte_clk_msk is by a described and door “ ﹠amp; " form and be applied to the input of the correspondence of buffer BUF.Data wire data_in will obtain certainly that the output of the correspondence of ACQ connects with the corresponding input of buffer BUF, and in statu quo be provided at the data of obtaining generation in the piece and entering buffer BUF.Obtaining piece ACQ is connected with address controll block ADC again, coming provides several signals to address controll block ADC, comprise frame start signal nxfr, by the frame address signal fr_addr that obtains piece ACQ decoding, also be acquired sector marker SID, next section initial signal nxt_SID of piece ACQ decoding, sector marker SID that indication is transmitted be acquired the effective sector marker signal SID_valid that ACQ certainly is correctly decoded and be used under the situation that serious optical problem is arranged by the operation of internal microprocessor request asynchronous stop stopping to indicate stop_flag.

Address controll block ADC is connected with buffer BUF, and the control input signals ctrl_in of three bit signalling ECC-, sector-of the input data that comprise by data wire data_in and frame-start is provided to buffer BUF, for the buffer Input Address signal addr_in of input data, for the buffer OPADD signal addr_out of dateout data_out be used for the output operation enable signal out_en to unshowned Reed-Solomon decoder reading of data data_out from buffer BUF.Address controll block ADC also is provided at and stops under the situation of illegal redirect or a signal RST_RS of the Reed-Solomon decoder that resets.

Buffer BUF provides control output signal ctrl_out, and it comprises three bit signalling ECC-, sector-and the frame-start of the dateout data_out that offers Reed-Solomon decoder.

As shown in Figure 1 obtain piece ACQ represent to be called as channel IC channel circuit obtain part, it must extract data and the several Control signal is used for synchronously.

From from for example bit stream of the opticator of unshowned DVD equipment, this piece decoded data data_in, byte clock byte_clk, frame address fr_addr and by the sector number of sector marker SID sign.Under the unordered situation of frame number, as the previous version that obtains part, the wrong sequence of expression is replaced.Sector marker SID definite decoding is really equaled the active zone segment identifier signal SID_valid classification of 1 pulse, and has nothing to do with the frame address decoding.It is 0 again synchronously that this information is used to frame address, even order is damaged.Address controll block ADC as shown in Figure 1 must do main work.Produce the address of buffer BUF with three phases:

Phase I: produce desired frame address fr_addr and sector marker SID.Follow from the synchronizing signal of obtaining piece ACQ, desired frame address fr_addr and the counter of sector marker SID are set up in the controll block ADC of address, and irrespectively are increased with current input under defective situation.In order to follow the track of redirect, also used the desired ECC counter in an inside, it should follow the tracks of the ECC piece of input data in ideal conditions.This internal counter is increased through 0 the time or reduces when sector number.Only provide an incomplete frame address fr_addr and a sector marker SID who determines if obtain piece ACQ, ECC is not provided numbering, then when redirect takes place, suppose the most probable variation of the address that (assume) is desired.If whole district segment identifier SID is used, also ECC-counter synchronously of highest significant position then.

Rule how to handle redirect is:

Under the situation of frame or section interruption, be not longer than the distance of the length of half frame/section from the current location redirect.

Below situation in the ratio of assessment current length and full-length, be possible, wherein n is an integer of suitably selecting.

A.0) frame length can, i.e. length/full-length=1

1) the oversize and n＜length/full-length＜=n+1/2 of frame length

2) the oversize and n+1/2＜length/full-length＜=n+1 of frame length

3) too short and 0＜length/full-length＜=1/2 of frame length

4) too short and 1/2＜length/full-length＜1 of frame length

B.0) frame address can

1) frame address mistake

C.0) sector marker SID can

1) in current ECC piece, SID is too little for sector marker

2) in next ECC piece, SID is too little for sector marker

3) in current ECC piece, sector marker SID is too big

4) in previous ECC piece, sector marker SID is too big

D.0) section can

1) section is too short

2) section is oversize

Can not in time find frame address fr_addr if obtain piece ACQ, then it inserts one.If during first field length, found next valid frame address, transmit frame address designator not then.Here it is why in A with respect to 1/2 nominal length, distinguished different situations.In these combinations some can not take place, so the quantity of combination has reduced a bit.

Second stage: produce buffer Input Address signal addr_in, be used for writing data to buffer BUF.

According to expectation address, sector marker SID and the frame address fr_addr of the ECC piece of phase I, a cycle counter that is used for Input Address is increased by the scope in buffer sizes.Under the situation of redirect, need be according to below the current location of direction, its size and the output stream of the redirect described in detail being taked different strategies.

Handle and to carry out redirect to stop input, up to reaching an address or synchronous again entire process up to new ECC BOB(beginning of block).

Phase III: produce OPADD, be used for reading dateout dara_out to unshowned Reed-Solomon decoder from buffer BUF.

In order to guarantee correct addressing, suppose that independent output clock out_clk is faster than input clock byte_clk.Input signal data_in and dateout data_out from data wire have constituted the corresponding stream of being controlled by enable signal, and OPADD addr_out follows Input Address addr_in on a segment distance.In one embodiment, used half distance of buffer sizes.

In beginning with under synchronous again situation, be set to 0 corresponding to the OPADD addr_out of buffer OPADD signal; In these cases and when distance between Input Address addr_in and OPADD addr_out is less than default distance, the processing of OPADD addr_out is waited for, is arrived up to it.If the Input Address addr_in increase because of redirect has increased the distance to OPADD, then produce addr_out, up to reaching default distance once more with full output clock out_clk speed.

For correct control redirect, this is handled must be immediately or out of service in given address, and executive address produces and is synchronized to 0 again at full speed, and this will be described below.

Buffer BUF as shown in Figure 1 is the RAM that has the specific size of two ports, so it can be read and write asynchronously, or alternatively constitutes and have an IO port and one and prevent the simultaneous control logic circuit of input and output request; This is necessary, and---clock byte_clk and clock out_clk---is completely independent from one another because two clocks.Input and output can be by wasted energy so that the clock processing be easier.Obtaining when being acquired and being transferred to address controll block ADC among the piece ACQ when synchrodata, they must be transferred to Reed-Solomon piece and following address ram generator piece; Therefore they must also be stored and synchronously be sent out with dateout data_out.

Generator clk_gen is the generator that is used for the independently clock out_clk of dateout data_out, it must have the frequency that is higher than the peak frequency (being clock byte_clk) of importing data, and the generation of independent clock out_clk can be passed through employed system clock in the implementation divided by suitable coefficient.

Redirect is handled:

According to the data segments border, the address redirect of listing above is classified.In order to find out the best mode of addressed, must use and above-mentioned different mode classification, because redirect must be considered following aspect:

● the relation of current input and output buffer address,

● the redirect compensation, represent the integrality whether this redirect has destroyed buffer data,

● send to the data volume of Reed-Solomon decoder simultaneously, depend on whether current ECC piece can by error correction by any way and

● how soon that follows can take place synchronously.

Forward direction redirect FWDJ is handled according to Fig. 2 and 3, and the back is handled according to Figure 4 and 5 to redirect BKWJ.

These accompanying drawings show the data axle 1 and the parallel buffer shaft 2 that has the start and end address of explaining in zone 5 that has ECC border ECC0, ECC1, ECC2 mark.Arrow is illustrated in buffer range and the bumper portion under the output 6, and this bumper portion is irrelevant with input 7.And, the snap of the Input Address before redirect is requested (snapshot) 9 and be instructed to the OPADD 8 of Input Address apart from nominal range.

Fig. 2 and 3 illustrates at the buffer Input Address addr_in shown in Fig. 2 and is higher than under the situation of buffer OPADD addr_out and is lower than the situation of the forward direction redirect FWDJ that is asked under the situation of buffer OPADD addr_out at buffer Input Address addr_in shown in Figure 3.First redirect 3 of being asked will be a target with a zone, and this is opposite with second redirect 4 of being longer than first redirect, will can not injure the integrality of the data of being stored.Therefore latter event will not carried out, but output must be accelerated and exceeds forbidden scope 6 up to the address of next one request or complete ECC piece must be dropped.This decision depends on progress and the jump distance of finishing the ECC piece.

Figure 4 and 5 show at buffer Input Address addr_in shown in Figure 4 and are higher than under the situation of buffer OPADD addr_out and are lower than under the situation of buffer OPADD addr_out the back at buffer Input Address addr_in shown in Figure 5 to the configuration of redirect BKWJ request.The scope that is allowed is pointed in the first short redirect 3, and can continue input, but must stop to export up to the distance between the input and output address is nominal range.Under the situation of the second long redirect 4, the next Input Address of being asked of buffer Input Address signal addr_in is pointed to also not from the zone that buffer BUF sends; Suppose that last data are damaged, output is stopped and the zone of dateout is rewritten.A different mode is the input and output that stop buffer BUF, points to the zone of a permission up to the Input Address of buffer Input Address signal addr_in.In dual mode, may impaired data 10 be issued.

Fig. 6 illustrates the performance of embodiment of the several redirects in input and the performance of OPADD.Its proves that most redirects is smoothed.

Fig. 6 shows the address realm AR of the buffer BUF on time shaft t.The Input Address of buffer Input Address signal addr_in makes the OPADD of buffer OPADD signal addr_out follow on a segment distance, and no matter resemble the redirect of JMP, it is obviously smoothed.

Under the situation of physics redirect, the current section that reads is not carried out any use.In this case, activating a stop flag stop_flag, as shown in Figure 1. this is with whether to have finished the current section that reads irrelevant.In this case, address process will be restarted fully, and signal RST_RS is produced with the Reed-Solomon operation that resets.

In second unshowned embodiment, buffer BUF is used as the error correction buffer of the first step of Reed-Solomon decoder simultaneously.Be the stricter scope of redirect with only having any different of the embodiment that illustrates previously, be divided into three addresses, be used for because must consider the single OPADD of the buffer OPADD signal addr_out of first embodiment

● utilize the data of in buffer BUF, storing, calculate and carry out the first step built error correction of Reed-Solomon decoder

● calculate the first outside error correction syndrome (syndrome) and

● with the data of internal schema output correction.

Error correction mode in the inside and outside error correction of term and the known Reed-Solomon decoder is relevant.

Therefore, in front among the embodiment for the decision of the OPADD of buffer OPADD signal addr_out, need now to make according to qualification to the maximum of these addresses.This realizes needing a stricter time scheme, and this depends on the needs of Reed-Solomon decoder.

By this way, Reed-Solomon decoder will can not obtain unordered ECC piece by intelligent buffer IBUF, this caused still less necessary RAM and the high-performance of entire circuit.Also be used as first logical (first pass) error corrected memory of Reed-Solomon decoder according to the intelligent buffer IBUF of this embodiment.

By as just example, those skilled in the art can realize other embodiment of the present invention under the prerequisite of the spirit in keeping the scope of the invention at the method and apparatus of this explanation.

Be particularly useful aspect following according to intelligent buffer IBUF of the present invention: it can easily be used in the various error correction systems.

Claims

1. device comprises:

Reed-Solomon decoder;

Buffer (BUF) in the data flow upstream of described Reed-Solomon decoder is used to analyze the integrality of the data that received, and can be repaired by Reed-Solomon decoder to determine whether described data; And

Be connected to the address controll block (ADC) of described buffer (BUF), be used to described buffer (BUF) that address and control signal are provided.

2. according to the described device of claim 1, wherein said buffer (BUF) is connected to via data wire (data_in) and obtains piece (ACQ) and described address controll block (ADC), is used for respect to error correction code block length (lgth) frame address signal (fr_addr) and sector marker (SID) being assessed.

3. according to the described device of claim 1, wherein said buffer (BUF) is by independent clock (out_clk) control, and this independent clock (out_clk) has than the high frequency of highest frequency in the input data (data_in) of the data wire that offers buffer (BUF).

4. according to the described device of claim 1, wherein said buffer (BUF) is a storage medium, and described Reed-Solomon decoder is a DVD player.

5. according to the described device of claim 1, wherein said buffer (BUF) can stop the first current logical inside/outside error correction of Reed-Solomon decoder, and synchronous again on next error correction code block border (ECC1).

6. according to the described device of claim 1, wherein said buffer (BUF) is used to the error correction of first step Reed-Solomon, and it handles the row of error correction code block.

7. according to the described device of claim 1, wherein said buffer (BUF) is constructed to have the storage array of dual-port, so that the dateout on data wire (data_out) is adopted different clocks with input data (data_in), so that it can be read and write asynchronously, perhaps be constructed to be with an IO port and one to prevent the simultaneous control logic circuit of input and output request.

8. according to the described device of claim 2, the clock (byte_clk) of wherein importing data (data_in) obtains from the described piece (ACQ) that obtains, and be applied to address controll block (ADC) and via with door (‘ ﹠amp; ') being applied in arrival buffer (BUF), the buffer input enable signal (in_en) that is provided by described address controll block (ADC) also has been provided described and door.

9. according to the described device of claim 2, the counter of wherein desired frame address (fr_addr) and sector marker (SID) is followed the synchronizing signal of obtaining piece (ACQ) from described, and is independent of current input ground increase or minimizing under the situation of mistake.

10. method that is used to Reed-Solomon decoder to prepare data comprises step:

In buffer (BUF), whether can be repaired by Reed-Solomon decoder according to the address buffer input data of row and the error correction code block of definite input, and

Can be repaired by Reed-Solomon decoder if determine the error correction code block of input, just data are provided to Reed-Solomon decoder.

11. the method according to claim 10 is characterized in that,

According to the order of from the synchronizing signal of input, decoding by address controll block (ADC), the address buffer data of foundation row in buffer (BUF), as long as the error correction code block of input can then be provided the address by the Reed-Solomon decoder reparation, and when error correction code block can not be repaired, provide a reset signal (RST_RS) with cancellation handle described error correction code block first the processing stage.

12. in accordance with the method for claim 11, wherein be relevant to by the frame address (fr_addr) that obtains piece (ACQ) decoding, sector marker (SID) and error correction code block numbering described data are analyzed, and the sector marker (SID) that ought only detect incomplete frame address (fr_addr) and determine, and when not detecting the error correction code block numbering, then suppose a redirect.

13. in accordance with the method for claim 12, if wherein can obtain whole district's segment identifier (SID), then the highest significant position of sector marker (SID) is used to the internal counter in described address controll block (ADC) synchronously.

14. in accordance with the method for claim 10, if wherein distance is not more than predetermined distance, then under the situation of frame or section interruption, the redirect of continuous data does not influence the integrality of error correction code block.

15. in accordance with the method for claim 14, wherein said distance is no longer than half of the length of free buffer device.

16. in accordance with the method for claim 14, if wherein during first field length, found next valid frame address, then do not provide any frame address designator.

17. in accordance with the method for claim 14, wherein according to expectation address, sector marker (SID) and the frame address (fr_addr) of error correction code block, the cycle counter of the Input Address in address controll block (ADC) is increased/reduces in the scope of the buffer sizes of buffer (BUF).

18. in accordance with the method for claim 14, wherein in beginning with under synchronous again situation, be set to 0 corresponding to the OPADD (addr_out) of buffer OPADD signal; In these cases and when distance between Input Address (addr_in) and OPADD (addr_out) is less than a default distance, OPADD (addr_out) is handled and is waited for, arrived up to it, if and increased because of redirect Input Address (addr_in) should distance, then produce OPADD (addr_out), up to reaching default distance once more with full output clock (out_clk) speed.

19. in accordance with the method for claim 14, wherein under the situation of forward direction redirect (FWDJ), if redirect (3) is target with respect to the length (lgth) of error correction code block with the not one-tenth piece zone in the buffer, then new storage can not injure the integrality of the data of having stored, on the contrary, if is that the redirect (4) of target is required with respect to the length (lgth) of error correction code block with the one-tenth piece storage area in the buffer, then redirect will not carried out, and exceed forbidden scope (6) but export to be accelerated up to the requested Input Address of the next one.

20. in accordance with the method for claim 14, wherein afterwards under the situation of redirect (BKWJ), if redirect (3) is target with respect to the length (lgth) of error correction code block with the not one-tenth piece zone in the buffer, then new storage can not injure the integrality of the data of having stored, and input can continue but must stop to export up to the distance between the input and output address is nominal range, and on the contrary, if is that the redirect (4) of target is requested with respect to the length (lgth) of error correction code block with the one-tenth piece storage area in the buffer, then the Input Address of buffer Input Address signal (addr_in) is updated but data are not stored the buffer area of pointing to a permission up to buffer Input Address signal (addr_in).

21. in accordance with the method for claim 10, wherein under the situation of picking up physics redirect partly of player, do not use the current section that reads, a stop flag (stop_flag) is activated, this is with whether to have finished the current section that reads irrelevant, address process is restarted fully, and signal (RST_RS) is produced the Reed-Solomon operation that resets.

22. in accordance with the method for claim 10, comprise following steps:

Produce a desired frame address (fr_addr) and sector marker (SID),

Desired address, sector marker (SID) and frame address (fr_addr) according to an error correction code block produce buffer Input Address signal (addr_in), be used for writing data at buffer (BUF),

Produce OPADD, be used for reading dateout (data_out) to Reed-Solomon decoder from described buffer (BUF).

23. in accordance with the method for claim 22, it is three addresses that the single OPADD of the buffer OPADD signal (addr_out) of wherein said buffer (BUF) is expanded, and is used for

The first step built error correction of data computation that utilization is stored in buffer (BUF) and execution Reed-Solomon decoder,

Calculate the first outside error correction syndrome and

Output is with the data of described built error correction mode correction.