MXPA02005110A

MXPA02005110A - Preparation of data for a reed solomon decoder.

Info

Publication number: MXPA02005110A
Application number: MXPA02005110A
Authority: MX
Inventors: Lothar Freissmann
Original assignee: Thomson Licensing Sa
Priority date: 1999-12-15
Filing date: 2000-12-12
Publication date: 2003-01-28
Also published as: PL355602A1; AU778986B2; CN1233097C; EP1256175A1; AU2364801A; KR100754905B1; CN1409896A; KR20020059777A; WO2001045271A1; JP2003517238A

Abstract

The present invention relates to a method and an arrangement for preparation of data for a Reed Solomon decoder and more particularly to a method and an arrangement for an intelligent buffer (IBUF) in front of a ramless DVD Reed Solomon decoder and further on particularly to a method and an arrangement for an intelligent buffer (IBUF) used also as a first pass correction storage of ECC blocks.In such a way, the Reed Solomon decoder will not get disordered ECC blocks by an intelligent buffer (IBUF) that leads to less necessary RAM and a high performance of the complete circuitry. The intelligent buffer (IBUF) is used as a first pass correction storage of the Reed Solomon decoder too.

Description

DATA PREPARATION FOR A REED DECODER - SOLOMON FIELD OF THE INVENTION The present invention relates to a method and an arrangement for a data preparation for a Reed-Solomon decoder and more particularly to a method and arrangement for an intelligent buffer in front of a Reed-Solomon decoder that needs less memory than Random access (RAM) and ensures high performance.

BACKGROUND OF THE INVENTION A conventional pre-processing buffer and Reed-Solomon use a common RAM to handle corrupted data. Such an arrangement and processing is for example used to correct data stored on an optical information medium such as a DVD for reproduction purposes. It is desirable to avoid feeding corrupted data to the Reed-Solomon decoder or using a RAM to store the ECC block or to read defective parts several times, which decreases the speed of the data path. DVD fe ^ Ai jJ ** ^ i ^ - * -------- a --- k - ^ ^ «JK¿it. is an acronym for Digital Versatile Disk and ECC is an acronym for Error Correction Code (for its meaning in English) - an electronic method to verify the integrity of the data. ECC data is organized in pieces of the data stream. The highest unit is a block of ECC - which is divided into a number of sectors. Each sector is constituted by a number of rows with a fixed length. To make possible a correction of the current, a number of parity bytes are appended to each row; the number of additional bytes determines the number of correctable faults per row. In addition to this facility of horizontal correction the same calculation is performed vertically on all the bytes of a block of ECC - which are in the same position of a row; the result is organized in additional rows of the ECC block. To control the order of the sectors, the first bytes contain the identification information. The blocks in front of the buffer and the Reed-Solomon part get the stream in frames, two of which constitute a row; an identification of the order of the picture is evaluated and the result made available to the buffer memory by appropriate synchronous signals. A conventional array stores the data in the common RAM with respect to the identification control results before the Reed-Solomon decoder begins performing the correction of corrupted data bytes. The replacement of data with memory failure could require more processing that could accumulate and significantly decrease the performance or performance of the system. RAM is an acronym for Random Access Memory (for its meaning in English). This is a temporary storage area that the processor uses to run programs and to retain data. Reed- Solomon is a technical term for a direct error correction code that is used to displace the effects of byt errors in the reception of the by-pass current. Reed-Solomon codes are special and widely implemented because they are almost perfect in the sense that the extra redundant data added by the encoder is still minimal for any level of error correction, so they are not bypassed.

BRIEF DESCRIPTION OF THE INVENTION An object of the invention is to provide a method and an arrangement for a Reed-Solomon decoder that needs less RAM and ensures high performance by avoiding a data replacement in a memory, which could require higher processing, which could accumulate and significantly decrease the performance of the system. A Reed-Solomon decoder microcircuit that contains two frame buffer controllers that are interconnected with two buffers outside the microcircuit one of which is serving the input data, has already been described by the International Conference on Solid State Circuits (IEEE International Solid-State Circuit Conference, United States IEEE Inc. (02- 1998) XP86225). The features mentioned in the independent claims solve that problem. The dependent claims describe preferred embodiments. In accordance with one aspect of the invention, a method and arrangement for an intelligent buffer memory is provided in front of a Reed-Solomon decoder such as a decoder Reed-Solomon DVD in which the data is analyzed based on the synchronous signals that enter, and the data is stored in the buffer at appropriate buffer sites as long as the ECC block that enters can be repaired by the Reed-Solomon decoder. In the case where the ECC block can not be corrected, the Reed-Solomon decoder obtains a readjust signal to cancel the first stage of processing. An address control block and a buffer form said intelligent buffer. In the case of a RAM-free Reed-Solomon decoder or a so-called Reed-Solomon without RAM according to the invention, the front end circuit has no way to store a complete ECC block that comes in, before sending it as a current of continuous data to the Reed-Solomon decoder. Without any precaution the Reed-Solomon decoder will get many disordered ECC blocks which the decoder can not correct. This leads to poor performance of the entire circuitry. The intelligent buffer in front of the Reed-Solomon decoder according to the invention, tries to maintain the organization of the data as intact as possible, and softens small defects; in the event that the defects lead to corrupted data the Reed-Solomon block and the microcontroller will be informed of the corrupted data. Since the Reed-Solomon block without RAM used has scalable parameters, the interconnection of the Reed-Solomon buffer is also usable in another context. The classification of the data and the lack of synchronization will remain 10 true for other block codes. A buffer is a small space for data storage. The buffer is placed between two units, which exchange data. The buffer function gives space for storage 15 temporary data entering from one unit, in a situation where the other unit is not ready to receive the data. The buffer keeps this data for a period of time and distributes it as soon as the recipient is ready to receive the data. 20 points. In the case of a DVD player for example, the data entering from the acquisition part must be entered into the buffer memory before they can be distributed to the Reed-Solomon correction block to compensate for the light ones 25 PLL defects. PLL is an abbreviation for loop insured in phase. For this reason, the acquisition part decodes the header of the frame and the identification of the sector from the incoming HF signal, and sends this information to the buffer part together with the data. In such a way a buffer is generally necessary in front of the Reed-Solomon decoder, which is advantageously used according to the invention. The buffer block must be able to resynchronize the data stream at the frame and sector boundaries to prevent the inappropriate length of the frame from corrupting Reed-Solomon. In the case of non-correctable jumps the buffer block stops the internal / external correction of the first, current step of the Reed-Solomon decoder and resynchronizes to the next limit of the ECC block. The interconnection of the Reed-Solomon buffer must be readjusted in the case of physical jumps. In an improved mode, an intelligent buffer is used for a first-pass Reed-Solomon correction, which has to do with the rows of an ECC block. Only some restrictions concerning the permitted jumping area have to be respected. In such a way, advantageously, a Reed-Solomon de-encoder without RAM that has a high performance and requires less RAM, is realized.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described with reference to the accompanying drawings, in which: FIGURE 1 is a block diagram for intelligent buffer memory in front of a DVD Reed-Solomon decoder together with some set of drive circuits, FIGURE 2 is a schematic diagram for direct jumps in the case of addr_in > addr_out, FIGURE 3 is a schematic diagram for direct jumps in the case of addr_in < addr_out, FIGURE 4 is a schematic diagram for backward jumps in the case of addr_in > addr_out, FIGURE 5 is a schematic diagram for backward jumps in the case of addr_in > addr_out, and FIGURE 6 shows the entry and exit address of the buffer in the case of jumps in the sector ID.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES In figure 1 are shown the three parts necessary to explain the function of an intelligent buffer IBUF in front of a Reed-Solomon decoder without RAM, not shown. The first part is an ACQ acquisition block that provides a byte_clk data entering clock, the data in the data_in data line and the synchronization information, the second part is an ADC address control block that creates addresses and control signals from the synchronization signals provided from the ACQ acquisition block; there are addresses for the input data stream in the data_in data line and the directions in the out-of-control signal ctrl._out for the output data_out sent from the BUF buffer to the Reed-Solomon decoder, the third part is the BUF buffer built as a storage array with double gates to handle independent time schedules for the output data ljká, & J?, J * »**». T * », M üu J? ... - .. - jtiÜLia. data_out and the data that enters the data line data_in. This can also be constructed with a gate 10 if the input and output data streams are properly decoupled. The ADC address control block and the BUF buffer form the so-called IBUF intelligent buffer according to the invention. An additional block shows a generator clk_gen to generate an independent clock out_clk used for the data stream leaving data_out. This task represents a part of the Reed-Solomon decoder not shown. As shown in Figure 1, the generator clk_gen is connected to the address control block ADC and the buffer BUF to provide the independent clock out_clk, which is also used to read the data from the buffer BUF to the Reed-Solomon block not shown. An additional clock byte_clk of data entering data_in is derived from the acquisition block ACQ and applied to the ADC address control block and via a Y (AND) gate and to the buffer BUF. The other entrance of the gateway Y (AND) - society is connected to an output of the ADC address control block by providing a signal that makes it possible to enter the buffer in_en which makes it possible to enter the buffer BUF via gateway Y (AND) - society by a masked byte clock signal byte_clk_msk formed by gate Y-society and applied to a corresponding entry of buffer BUF. A data line data_in connects a corresponding output of the acquisition block ACQ to a corresponding input of the buffer BUF and provides the data as they are generated in the acquisition block and to be inserted into the buffer BUF. The acquisition block ACQ and the address control block ADC are also connected for the provision of several signals for the ADC address control block since there is a start signal of the nxfr frame, a frame address signal fr_addr which has has been decoded by the acquisition block ACQ, an identifier of sector SID that has also been decoded by the acquisition block ACQ, a start signal of the next sector nxt_SID, a signal identifying the valid sector SID__valid indicating that the identifier of transferred sector SID was decoded correctly by the ACQ acquisition block and a stop_flag stop flag for an asynchronous stop or stop of the operation required by an internal microcontroller in the case of severe optical problems. The address control block ADC is connected to the BUF buffer and provides the buffer BUF with a control in signal ctrl_in comprising the start of ECC, sector and three-bit signaling box of the input data via the data line data_in, a buffer in the addr_in address signal for incoming data, an outward address signal from the buffer addr_out to send out data data_out and an enable signal from the output operation out_en to read data_out data from the BUF buffer to the Reed-Solomon decoder not shown. The ADC address control block further provides an RST_RS signal that stops or resets the Reed-Solomon decoder in the case of illegal jumps. BUF buffer provides an out-of-control signal ctrl_out comprising the start of ECC, sector and signaling box of three bits of the data_out output data provided for the Reed-Solomon decoder. The acquisition block ACQ as shown in FIG. 1 represents the acquisition part of the channel circuit called as channel IC which has to extract the data and several control signals for synchronization. Starting from the bit stream coming from the optical part of a DVD unit, for example, not shown, this block decodes the data data_in, the bit block byte_clk, the frame address fr_addr and the sector number identified by the sector identifier SID In the case of disorder in the frame numbers a sequence of fault representation is replaced as in the present version of the acquisition part. A definitive decoding of the SID of the sector identifier is classified by a valid sector identifier signal SID_valid equal to 1 pulse, independently of the decoding of the frame address. This information is used to resynchronize the frame address to 0 even if the order was corrupted. The ADC steering control block as shown in figure 1 has to do the job l.a., Mfc.í J íMáA. ..:,. Jfr..í, LJ principal. Three stages are used to generate addresses for the BUF buffer.

First Stage: Generation of the expected table address fr_addr and the sector identifier SID. After the synchronization signals from the ACQ acquisition block, the counters for the expected frame address fr_addr and for the identifier of the SID sector are set in the ADC address control block, and in cases of independently increased defects on the input of current. To follow the tracking of the jumps, an expected internal ECC counter is also used, which in the ideal case should follow the ECC blocks of the incoming data. This internal counter is incremented or decremented when the sector number crosses 0. If the ACQ acquisition block provides only an incomplete table address fr_addr and a definitive sector identifier SID and no ECC number, the most likely change in the expected direction is assumed when the jump occurs. If the complete sector identifier SID is used, the most significant bit can also synchronize the ECC counter. The rule of how to handle the jumps is: In the case of disturbances in the table or in the sector, do not skip an instance greater than half the frame / sector length from the current site. The following cases are possible to evaluate the ratio of a current length to a normal length, where n is an appropriately chosen whole number: A. 0) frame length ok, eg, normal length / length = 1 1) length of too long picture and n <; what length / normal length < = n + 1/2 2) frame length too long and n + 1/2 < what length / normal length < = n + 1 3) frame length too short and 0 < what length / normal length < - 1/2 4) frame length too short and 1/2 < what length / normal length < 1 B. 0) address of the table ok 1) address of the wrong frame C. 0) identifier of sector SID ok 1) identifier of sector SID too small, in the present block of ECC 2) identifier of sector SID too small, in the next block of ECC \ J ^^ L¡itito? ~ ItJ ~ AM * ~ * L ~. ~ "• * -« «to» * »*" fc * »? - - < ? ... 3) SID sector identifier too large, in the present ECC block 4) SID sector identifier too large, in the next ECC block D. 0) sector ok 1) sector too short 2) sector too long If the acquisition block ACQ could not find the address of the fr_addr table in time, it inserts one. If the next valid frame address is found during the length of the frame of the first half, frame direction indicators are not sent. This is why different cases have been made in A with respect to the nominal length of 1/2. Some of these combinations can not occur, so the number of combinations is reduced a little.

Second Stage: Generate the buffer memory in address addr_in to write data in the buffer BUF. Based on the expected addresses for an ECC block, the SID sector identifier and the fr_addr box address of the first stage, a circular counter for the input address is increased in the range of the buffer size. In the case of the jumps, different strategies have to be carried out depending on the direction of the jump, its size and the current direction of the output current, as will be described later in detail. The process has to be able to perform a jump, to determine the entry until an address is reached or to resynchronize the total process until it starts a new ECC block.

Third Stage: Generate the output address to read the data output from the BUF buffer in the Reed-Solomon decoder not shown. To ensure an appropriate address it is assumed that the independent output clock out_clk is faster than the input clock byte_clk. The input signals from the data line data_in and the data output data_out form corresponding currents controlled by enabling the enable signals and the output address addr_out follows the input address addr_in at some distance. In one mode, a distance of half the size of the buffer has been used.

At the beginning and in the case of resynchronization the output address corresponding to the buffer outside the address signal addr_out is set to 0; in these cases and when the distance between the addr_in entry address and the addr_out exit address is less than the default distance, the addr_out exit address process waits until it is reached. If due to the jumps the addr_in input direction advances increasing the distance to the output address, the addr_out is generated with full output clock speed out_clk until the default distance is reached again. In order to handle jumps properly this process must be able to stop the operation immediately or in a given direction, to perform address generation by full speed and to resynchronize to 0 as will be described later in the present. The buffer BUF as shown in Figure 1 is a RAM of the specified size with double gates, so that it can be asynchronously written and read or is alternatively constructed with an input 10 and a control logic that prevents incoming requests and matching output; this is necessary because the two clocks - the clock byte_clk and the clock out_clk, are completely independent of each other. Both, the entrance and the exit, can be disabled to make easier the handling of the clock. When synchronous data is acquired in the ACQ acquisition block and transferred to the ADC address control block, these must be transferred to the Reed-Solomon block and to the next RAM address generator block; therefore, these must also be stored and sent synchronously with the data output data_out. The generator clk_gen is the generator of the independent clock out_clk for data output data_out, which must have a higher frequency than the maximum frequency of the input data, for example, the clock byte_clk. The generation of the independent clock out_clk can be performed by dividing the clock of the system used in the embodiment by an appropriate factor.

Handling of Jumps: The address jumps listed above were stored in categories with respect to the limits of the data section. To find it il.J..Í. «E_l-Stl .: better strategy for the address of a buffer memory, it has to be used a different classification than the one shown above, because the jumps have to be considered under the aspect of: • the address of the current input and output buffer, • of the jump shift which means if the jump violates the integrity of the buffer data, • of the amount of data sent in the time lapse to the Reed-Solomon decoder depending on the question of whether the current ECC block can be corrected in some way, and • how fast a next synchronization occurs. The direct jumps FWDJ are handled according to figures 2 and 3 and the reverse jumps BK J according to figures 4 and 5. These figures show a data axis 1 with ECC markers - ECCO, ECC1, ECC2 and parallel limits an axis 2 with buffer with the start and end address annotated in area 5. The arrows show the interval of the buffer under output 6 and the part of the buffer memory, which is . i.Mr8 v? iM **.,? t *. * f ** »aAkr * At ?. jal * - ** / t t .l free for the input 7. In addition, 9 a snapshot was required for the entry address before a jump, and the exit direction is indicated at the nominal distance towards the entry direction 8. Figures 2 and 3 illustrate the situation of a front or direct jump required by F DJ under the circumstance that a buffer in address addr_in is higher than the buffer outside the addr_out address as shown in figure 2 and under the circumstance that a buffer in address addr_in is lower than the buffer outside address addr_out as shown in Figure 3. The first required hop 3 will be directed to an area, which will not damage the aforementioned integrity of the stored data, in contrast to a second hop 4 which It is longer than the first. The last case will therefore not be made but the output must be accelerated until the next required address is outside the prohibited range 6 or the entire ECC block must be discarded. The decision depends on the progress in completing the ECC block and on the jump distance. Figures 4 and 5 show the configuration of the backward jump requests BK J under the circumstance that a buffer in toa. »# * - * .fe *« ÉM¡i ^ .riifeaa & ate address addr_in is higher than the buffer outside address addr_out as shown in figure 4, and under the circumstance that a buffer in address addr_m is lower than the buffer outside address addr_out as shown in the figure 5. The first short jump 3 points to the allowed interval, and the entry can continue but must have the exit until the distance between the entry direction and the exit direction is the nominal distance. In the case of a second, longer jump 4, the next required input address of the buffer memory in address addr_in points to an area that is not yet sent out of the buffer BUF; assuming that the last data was corrupted the output is stopped and the area of the output data is overwritten. A different strategy is to stop the input and the output of the BUF buffer until the address of the buffer in the address signal addr_in points to a permitted area. In both strategies the possible corrupted data 10 are already sent out. Figure 6 illustrates the behavior of the multi-hop modality at the entrance, and the .isÉAil behavior of the exit directions. This shows that most of the jumps are smoothed. Figure 6 shows an address range AR of the buffer BUF over a time axis t. The input address of the buffer in the address signal addr_in causes an output address of the buffer outside the address signal addr_out after some distance, in spite of the jumps like JMP that are obviously softened. In the case of physical jumps, no use will be made of the sectors currently read. In this case, a tension flag stop_flag is activated as shown in figure 1. This is independent of whether the sectors currently read have been completed or not. The address process will be completely restarted in that case, and an RST_RS signal is generated to readjust the Reed-Solomon operation. In a second mode not shown, the BUF buffer is used simultaneously as a correction buffer for the first step of the Reed-Solomon decoder. The only difference to the previously described modality is a more restricted interval for the jumps because it has to be taken into account that the jump direction The simple buffer signal outside address addr_out of the first mode is divided into three addresses dedicated to: • calculating and performing the internal correction of the first step of a Reed-Solomon decoder using the data stored in the buffer BUF • the calculation of the syndromes of the first external correction and 10 • the output of the corrected data in the internal mode. The terms of internal and external correction are related to the known correction modes within a Reed-Solomon decoder. The decisions made in the previous mode on the output address of the buffer memory outside address addr_out have therefore to be made now on the most limiting of these addresses. The implementation 20 requires a more restrictive time scheme depending on the needs of the Reed-Solomon decoder. In such a way, the Reed-Solomon decoder will not get disordered ECC blocks by a 25 IBUF intelligent memory that leads to less ? i Required RAM and high performance of the complete circuitry. The IBUF intelligent buffer according to this mode is used as a first step correction storage also of the Reed-Solomon decoder. The method and arrangement described herein are given as examples only, and a person skilled in the art can perform other embodiments of the invention while remaining within the scope of the invention. The IBUF intelligent buffer according to the invention is particularly advantageous since it can easily be used for various types of error correction systems.

Claims

1. An apparatus for a data preparation for a Reed-Solomon decoder comprising: an intelligent memory in front of a Reed-Solomon decoder in which the received data is analyzed with respect to the integrity if the data may or may not be repaired by the Reed-Solomon decoder.

2. Apparatus according to claim 1, wherein the buffer memory is connected via a data line to an acquisition block, as well as to a control block of 15 direction to evaluate the frame direction signals and the sector identifier concerning an integrity with an ECC block length.

3. Apparatus in accordance with Claim 1, wherein the intelligent buffer is controlled by an independent clock having a higher frequency, than a maximum input data rate in the data line supplied to the buffer. 25 4 m Imi liw f J * fc j

4. Apparatus according to claim 1, wherein the smart buffer is a storage medium normally used in front of a Reed-Solomon decoder of a DVD player.

5. Apparatus according to claim 1, wherein the intelligent buffer can stop a current, first, internal, external correction of the Reed-Solomon decoder and resynchronizes at the next limit of the ECC block.

6. Apparatus according to claim 1, wherein the intelligent buffer is used for a first-pass Reed-Solomon correction having to do with the rows of an ECC block.

7. Apparatus according to claim 1, wherein the buffer is constructed as a storage array with double gates to handle independent time frames for the output data and the input data on the data line, so that it can be written and read asynchronously or alternatively constructed with an input / output gate and a control logic that prevents matching input and output requests.

8. Apparatus according to claim 2, wherein an input data clock is derived from the acquisition block and applied to the address control block and via a 10 gate Y (&) and also supplied by an input enable signal of the buffer provided by the address control block to the buffer.

9. Apparatus according to claim 2, wherein the counters for an expected frame address and for the sector identifier follow the synchronization signals from the acquisition block, and in case of defects 20 were increased or decreased regardless of the current entry.

10. A method for data preparation for a Reed-Solomon decoder, comprising 25 the steps of: a storage in memory intermediate of the data entering addresses that depend on the row in a buffer as long as an ECC block that enters can be repaired by the Reed-Solomon decoder.

11. A method according to claim 10, characterized in that: the data is stored in the buffer in addresses that depend on the row based on the decoded order from the synchronous signals that enter through a control block in a direction buffer providing the addresses as long as the Reed-Solomon decoder is able to repair an ECC block that comes in and in a case where an ECC block can not be corrected, it provides a reset signal to cancel the first process step of the processing of the ECC block.

12. A method according to claim 11, wherein the data is analyzed with respect to the address of the frame, the sector identifier and the ECC block number decoded by an acquisition block, and where a jump or the most likely change in the expected directions is assumed when only an incomplete frame address and a defined sector identifier and no ECC block number have been detected.

13. A method according to claim 12, wherein if the complete sector identifier is available, the most significant bits of a sector identifier are used to synchronize an internal counter within 10 of the steering control block.

14. A method according to claim 10, wherein the successive data jumps in the case of disturbances of frame or of 15 sector does not influence the integrity of the ECC blocks, if a distance is no greater than a predetermined distance.

15. A method according to claim 14, wherein the distance is no greater than half the length of the free buffer.

16. A method according to claim 14, wherein not provided Igi? m ^^ jjí Box direction indicators if a next valid box direction is found during the frame length of the first half.

17. A method according to claim 14, wherein a circular counter for the address address in an address control block is incremented / decremented in the range of the buffer size, from a buffer based on the addresses expected for an ECC block, a sector identifier and a box address.

18. A method according to claim 14, wherein at the beginning and in the case of resynchronization, the input address corresponding to an address signal outside buffer is set to zero, and in these cases and when the distance between the input address and the output address is less than a default distance, the output address process waits until it is reached, and if due to the jumps of the input address the distance is increased, output addresses are generated with full speed of exit clock until the default distance is reached again.

19. A method according to claim 14, wherein in the case of a direct jump or forward if a hop is directed to an unblocked area of the buffer of determined length the new storage does not damage the integrity of the data already stored and if in contrast, a jump within the blocked storage area of the buffer of the given length is required, the hop will not be made but the output is accelerated until the next required input address is outside a forbidden range.

20. A method according to claim 14, wherein in the case of a backward jump if a hop is directed towards an unblocked area of the buffer of determined length, the new storage will not damage the integrity of the stored data and the input can continue but must have the output until the distance between the input and output address is the nominal distance, and if in contrast a jump inside ^^ M. . ^ ,, ^ Li, .. ¿¿¿Jü ^ gm ^ g of a blocked storage area of the buffer of determined length is required, the address address of the buffer memory in address is updated but the data is not stored until the next buffer memory in address points to an area buffer memory allowed.

21. A method according to claim 10, wherein in the case of physical jumps of a pickup of a player does not make use of the currently read sectors, a stop flag is activated regardless of whether the sectors currently read have been or not When completed, the address process is completely restarted and a signal is generated to readjust the Reed-Solomon operation.

22. A method according to claim 10, comprising the steps of: generating an expected frame address and the sector identifier, generating a buffer in the address signal for writing data in a buffer, based on the expected addresses for an ECC block, the identifier of sector and frame direction, output address generation to read output data from the buffer to the Reed-Solomon decoder.

23. A method according to claim 22, wherein a simple output address of a buffer outside the address signal of the buffer memory is extended to three addresses dedicated to a calculation, and an embodiment of a first internal correction. step of a Reed-Solomon decoder, using data stored in the buffer memory, and the calculation of the syndromes of a first external correction and a corrected data output in the internal correction mode.