KR20020055036A - CMOS image sensor for improving capacitance of buried photodiode and method for fabricating the same - Google Patents

Abstract

PURPOSE: A complementary metal oxide semiconductor(CMOS) image sensor for improving the capacitance of a buried photodiode is provided to remarkably improve a characteristic by preventing a punch between adjacent pixels, and to increase the number of dies regarding a wafer by reducing the size of the device. CONSTITUTION: A semiconductor substrate(201) is of the first conductivity type. A field insulation layer(202) is locally formed in the semiconductor substrate. A field stop impurity layer(203) of the first conductivity type is formed under the field insulation layer. An impurity layer of the first conductivity type is formed under the field insulation layer and the surface of the semiconductor substrate adjacent to the field insulation layer. An impurity layer of the second conductivity type is formed under the impurity layer of the first conductivity type. The buried photodiode is fabricated by the impurity layers of the first and second conductivity type. A silicon oxide layer(207a) is formed on the interface between the impurity layer of the second conductivity type and the field stop impurity layer.

Description

CMOS image sensor for improving capacitance of buried photodiode and method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a CMOS image sensor for improving the capacitance of a buried photodiode and a method of manufacturing the same.

A buried photodiode is used as part of a component pixel of a CMOS image sensor used as an image recognition device. The buried photodiode converts light incident on a unit pixel into electrons, which is a major part of the sensor's characteristics.

The buried photodiode is composed of an impurity bonding layer formed on a silicon substrate through an impurity ion implantation process. A depletion layer is formed by applying a bias to the impurity bonding layer configured as described above, and an image signal is realized by collecting electrons generated in the silicon substrate in the depletion layer by the incident light for a predetermined time and reading them in a circuit.

Therefore, the capacitance of the buried photodiode must be increased to collect a large amount of electrons, thereby obtaining a good image signal.

1A to 1C show a process in which electrons collect in a depletion layer of a photodiode under an image sensor structure according to the related art.

First, referring to FIG. 1A, the buried photodiode is formed by high energy low concentration impurity ion implantation and low energy high concentration impurity ion implantation in the active region of the low concentration P-type epilayer substrate 101 surrounded by the field oxide film 102. It is comprised by the N-type impurity layer 104 and the P-type impurity layer 105. FIG. In other words, the P-type impurity layer 105, the N-type impurity layer 104, and the P-type epilayer substrate 101 form a PNP photodiode.

When the reverse bias is applied to the buried photodiode, depletion starts from the junction, and finally, the N-type impurity layer 104 is completely depleted, and the portion where the electric filed is peaked is the depletion of the two PN junctions. This is the meeting area ("a" in the drawing).

On the other hand, the field stop ion implantation region (P-type impurity region) 103 is formed under the field oxide film 102 because impurities (for example, boron) of P wells (not shown) are diffused into the field oxide film 102 during field oxidation. ) Should be formed.

Subsequently, referring to FIG. 2B, when light is incident, electrons are collected in a depletion layer, and electrons are accumulated from a portion where an electric field of the N-type impurity layer 104 is collected by an electric field.

Subsequently, in FIG. 1C, when the electrons are accumulated to some extent, electrons in the depletion layer adjacent to the field stop ion implantation region 103 are diffused and consumed in the field stop ion implantation region 103, which is a P-type impurity region. The depleted layer region in which electrons are consumed is indicated by the symbol "b". Practically this consumed electron is about 40% of the generated electrons.

Therefore, the capacitance of the buried photodiode is lowered, thereby degrading the photosensitive efficiency of the buried photodiode.

On the other hand, as the CMOS image sensor shrinks with a 0.35 탆 design rule, it is necessary to secure a separate region from the buried photodiode of adjacent pixels due to depletion.

However, since the ion implantation energy for forming the N-type impurity layer 105 is 180 KeV, the amount of lateral diffusion is large, so that the punch by the buried photodiode between pixels is high. This punch problem is aggravated by the application of deep sub micron technology, and becomes an obstacle to the size reduction of pixels.

An object of the present invention is to provide a CMOS image sensor and a method of manufacturing the same to solve the problem of capacitance between buried photodiode and the punch between adjacent pixels.

1A to 1C are conceptual views illustrating a process of collecting electrons in a depletion layer of a photodiode under an image sensor structure according to the related art;

2A to 2E are cross-sectional views of a manufacturing process of a CMOS image sensor according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

201: P-type epilayer substrate 202: field oxide film

203: field stop impurity layer 204: gate electrode

205: oxygen ion implantation mask 206: oxygen ion implantation

207: oxygen ion implantation region 208, 212 ion implantation mask

209 N-type impurity ion implantation 210 N-type impurity layer

211: gate sidewall spacer 213: P-type impurity ion implantation

214: P-type impurity layer 215: source / drain ion implantation mask

216: N + source / drain ion implantation 217: sensing area

218: oxide film 219: BPSG film

207a: silicon oxide film

According to another aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor, the method including: forming a field stop impurity layer and a field insulating film on a semiconductor substrate of a first conductivity type; Performing oxygen ion implantation using a first mask at which a boundary of an active region in which the field insulating layer and the buried photodiode are to be opened is opened; Forming a buried photodiode in the active region by continuously performing a high energy second conductivity type impurity ion implantation and a low energy first conductivity type impurity ion implantation by a mask and an ion implantation process; And forming a silicon oxide film in a region where the oxygen ion implantation is performed by performing a thermal process.

In the present invention, the projection ratio (Rp) of the impurity ion implantation of the second conductivity type and the oxygen ion implantation is the same.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2A to 2E are cross-sectional views of a manufacturing process of a CMOS image sensor according to a preferred embodiment of the present invention. Here, only the buried photodiode, the transfer transistor, and the floating diffusion region (sensing region) of the unit pixel structure of the CMOS image sensor are shown.

First, as shown in FIG. 2A, the field oxide film 202 and the field stop impurity layer 203 are formed on the P-type epitaxial substrate 201, and the gate electrode 204 of the transfer transistor is formed. An oxygen ion implantation mask 205 is formed in which the active region where the photodiode is to be formed and the boundary portion of the field oxide film 202 is opened, and then oxygen ion implantation 206 is performed.

At this time, the oxygen ion implantation energy is selected to have the same projection ratio (Rp) as the N-type impurity ion implantation of the subsequent process. Also it is carried out after the process of the above design rule 0.35㎛ uses a high-energy ion implantation equipment, forming the oxygen ion implantation mask 205 on the field oxide film 202, and oxygen (O ₂₎ ion implantation. In this case, the area of the buried photodiode is not reduced at all. The oxygen ion implantation mask is not opened at the photodiode boundary connected to the transfer transistor.

Subsequently, in FIG. 2B, after the oxygen ion implantation mask 205 is removed, the ion implantation mask 208 for forming the N-type impurity layer is formed again, and the N-type impurity ion implantation 209 is performed. Here, under the field oxide film, there is a profile of the oxygen ion implantation region 207 together with the profile of the field stop impurity layer 203. In general, since there is no thermal process from the gate electrode formation to the source / drain annealing process, the doping profile of the oxygen ion implantation remains as it is.

Subsequently, in FIG. 2C, after removing the ion implantation mask 208 for N-type impurity ion implantation, a spacer 211 is formed on the sidewall of the gate electrode 203, and the ion implantation mask 212 for P-type impurity ion implantation is formed. After the formation, the P-type impurity ion implantation 213 was performed at low energy. Doping profiles of the field stop impurity layer 203, the oxygen ion implantation region 207, and the N-type impurity layer 210 exist in the active region below the field oxide film 202 and in the buried photodiode region.

2D is a state in which the ion implantation mask 212 is removed, and then the source / drain ion implantation mask 215 is formed again, and the N + source / drain ion implantation 216 is performed. In the active region of the dephotodiode region, doping profiles of the field stop impurity layer 203, the oxygen ion implantation region 207, the N-type impurity layer 210, and the P-type impurity layer 214 exist. The sensing region 217 is formed on the other side of the gate electrode by the N + source / drain ion implantation 216.

Subsequently, as shown in FIG. 2E, the ion implantation mask 215 is removed, and then an oxide film 218 and a BPSG film 219 are formed as a pre-insulation film.

As shown in FIG. 2E, an oxygen ion implantation region 207 reacts with silicon through a thermal process to form a silicon oxide film (SiO ₂ ) 207a in the boundary region between the field region and the buried photodiode region.

Therefore, since the silicon oxide film 207a is present in the portion adjacent to the N-type impurity layer 210 and the field stop impurity layer 203, the mutual depletion between the two regions can be effectively prevented to prevent or prevent the consumption of electrons (photocharges). do. In addition, this enhances the isolation between adjacent photodiodes, which is a great advantage in reducing the pixel size.

In addition, since the oxygen ion implantation can be effectively performed to the high energy ion implantation equipment at the required depth, the P-type epilayer substrate 210 and the P-type impurity layer 214 are still connected by the field stop impurity layer 203 to further technology. Without the advantages of the buried photodiode of the prior art.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention increases the capacitance of the buried photodiode, and also solves the problem of punching between adjacent pixels, thereby greatly improving the characteristics of the CMOS image sensor.

In addition, the device can be scaled down, leading to higher integration of the chip and increasing the number of dies produced per wafer.

Claims (3)

CMOS image sensor, A first conductive semiconductor substrate; A field insulating film formed locally on the semiconductor substrate; A field stop impurity layer of a first conductivity type formed under the field insulating film; A buried photodiode formed by a pure layer of a first conductive type formed under the surface of the semiconductor substrate adjacent to the field insulating film and an impurity layer of a second conductive type formed below; And A silicon oxide film formed at a boundary between the second conductive impurity layer and the field stop impurity layer CMOS image sensor comprising a. In the CMOS image sensor manufacturing method, Forming a field stop impurity layer and a field insulating film on the first conductive semiconductor substrate; Performing oxygen ion implantation using a first mask at which a boundary of an active region in which the field insulating layer and the buried photodiode are to be opened is opened; Forming a buried photodiode in the active region by continuously performing impurity ion implantation of a high energy second conductivity type and impurity ion implantation of a low energy first conductivity type by a mask and an ion implantation process; And Performing a thermal process to form a silicon oxide film in the region where the oxygen ion implantation is performed CMOS image sensor manufacturing method comprising a. The method of claim 2, And a projection ratio (Rp) of the impurity ion implantation of the second conductivity type and the oxygen ion implantation is the same.