KR20020054716A - Buffer Circuit for Input of RAS - Google Patents

Abstract

PURPOSE: An RAS(Row Address Strobe) signal input buffer circuit is provided to output a stable internal RAS signal regardless of power noise by improving a structure of an input buffer. CONSTITUTION: The first input inverter(I4) has an input terminal for receiving a power-up signal and an RAS bar signal from the outside. The first input inverter(I4) is used for inverting the received power-up signal. The first PMOS transistor(Q5) is controlled by an output of the first inverter(I4). The second PMOS transistor(Q6) and the first NMOS transistor(Q7) are controlled by the RAS bar signal. The second PMOS transistor(Q6) and the first NMOS transistor(Q7) are connected directly with the first PMOS transistor(Q5). The second NMOS transistor(Q8) is controlled by an output of the first input inverter(I4). The second inverter(I5) inverts outputs of the second PMOS transistor(Q6) and the first NMOS transistor(Q7). The third inverter(I12) inverts an internal RAS signal. The fourth, the fifth, and the sixth inverters(I11,I10,I9) delay and invert an output of the third inverter(I12). A NOR gate performs a logical operation for an output of the third inverter(I12), an output of the sixth inverter(I9), and the first inverter(I4). A switching portion is formed with a transmission gate and the seventh inverter(I6). A latch portion is formed with the eighth inverter(I7) and the ninth inverter(I8).

Description

RAS signal input buffer circuit {Buffer Circuit for Input of RAS}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly, to a row address strobe (RAS) signal input buffer circuit for outputting a stable internal ras (intRAS) signal regardless of power noise.

In general, a row address strobe (RAS) signal input buffer circuit of a semiconductor memory device receives a raster (RAS) signal of a transistor-transistor logic (TTL) level and receives an internal ras (intRAS) of a complementary metal oxide semiconductor (CMOS) level. This circuit outputs a signal.

Hereinafter, a Lars signal input buffer circuit will be described with reference to the accompanying drawings.

1 shows a conventional lath signal input buffer circuit.

2 illustrates the timing diagram of FIG. 1.

As shown in FIG. 1, a conventional ras signal input buffer circuit includes a powerup signal and a rasp ) A first inverter (I1) that enters the input terminal and inverts the powerup signal, a first PMOS transistor (Q1) controlled by the output of the first inverter (I1), Said Rasva ( Is controlled by a second PMOS transistor Q2 and a first NMOS transistor Q3 connected in series with the first PMOS transistor Q1 and by the output of the first inverter I1. Second and third outputting the second PMOS transistor Q4 and the output phases of the second PMOS transistor Q4 and the first NMOS transistor Q3 by inverting twice to output the original phase. It consists of inverters I2 and I3.

Said Rasva ( The second PMOS transistor Q2 and the first NMOS transistor Q3, which are controlled by the ()) signal, serve as an inverter for outputting a phase inversion signal of the rasva signal.

The second inverter I2 and the third inverter I3 are connected to the ras bar ( ) Delays the phase reversal of the signal for a certain period of time.

As shown in FIG. 2, the las signal input buffer circuit is initialized as the powerup signal changes from logic low to logic high. At this time, Rasbah ( When the signal is changed from logic high to logic low, the node N indicates logic high, and the internal ras signal intRAS has a predetermined delay component and outputs a logic high to drive the internal circuit.

Said Rasva ( When the signal is in a logic low state, due to in-chip power noise such as bit line sensing noise and data output noise, ) Signal is determined to be logic high, the internal ras (intRAS) signal transitions to a logic low state. The logic low state of this internal lath circuit disables the internal circuitry.

However, the conventional lath signal input buffer circuit as described above has the following problems.

The RAS signal is a TTL level signal, and because of various power noises formed inside the semiconductor memory device, ) Signal may transition. Therefore, since the conventional ras signal input buffer circuit responds only to the rasva signal, the ras signal is output to the logic low state when the rasva signal transitions to logic high, where the internal circuit is disabled. The disable state of the internal circuits causes the entire circuits to fail, and causes a fatal defect in the entire semiconductor memory device. Therefore, there is a need for a lath signal input buffer circuit capable of outputting a stable internal lath signal regardless of power noise.

The present invention has been made to solve the above problems, and an object thereof is to provide a lath signal input buffer circuit capable of outputting a stable internal lath signal regardless of power noise generation.

1 is a conventional Lars signal input buffer circuit

2 is a signal timing diagram illustrating the operation of FIG. 1.

3 is a Lars signal input buffer circuit of the present invention

4 is a signal timing diagram illustrating the operation of FIG. 3.

The las signal input buffer circuit of the present invention includes an input buffer unit for outputting a level-converted signal by inputting a power signal and a las signal from an external source, and outputting a pulse delayed for a predetermined time in response to the power signal and the internal las signal. A delay unit connected to an output terminal of the input buffer unit, a switching unit to block a signal path between the level-converted signal and the internal lath signal in response to the delay unit pulse, and an output terminal of the input buffer unit. And a latch unit for maintaining the level of the internal signal in response to the delay unit pulse.

Hereinafter, a lass signal input buffer circuit of the present invention will be described with reference to the accompanying drawings.

Figure 3 shows a lath signal input buffer circuit of the present invention.

4 illustrates a timing diagram of FIG. 3.

As shown in Fig. 3, the present invention is largely composed of an input buffer section, a delay section, a switching section, and a latch section.

The input buffer unit includes a powerup signal and a ras bar ) A first inverter I4 which enters an input terminal and inverts the powerup signal, a first PMOS transistor Q5 controlled by an output of the first inverter I4, Said Rasva ( A second PMOS transistor Q6 and a first NMOS transistor Q7 connected in series with the first PMOS transistor Q5 and the output of the first inverter I1. The second NMOS transistor Q8 and the second inverter I5 for inverting the outputs of the second PMOS transistor Q6 and the first NMOS transistor Q7 are configured.

The input buffer unit applies a power-up signal to initialize the circuit and generates a ) And outputs an internal ras (intRAS) signal having a reversed phase. The structure is the same as that of a conventional lath signal input buffer circuit.

The delay unit receives an internal ras (intRAS) signal as an input, and a third inverter I12 for inverting it and a fourth connected odd number in series for delaying and outputting the output of the third inverter I12 by a predetermined time. Logic operation by receiving the fifth and sixth inverters I11, I10, and I9, the output of the third inverter I9, the output of the sixth inverter I9, and the output of the first inverter I4. Is composed of a NOR gate NG.

The delay unit functions to maintain and output the original signal for a predetermined time due to an input terminal (delay units I11, I10, I9) having a predetermined time delay connected to the odd gate NG. In addition, the inverter may arbitrarily add an odd number to set a predetermined time for the signal to be maintained.

The switching unit is composed of a transmission gate TG and a seventh inverter I6, and the seventh inverter I6 is connected to a node A from which the output of the NOR gate NG of the delay unit is output. The output of the gate NG is received and inverted to be transmitted to the transmission gate TG. In addition, the transmission gate TG is connected to the output node A of the NOR gate NG again to form a loop structure.

The switching unit blocks the signal path only during a predetermined time when the delay unit is activated.

The latch unit may include an eighth inverter I7 that inverts the output of the transfer gate of the switching unit to output an internal lath signal, and a ninth inverter that inverts the output of the eighth inverter I7 and applies it to the transfer gate again. I8).

The latch part functions to stably maintain the level of an internal ras (intRAS) signal.

As shown in FIG. 4, the Lars signal input buffer circuit is initialized as the powerup signal transitions from logic low to logic high. At this time, Rasbah ( As the signal changes from logic high to logic low, it activates the internal ras (intRAS) signal to logic high and enables the chip.

Said Rasva ( ) When the signal is in the logic low state, the second PMOS transistor Q6 and the first NMOS transistor Q7 serving as the inverter output a logic high to the node N. At this time, the second inverter I5, The internal inras signal is double inverted by the eighth inverter I7 to output a logic high.

An internal lath signal, which is an output signal of the lath signal input buffer circuit, is connected to the third inverter I12 and inverted and input to the NOR gate NG. By turning off the transmission gate TG while passing through the NOR gate NG, ) And the connection between the internal ras (intRAS) signal. At this time, the eighth inverter I7 and the ninth inverter I8 of the latch portion hold the internal signals.

Thereafter, an internal ras (intRAS) signal is inputted to the NOR gate NG after being delayed for a predetermined time through the delay element through the third inverter I12, and the NOR gate NG output (confirmed at node A) is After the predetermined time passes, the transfer gate TG is turned on. Therefore, the signal path is formed again with the output of the level shifting buffer.

That is, when a voltage noise occurs, the las signal input buffer circuit of the present invention functions to delay the delay element of the delay unit for a time when voltage noise may occur, and the switching unit may perform the time during which the voltage noise may occur. It is turned off. Accordingly, the path between the ras (RAS) signal and the internal ras (intRAS) signal is cut off, so that a stable signal can be output to the internal ras (intRAS) signal regardless of a rasva transition that may occur due to voltage noise.

According to the present invention, the delay unit, the transfer unit, and the latch unit may be added to a conventional Lars signal input buffer circuit to maintain a logic high state in which the internal Ras signal intRAS is active regardless of voltage noise.

The las signal input buffer circuit of the present invention as described above has the following effects.

Switching, delay, and latch sections are added to the conventional las signal input buffer circuit to turn off the transmission gate when there is power noise in the circuit, and output a stable internal lath signal through the latch section. Turn on to output an internal Lars signal corresponding to the Rasva signal.

Therefore, a stable signal is outputted regardless of power noise, so that in-chip failing can be prevented and the yield of the semiconductor memory can be improved.

Claims (4)

An input buffer unit for outputting a level-converted signal by inputting a power-up signal and a rasva signal from the outside; A delay unit for outputting a pulse delayed for a predetermined time in response to an inversion signal of the power-up signal and an internal lath signal; A switching unit connected to an output terminal of the input buffer unit and blocking a signal path between the level-converted signal and the internal lath signal in response to the delay unit pulse; And a latch unit connected to an output terminal of the input buffer unit and configured to maintain a level of the internal signal in response to the delay unit pulse. The las signal input buffer circuit of claim 1, wherein the switching unit comprises a transmission gate and an inverter to block the signal path only during a predetermined time period when the delay unit pulse is activated. The apparatus of claim 1, wherein the delay unit comprises: a first inverter for inverting an internal lath signal; Second, third and fourth inverters connected to the first inverter in series and being inverted to output a delayed signal; And a NOR gate configured to logically perform an output of the first inverter, an output of the fourth inverter, and a signal inverting the power signal, and output a delayed pulse signal to a switching unit. The las signal input buffer circuit of claim 1, wherein the latch unit is configured such that two inverters are circulated with each other.