KR0120559B1 - Toggle and buffering apparatus - Google Patents

Abstract

A toggle and buffer is provided, which includes toggling means(10) for inputting external input clock(CK) and period selection control signal(CNT) to generate clock synchronized to input clock(CK); an inverter having second PMOS transistor(PM2), first PMOS transistor(PM1), first NMOS transistor(NM1) and second NMOS transistor(NM2); third and fourth PMOS transistor(PM3,PM4); and an inverting means(IV2) for inverting the signal.

Description

Device for Toggle and Buffering

1 is a block diagram of a device for conventional toggle and buffering.

2 is a circuit diagram of an apparatus for toggle and buffering according to an embodiment of the present invention.

3 is an operating characteristic diagram of an apparatus for toggle and buffering according to an embodiment of the present invention.

4 is a block diagram of an apparatus for extended toggle and buffering according to another embodiment of the present invention.

The present invention relates to a device for toggling and buffering, and more particularly to a device for toggling and buffering which can selectively generate a signal having the same and double periods thereof using an input clock signal.

In general, a toggle and buffering device used in a digital system is composed of a flip-flop and a combinational logic circuit having a toggle characteristic.

An apparatus for a conventional toggle and buffer work having the above structure will be described with reference to FIG.

Referring to (a) of FIG. 1, a conventional toggle and a buffer may include a toggle flip-flop 1 for doubling the period of the clock signal CK input through the input terminal IP1 and an input terminal IP2. And a multiplexer 2 for selectively outputting the output signal of the toggle flip-flop 1 and the clock signal CK input through the input terminal IP1 by the input period selection control signal CNT.

Referring to the operation of the conventional toggle and buffering device having the above structure as follows.

The clock signal CK input through the input terminal IP1 is directly applied to the multiplexer 2, and the cycle is doubled by the toggle flip-flop 1 and applied to the multiplexer 2. At this time, the multiplexer 2 has a double cycle due to the clock signal CK and the toggle flip-flop 1 directly input through the input terminal IP1 by the period selection control signal CNT input through the input terminal IP2. Selects the increased clock signal DEOUT and outputs it through the output terminal OUT.

However, in the case of the conventional toggle and buffering device as described above, there is a problem that the initial phase is random after selecting the period of the input clock signal.

In order to solve this problem, conventionally, the initial phase is controlled by using a latch as shown in FIG.

Referring to FIG. 1 (b), the conventional toggle and buffering device has a toggle flip-flop 1 and a multiplexer 2, like (a) of FIG. 1, and is also input through the input terminal IP2. And a latch 3 for temporarily storing the selected period selection control signal CNT to prevent randomization of the initial phase of the clock signal CK input through the input terminal IP1.

Referring to the operation of the conventional toggle and buffering device having a structure as shown in (b) of FIG. 1 as follows.

The operation of selecting and outputting the period of the clock signal CK input through the input terminal IP1 is illustrated in FIG. 1A, and the latch 3 is a period selection control signal inputted through the input terminal IP2. CNT is stored and applied to the multiplexer so that the output signal of the multiplexer 2 according to the cycle change of the clock signal CK input through the input terminal IP1 has a constant phase according to the phase of the clock signal CK. .

However, such a conventional toggle and buffering device occupies a large area in the chip by using too many logic gates and flip-flops, and there is a problem in that the efficiency of the signal is inferior. .

Accordingly, the present invention to solve the above problems is to provide a device for toggle and buffering that can reduce the area of the chip by using logic gates without using a flip-flop, and also can improve the synchronous efficiency of the signal The purpose is to provide.

Toggle and buffering apparatus of the present invention for achieving the above object comprises a toggling means for receiving an input clock signal and a period selection control signal input from the outside to generate and output a clock signal synchronized with the input clock signal; A second PMOS transistor connected in series from a power supply voltage terminal to a ground terminal, in which an output signal of the toggling means is applied to a gate, a first PMOS transistor in which an inverted clock signal is applied to a gate, its own output terminal, and the input An inverter comprising a first NMOS transistor to which a clock signal is applied to a gate and a second NMOS transistor to which an output signal of the toggling means is applied to the gate; Third and fourth PMOS transistors connected in series with the first and second PMOS transistors in parallel between the power supply voltage terminal and the output terminal of the inverter, and the input clock signal and the period selection control signal applied to a gate, respectively; And inverting means for inverting and outputting the signal.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2, 3 and 4.

Referring to FIG. 2, the apparatus for toggling and buffering of the present invention receives a clock signal synchronized with the input clock signal CK by receiving an input clock signal CK and a period selection control signal CNT input from the outside. A second PMOS transistor (PM2) to which the toggling means (10) which is generated and output is connected in series from the power supply voltage terminal to the ground terminal, and the output signal of the toggling means (10) is applied to the gate, and the inverted clock signal Output signal of the first PMOS transistor PM1 to which (/ CK) is applied to the gate, its own output terminal, the first NMOS transistor NM1 to which the input clock signal CK is applied to the gate, and the toggling means 10 Is connected in series with the first and second PMOS transistors PM1 and PM2 in parallel between an inverter consisting of a second NMOS transistor NM2 and a power supply voltage terminal and an output terminal of the inverter, and an input clock signal CK ) And the period select control signal (CNT) Each is applied to the third and the fourth and the PMOS transistor (PM3, PM4), which includes the inverting means (IV2) for inverting the output signal.

In the toggling means 10, an input clock signal CK input from the outside is applied to the P-type and N-type gates, and an inverted input clock signal / CK is applied to the N-type and P-type gates, respectively. First and second transmission gates TRG1 and TRG2, an input terminal of which is connected to an output terminal of the first transmission gate TRG1, an input terminal of which is connected to an output terminal of the second transmission gate TRG2, and an output terminal of the first and second transmission gates TRG1 and TRG2. A logic NAND by logic NAND of the inverter IV3 connected to the input terminal of the first transmission gate TRG1, the output signal of the inverter IV4 input to one input terminal, and the period selection control signal CNT inputted to the type force terminal. And a NAND gate NAG for outputting a value to the second transmission gate TRG2.

Referring to the operation of the device for the toggle and buffering of the present invention having the above structure as follows.

First, an output process of the output clock signal DEOUT having a double cycle of the input clock signal CK through the output terminal OUT will be described.

When the high state period selection control signal CNT is input through the second input terminal IP2 and the high state clock signal CK is input through the first input terminal IP1, the second transmission gate TRG2 is turned on. The clock signal logically napped by the NAND gate NAG is applied to the inverter IV3 through the second transmission gate TRG2, and the clock signal, which is a logical NAND value, is inverted by the inverter IV3 to invert the first transmission gate. Is applied to (TRG1). At this time, when the period selection control signal CNT is kept high and the low state clock signal CK is input through the first input terminal IP1, the first transmission gate TRG1 is turned on to turn off the inverter IV3. The output logic NAND clock signal is transmitted to the inverter IV4. The inverter IV4 then inverts the logic NAND value inverted by the inverter IV3 to convert the synchronization signal of the input clock signal CK into the node N1. )

At this time, when the high state input clock signal CK is input through the first input terminal IP1, the first PMOS and the first NMOS transistors PM1 and NM1 are turned on to drive the CMOS inverter 20. When the high state clock signal is applied from the node N1, the CMOS inverter 20 inverts the high state clock signal and outputs the low state clock signal to the node N2.

Subsequently, when the low state input clock signal CK is input through the first input terminal IP1 and the high state clock signal is transmitted from the node N1, the first PMOS and the first NMOS transistors PM1 and NM1 are turned off and the CMOS inverter is turned off. (20) is stopped so that the clock signal of the node N2 remains low.

Subsequently, the inverting means IV2 inverts the low state clock signal of the node N2 and outputs the high state output clock signal DEOUT through the output terminal OUT.

In addition, the output clock signal DEOUT goes low through the reverse process.

Therefore, when the high state clock signal is input through the second input terminal IP2 as described above, the first NMOS transistor NM1, the second PMOS transistor PM2, and the CMOS inverter 20 are input by the above-described process. The output clock signal DEOUT having a period twice the clock signal CK is outputted. Next, an output process of the output clock signal DEOUT having the same period as the input clock signal CK through the output terminal OUT will be described.

When the low state period selection control signal CNT is input through the second input terminal IP2 and the high state clock signal CK is input through the first input terminal IP1, the second transmission gate REG2 is turned on. The high state clock signal logic NAND by the NAND gate NAG is applied to the inverter IV3 through the second transmission line gate TR2, and the high state clock signal which is the logic NAND value by the inverter IV3 is inverted. And is applied to the first transmission gate TRG1. At this time, when the period selection control signal CNT is kept high and the low state clock signal CK is input through the first input terminal IP1, the first transmission gate TRG1 is turned on to turn off the inverter IV3. The output logic NAND low state clock signal is transferred to the inverter IV4. The inverter IV4 then inverts the logic NAND value inverted by the inverter IV3 again, thereby causing a high state synchronization signal of the input clock signal CK. Is output to node N1.

Subsequently, the second PMOS transistor PM2 is turned off and the second NMOS transistor NM2 is turned on by the high state clock signal of the node N1.

As described above, the second NMOS and the third PMOS transistors NM2 and PM3 are turned on by the period selection control signal CNT input through the second input terminal IP2, and the high state is transmitted through the first input terminal IP1. When the clock signal CK is input, the fourth PMOS transistor PM4 is turned off and the first NMOS transistor NM1 is turned on to output a low state clock signal to the node N2. The inverting means IV2 then receives the node ( The clock signal in the low state of N2) is inverted to output the output clock signal DEOUT having the same period as the input clock signal CK through the output terminal OUT.

In addition, when the low state clock signal CK is input through the first input terminal IP1 in the above state, the fourth PMOS transistor PM4 is turned on and the first NMOS transistor NM1 is turned off to the node N2. The high state clock signal is output, and then the inverting means IV2 inverts the high state clock signal of the node N2 to output the output clock signal DEOUT having the same period as the input clock signal CK. Output through

Accordingly, when the period selection control signal CNT in the low state is input through the second input terminal IP2, the first and second NMOS transistors NM1 and NM2 and the third and fourth PMOS transistors are processed by the above process. The PM3 and PM4 output the output clock signal DEOUT having the same period as the input clock signal 9CK.

Referring to Figure 3 will be described in detail the operation of the present invention.

Referring to FIG. 3, (A) is a clock signal (CK) input through the first input terminal, (B) is a clock signal (/ CK) inverted by the first inverter (IV1), (C) is The period selection control signal CNT and (D) input through the second input terminal IP2 are the clock signal DEOUT output through the output terminal OUT.

While the cycle select control signal CNT of (C) is kept high, the output clock signal DEOUT of (D) having a double period of the clock signal CK of (A) receives the output terminal OUT. Is output via

At this time, the transition of the output clock signal DEOUT of (D) is made only in the falling edge section of the clock signal CK of (A).

In addition, while the period selection control signal CNT of (C) is kept low, the output clock signal DEOUT of (D) having the same period as the clock signal CK of (A) is output terminal OUT. Is printed through).

Another embodiment of the toggle and buffer of the present invention will be described with reference to FIG.

As shown in FIG. 4, a plurality of toggles and buffers 10-1 to 10-n of the present invention consisting of the toggle and buffer circuit of FIG. 3 are connected.

The period selection control signal CNT input through the second input terminal IP2 is input to each one input terminal of the plurality of toggles and the buffers 10-1 and 10-n, and is input through the first input terminal IP1. The clock signal CK is input to the type power stage of the toggle and buffer 10-1, and the output clock signal CK or 2 * CK of the toggle and buffer 10-1 is toggle and buffer 10-2. And the output clock signal CK or 2 ² * CK of the toggle and buffer 10-1 is input to the next force and the type force stage of the buffer.

According to the above process, the period selection control signal CNT is input to one input terminal of the toggle and buffer 10-n, and the previous toggle and buffer 10- (n-1), which is not shown in the drawing, as the type force stage. The output clock signal CK or 2 ^(n-1) * CK is input, and the toggle and buffer 10-n are then output by the output clock signal CK or ²ⁿ * CK to the output terminal.

When the low state period selection control signal CNT is applied to each one input terminal of the plurality of toggles and the buffers 10-1 to 10-n, the output clock signal CK which is not extended to each output terminal is outputted. On the contrary, when the high state period selection control signal CNT is applied to each of the type force stages of the plurality of toggles and the buffers 10-1 to 10-n, respectively, the output state of the toggle and the buffer 10-n is determined. The output clock signal 2 ⁿ * CK is output.

Therefore, the toggle and buffer of the present invention sequentially connects n toggles and buffers as described above, and inputs a high state period selection control signal CNT to perform a cycle of 2 ⁿ times through the output terminal of the n th toggle and buffer. Can have a clock signal (2 ⁿ * CK).

As described above, the toggle and buffer of the present invention can reduce the area of the chip, improve the efficiency of the synchronization of the clock signal by using an appropriate number of logic gates and MOS transistors, and also enable multiple toggles. And buffers are sequentially connected to provide an excellent effect of outputting a clock signal extended in multiples of two.

Claims (2)

Toggling means for receiving an input clock signal and a period selection control signal input from the outside to generate and output a clock signal synchronized with the input clock signal; A second PMOS transistor connected in series from a power supply voltage terminal to a ground terminal, the output signal of the toggling means being applied to the gate, the first PMOS transistor to which the inverted clock signal is applied to the gate, its own output terminal, and the input clock signal An inverter comprising a first NMOS transistor applied to a gate and a second NMOS transistor to which an output signal of the toggling means is applied to the gate; Third and fourth PMOS transistors connected in series with the first and second PMOS transistors in parallel between the power supply voltage terminal and the output terminal of the inverter, and the input clock signal and the period selection control signal applied to a gate, respectively; And inverting means for inverting and outputting the signal. 2. The method of claim 1, wherein the toggling means comprises: a first input to which the input clock signal input from the outside is applied to the P-type and N-type gates, and the inverted input clock signal is applied to the N-type and P-type gates, respectively. And a second transmission gate; A first inverter having an input terminal connected to an output terminal of the first transmission gate; A second inverter having an input terminal connected to an output terminal of the second transmission gate and an output terminal connected to an input terminal of the first transmission gate; And a NAND gate for outputting a logic NAND value to the second transmission gate by logic NAND of an output signal of the first inverter input to one input terminal and the period selection control signal input to a type force stage. And device for buffering.