KR20020054112A - Fabrication method of Mulichip module substrate with embedded passive components - Google Patents

Abstract

PURPOSE: A method for fabricating a multichip module(MCM) substrate having a passive device is provided to reduce the size of the MCM substrate and to increase a signal rate of an MCM, by increasing interconnection density of the MCM substrate. CONSTITUTION: The first metal layer as a power layer, the second metal layer(114) and the third metal layer are sequentially formed on a base substrate of the MCM substrate. A capacitor and a resistor are formed between the power layer and the second metal layer in the same process. The resistor is made of NiCr. The power layer, the second metal layer and the third metal are stack structures composed of a seed metal layer and a main metal layer.

Description

Fabrication method of Mulichip module substrate with embedded passive components

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi chip module (MCM) substrate and a method of manufacturing the same. In particular, a multi chip module substrate can be reduced in size by forming resistors, capacitors, and inductors, which are passive elements. It relates to a chip module substrate and a method of manufacturing the same.

In general, semiconductor devices are individual packages, whereas multi-chip modules are packaged and printed circuit board (PCB) by mounting several semiconductor bare chips and passive devices (resistors, capacitors, and inductors) on a single substrate. : Package technology to reduce delay time in printed circuit board, which has advantages of miniaturization, high speed, and high reliability of boards compared to existing technologies using individual semiconductor devices and passive devices. It is a new package technology used in communication systems, portable terminals, automobiles, and military equipment.

Multi-chip modules are classified into MCM-L, MCM-C, and MCM-D according to the type of substrate used. MCM-L uses FR-4 (Fire Resistant Epoxy Bonded Fiber Glass), a general printed circuit board (PCB) material. It is used as a substrate material. It is mainly used for systems below 100 MHz, which do not require high speed, are inexpensive, and have low heat dissipation.

MCM-D uses silicon or ceramics in the manufacture of substrates, and because it uses a semiconductor process, the wiring density is high, and it is used for high speed, high temperature, and high performance modules. The wiring density of MCM-C is about MCM-L, but ceramics are used as the substrate, so the heat dissipation characteristics are good.

On the other hand, according to the recent trend of miniaturization of all electronic equipment, the miniaturization of the multi-chip module is also required. In order to miniaturize the multi-chip module, the size of the multi-chip module substrate must be reduced. However, the multi-chip module substrate has a limitation in reducing the size of the substrate because an area in which several bare chips are to be mounted and an area in which a plurality of passive elements are mounted around the bare chip must be secured. In particular, in the mixed signal, many passive elements are mounted around the bare chip, compared to the existing digital signal, so that the area of the multi-chip module substrate may be larger to accommodate the bare chip and the passive element. As described above, since the size of the multi-chip module substrate is limited, it is difficult to miniaturize the multi-chip module.

In addition, passive components such as resistors, capacitors, and inductors are mounted in chip form on a multi-chip module substrate. However, in a high-speed mixed signal, the passive components in the form of chips act as resistance components of the signal, thereby reducing the speed of the multi-chip module. As a factor, there is a problem of degrading the performance and reliability of the multi-chip module.

In order to solve this problem, if the passive element is embedded in the substrate, the interconnection length is shortened, the signal speed is increased, and the surface mount is mounted inside the substrate, thereby reducing the substrate area.

However, in order to embed a passive element in a substrate, mutual stability (process conditions) between the structure and the manufacturing process of the substrate must be ensured. The manufacturing process of the substrate varies depending on the type of substrate, insulating film, and metal wiring used. There is no standardized structure and manufacturing method.

Meanwhile, as a prior art related to a multi-chip module, U.S. Patent No. 5,544,017 (Inventor: Beilin, Solomon I, Country: USA, Name of the Invention; multichip module substrate, Registered Date: July 19, 1994) includes a general cross-sectional structure. Since chip-mounted substrates are placed on a support base and connected to a connector in the z-axis direction, a high-performance module is described by implementing a multi-chip module having a three-dimensional structure.

In addition, U.S. Patent No. 5,633,530 (Inventor: Hsu, Chen-Chung, Country: Taiwan, Name of the Invention: Multichip module having a multi-level configuration, date of registration; October 24, 1995) has a framework called Module Template. It is described to manufacture a multifunctional module capable of mounting a plurality of semiconductor chips in one module by packaging the semiconductor chips in a multilayer using.

However, all these prior arts are aimed at multifunctionalization of a multi-chip module, and since passive devices are mounted in a chip form, there is a limit in miniaturization as described above. Therefore, it is necessary to reduce the board size of the multi-chip module by embedding passive elements used in the multi-chip module on the substrate for miniaturization.

Therefore, the present invention forms passive elements (resistors, capacitors, inductors) in any part of the internal signal layer of the substrate, thereby reducing the size of the substrate used in the multi-chip module and miniaturizing the multi-chip module. It is an object of the present invention to provide a multi-chip module substrate, and to provide a multi-chip module substrate manufacturing method capable of securing stability of a substrate manufacturing process by embedding a passive device in the multi-chip module substrate.

1A to 1B are process diagrams illustrating a method for manufacturing a passive chip embedded multi-chip module substrate according to an embodiment of the present invention.

※ Explanation of code about main part of drawing ※

101 base substrate 102 first insulating film

103: first seed metal layer 104: first main metal layer

105: first metal layer 106: second insulating film

107: first via hole 108: first photosensitive film

109: resistive material 109-a: capacitor

109-b: resistance 110: low dielectric insulating film

111: second seed metal layer 112: photosensitive film

113; 2nd main metal layer 114: 2nd metal layer

According to the present invention for achieving the above object, the first metal layer (power supply layer), the second metal layer, the pad layer is sequentially disposed on the base substrate with a low dielectric insulating film 110 having a via hole therebetween. In the multi-chip module substrate formed, the multi-chip module substrate, characterized in that the capacitor 109-a and the resistor 109-b are formed between the power supply layer and the second metal layer 114.

The first insulating film 102, the power supply layer 105, the second insulating film 106, the low dielectric insulating film, and the second metal layer 114 are sequentially stacked on the base substrate. A multi-chip module substrate is provided on which a resistor and a capacitor are formed, and an inductor is formed from the second metal layer 114.

In addition, a first step of depositing titanium (Ti) and copper (Cu) as a seed metal on a base substrate (silicon wafer) by a sputtering method, and then patterning a power layer to be plated by a photo process; A second step of plating the copper layer deposited in the first step by electroplating to strip a photoresist and etching the seed metal to form a power layer; A third step of forming an insulating film having via holes on the power supply layer, applying a photosensitive film on the insulating film, and patterning a resistive material deposition layer to form a capacitor electrode and a resistor by a photo process; Depositing a resistive material on the photoresist layer and forming a resistor with the capacitor electrode using a lift-off process; After applying a low dielectric insulating film on the resultant of the fourth step, forming a via hole by a photolithography process, seed metal is deposited on the entire substrate by a sputtering method, and the photoresist film is spin coated and patterned. A fifth step of electroplating to form a second metal layer; Thereafter, the third metal layer is formed by performing the sixth step process in the same process sequence as the fifth step. That is, after applying a low dielectric insulating film, forming a via hole by a photolithography process, depositing seed metal on the entire substrate by sputtering, spin coating the photoresist, and patterning the same, followed by electroplating There is provided a multi-chip module substrate manufacturing method comprising the sixth step of forming a metal layer.

Embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

1A to 1B are process diagrams illustrating a method for manufacturing a passive chip embedded multi-chip module substrate according to an embodiment of the present invention.

First, as shown in FIG. 1A, a Si ₃ N ₄ layer is formed on the base substrate 101 using the first insulating film 102, and then the first seed metal layer 103 and the first insulating film 102 are formed on the first insulating film 102. 1, the main metal layer 104 is sequentially raised to form a first metal layer 105 which is a power source layer.

In this case, the first seed metal layer 103 is formed by stacking titanium (Ti) and copper (Cu), and the first main metal layer 104 is formed by plating copper (Cu) by an electroplating method. . Subsequently, after the Si ₃ N ₄ layer is formed on the first metal layer with the second insulating film 106, a capacitor first formed on the first insulating film layer 102 on a portion of the second insulating film 106. A first via hole 107 is formed to connect an electrode with a pad to be formed in the third metal layer, and the first photoresist layer 108 is formed on the second insulating layer 106 including the first via hole. After coating, the resistive material layer 109 is deposited on the entire structure after the photoresist layer is removed by patterning a portion where the resistive material is to be deposited to form a resistor and a capacitor.

In this case, the resistive material layer 109 is formed by depositing nickel chromium (NiCr) by a thermal evaporator method. In addition, in consideration of a lift-off process, the coating thickness of the first photoresist layer 108 may be formed to be 2 to 3 times or more thick than the deposition thickness of the resistive material layer 109.

Subsequently, as shown in FIG. 1B, the first photoresist layer 108 and the resistive material layer 109 formed thereon are simultaneously removed through a lift-off process, thereby allowing the second insulating layer 106 to pass through the first opening. A layer of resistive material 109 formed on the substrate remains, and the remaining layer of resistive material becomes the resistor 109-b, which is a passive element, and the second electrode 109-a of the capacitor.

Subsequently, as shown in FIG. 1C, after the first low dielectric insulating layer 110 is coated on the second insulating layer 106 including the resistor and the capacitor second electrode to form a second via hole, the first low dielectric insulating layer is formed. The second seed metal layer 111 is formed on the layer 110.

Subsequently, as illustrated in FIG. 1D, the second photosensitive film 112 is coated on the second seed metal layer 111.

Subsequently, as shown in FIG. 1E, the photoresist is removed by patterning both ends of the resistor, the second electrode of the capacitor, and the portion of the inductor to form the first electrode layer, and then form the second main metal layer 113.

Subsequently, the second metal layer 114 is formed by stripping the photoresist film as shown in FIG. 1F.

Subsequently, the second electrode layer of the inductor is formed on the second metal layer by forming a third via hole by applying a second low dielectric layer in the same manner as described above, and then forming a third seed metal layer using the first seed metal layer ( It is formed by stacking titanium (Ti) and copper (Cu) in the same manner as in 103, and the third main metal layer is plated with copper (Cu) by electroplating in the same manner as the first main metal layer 113. Is formed.

In the above-described process, the manufacture of the multi-chip module substrate including the passive element including the resistor, the capacitor, and the inductor of the present embodiment is completed. In order to embed the resistor in the multi-chip module substrate, a base substrate, which is a basic component of the multi-chip module substrate, is manufactured. The inter-process stability with the metal layer and the insulating film manufacturing process should be ensured. That is, the temperature of the resistance forming process should be a temperature at which the base substrate 101, the first metal layer 105, the first insulating film 102 and the second insulating film 106 already exist before the resistance is formed, and In the process of forming the second metal layer 114, the third insulating layer, and the third metal layer after the resistor is formed, the inherent properties of the resistor should not be changed.

The present embodiment is formed by depositing each seed metal layer (103, 111) at room temperature in a sputtering method using titanium and copper to ensure such process stability, and the main metal layer is also at room temperature using copper It is formed by plating, and the resistor 109-b is formed at room temperature using nickel chromium. In addition, the insulating films 102 and 106 and the low dielectric insulating film 110 are formed using Si ₃ N ₄ and benzocyclobutene (BCB), respectively, and the insulating film Si ₃ N ₄ layer is 90% cured by BCB. It is deposited at a temperature range of 200 ° C. to 250 ° C., and BCB is also coated at room temperature.

By the way, the melting point of titanium is 1600 degreeC or more, the melting point of copper is very high, 1000 degreeC or more, BCB hardens at 250 degreeC, and deforms at 350 degreeC or more. On the other hand, since nickel chromium, which is a resistor, is deposited at room temperature, nickel chromium does not damage the insulating layer or the metal layer of the lower layer during deposition, and is dissolved at 1300 ° C. or higher, so that the curing temperature of BCB, the third insulating layer of the upper layer, is 250. It is not damaged at ℃.

Therefore, the process stability is sufficiently secured in simultaneously fabricating the resistor and the capacitor of the present embodiment, and in manufacturing the passive chip embedded multi-chip module substrate including both inductors.

The technical details of the present invention have been described above with reference to the accompanying drawings, which are illustrative examples of the preferred embodiments of the present invention and are not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

As described above, the present invention has the effect of reducing the number of processes by simultaneously producing a resistor and a capacitor.

In addition, by embedding the passive element in the multi-chip module substrate, the interconnect density of the multi-chip module substrate can be increased, thereby reducing the size of the multi-chip module substrate and increasing the signal speed of the multi-chip module. It has the effect of speeding up.

In addition, the present invention forms a resistance by depositing nickel chromium that can be deposited at a temperature at which the base substrate, each layer and the insulating film are not deformed, and by depositing the insulating film at 250 ° C. when forming a capacitor, process stability is ensured, thereby multi-chip module substrate. This has the effect of easily embedding resistors, capacitors, and inductors.

Claims (17)

In the multi-chip module substrate in which the power supply layer (first metal layer), the second metal layer, and the third metal layer are sequentially formed on the base substrate with the low dielectric insulating film 110 having a via hole interposed therebetween. Multi-chip module substrate, characterized in that the capacitor (109-a) and the resistor (109-b) are formed together in the same process between the power supply layer and the second metal layer (114). The method of claim 1, The low dielectric insulating film is a multi-chip module substrate, characterized in that the nitride film having a process stability by being deposited in a temperature range that does not damage the already produced substrate. The first insulating film 102, the power supply layer 105, the second insulating film 106, the low dielectric insulating film, and the second metal layer are sequentially stacked on the base substrate, A resistor and a capacitor are formed on the second insulating film 106, An inductor is formed on the second metal layer and the third metal layer. The method according to claim 1 or 3, The resistor (109-b) is a multi-chip module substrate, characterized in that formed of nickel chromium (NiCr). The method according to claim 1 or 3, The power supply layer, the second metal layer and the third metal layer is a multi-chip module substrate, characterized in that the laminated structure of the seed metal layer and the main metal layer. The method of claim 5, The seed metal layer is a multi-chip module substrate, characterized in that the titanium (Ti) and copper (Cu) is laminated. The method of claim 5, The main metal layer is a multi-chip module substrate, characterized in that formed of copper (Cu). The method according to claim 1 or 3, The low dielectric insulating film is a multi-chip module substrate, characterized in that the benzo cyclobutene (BCB: photosensitive polyimide). The method of claim 3, wherein The first insulating film and the second insulating film is a multi-chip module substrate, characterized in that the nitride film having a process stability by being deposited in a temperature range that does not damage the already produced substrate. A first step of depositing titanium (Ti) and copper (Cu) as a seed metal on a base substrate (silicon wafer) by sputtering, and then patterning a power layer to be plated by a photo process; A second step of plating the copper layer deposited in the first step by electroplating to strip a photoresist and etching the seed metal to form a power layer; Forming an insulating film having via holes on the power supply layer, applying a photoresist film on the insulating film, and patterning a resistive material deposition layer to form a capacitor electrode and a resistor by a photo process; Depositing a resistive material on the photoresist layer and forming a resistor with the capacitor electrode by using a lift-off process; A fifth step of forming a second metal layer on which the low dielectric insulating film, the seed metal layer, and the main metal layer having via holes are stacked on the resistive material layer; And A sixth step of forming a third metal layer in the same process order as the fifth step; Multi-chip module substrate manufacturing method comprising a. The method of claim 10, The capacitor electrode formed in the third step is formed so that the thickness is 0.1㎛ or less. The method of claim 10, The low dielectric insulating film is a photosensitive polyimide benzo cyclobutene (BCB: Benzocyclobutene) characterized in that the manufacturing method of the multi-chip module substrate. The method according to claim 10 or 12, And the insulating film is a nitride film. The method of claim 13, The process temperature for depositing the nitride film (Si ₃ N ₄ ) is a method of manufacturing a multi-chip module substrate, characterized in that the benzo cyclobutene ranges from 200 ℃ to 250 ℃ to cure about 90%. The method of claim 10, The seed metal layer is a method of manufacturing a multi-chip module substrate, characterized in that formed by sequentially depositing titanium (Ti) and copper (Cu) at room temperature in a sputtering method. The method of claim 10, The first metal layer, the second metal layer and the third metal layer is a multi-chip module substrate manufacturing method, characterized in that formed by electroplating copper at room temperature. The method of claim 10, The third step, Forming a photoresist film on the insulating layer, the photosensitive film having an open portion at which the resistance is to be formed, and then depositing nickel chromium at room temperature by a thermal evaporator method; And Simultaneously removing the photoresist and the nickel chromium deposited thereon through a lift-off process; Multi-chip module substrate manufacturing method comprising a.