KR20020051487A - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- KR20020051487A KR20020051487A KR1020000080710A KR20000080710A KR20020051487A KR 20020051487 A KR20020051487 A KR 20020051487A KR 1020000080710 A KR1020000080710 A KR 1020000080710A KR 20000080710 A KR20000080710 A KR 20000080710A KR 20020051487 A KR20020051487 A KR 20020051487A
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- semiconductor device
- forming
- gate electrode
- channel region
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 7
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 STI(Shallow Trench Isolation) 구조를 이용한 반도체소자 및 그 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device using a shallow trench isolation (STI) structure and a method of manufacturing the same.
이하 첨부도면을 참조하여 종래기술에 따른 반도체 소자의 제조 방법을 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도 1은 종래기술의 따른 반도체소자의 구조 단면도로서, 반도체기판(11)상에 폴리실리콘으로 이루어진 게이트전극(12)을 형성한 후, 게이트전극(12)을 마스크로 이용한 불순물 이온주입으로 소스 영역(13b)과 드레인 영역(13a)을 형성한 후, 전면에 층간절연막(14)을 형성한다. 층간절연막(14)을 선택적으로 패터닝하여 반도체기판(11), 즉 소스 영역(13b)과 드레인 영역(13a)의 소정 부분이 노출되는 금속배선용 콘택홀을 형성한다.1 is a cross-sectional view illustrating a structure of a semiconductor device according to the related art, in which a gate electrode 12 made of polysilicon is formed on a semiconductor substrate 11, and then a source region is formed by implanting impurity ions using the gate electrode 12 as a mask. After the 13b and the drain region 13a are formed, the interlayer insulating film 14 is formed over the entire surface. The interlayer insulating film 14 is selectively patterned to form contact holes for the metal wirings in which the semiconductor substrate 11, that is, predetermined portions of the source region 13b and the drain region 13a are exposed.
후속 공정으로 금속배선용 콘택홀에 금속막을 증착한 후 패터닝하여 소스콘택(15b)과 드레인콘택(15a)을 형성한다.In a subsequent process, a metal film is deposited in the contact hole for metal wiring and then patterned to form a source contact 15b and a drain contact 15a.
도 2는 도 1의 A-A'선에 따른 반도체 소자의 평면도로서, 채널영역(L)에 의해 전류량이 전류량(CP)이 결정됨에 따라, 즉, 전류량에 의해 트랜지스터의 속도가 결정된다.FIG. 2 is a plan view of the semiconductor device along the line AA ′ of FIG. 1, and as the amount of current CP is determined by the channel region L, that is, the speed of the transistor is determined by the amount of current.
그러므로, 속도가 빠른 트랜지스터를 구현하고자 하면 칩 면적이 증가하는 문제점이 있어, 고집적 반도체소자의 제조에는 한계가 있다.Therefore, there is a problem in that the chip area is increased when a fast transistor is to be implemented, and thus there is a limitation in manufacturing a highly integrated semiconductor device.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 채널영역의 증가에 따른 칩 면적의 증가를 방지하여 고속으로 동작하는데 적합한 고속 트랜지스터의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a method of manufacturing a high speed transistor suitable for operating at high speed by preventing an increase in chip area due to an increase in a channel region.
도 1은 종래기술에 따른 반도체 소자의 구조 단면도,1 is a structural cross-sectional view of a semiconductor device according to the prior art,
도 2는 도 1의 A-A'선에 따른 반도체 소자의 평면도,2 is a plan view of a semiconductor device taken along line AA ′ of FIG. 1;
도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도,3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;
도 4a는 도 3e의 B-B'선에 따른 반도체 소자의 구조 사시도,4A is a structural perspective view of a semiconductor device taken along a line BB ′ of FIG. 3E;
도 4b는 도 3e의 B-B'선에 따른 반도체 소자의 평면도,4B is a plan view of the semiconductor device taken along the line BB ′ of FIG. 3E;
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 트렌치 마스크21 semiconductor substrate 22 trench mask
23 : 채널영역 24 : 폴리실리콘23: channel region 24: polysilicon
24a : 게이트전극 25 : 게이트 마스크24a: gate electrode 25: gate mask
26 : 이온주입마스크 27a,27b : 드레인영역, 소스영역26: ion implantation mask 27a, 27b: drain region, source region
28 : 층간절연막 29 : 금속콘택28: interlayer insulating film 29: metal contact
상기의 목적을 달성하기 위한 본 발명의 반도체 소자는 반도체기판, 상기 반도체기판을 트렌치 식각하여 형성된 실리콘기둥 형태의 채널영역, 상기 채널영역의 상측 및 측면을 둘러싸는 게이트전극, 및 상기 게이트전극 양측의 상기 식각된 반도체기판에 형성된 소스/드레인 영역을 포함하여 이루어짐을 특징으로 한다.A semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a channel region of a silicon pillar formed by trench etching the semiconductor substrate, a gate electrode surrounding the upper and side surfaces of the channel region, and both sides of the gate electrode And a source / drain region formed on the etched semiconductor substrate.
본 발명의 반도체 소자의 제조 방법은 반도체기판을 트렌치 식각하여 기둥형태의 채널영역을 형성하는 단계, 상기 채널영역의 상측 및 측면을 둘러싸는 게이트전극을 형성하는 단계, 및 상기 게이트전극 양측의 트렌치 식각된 반도체기판에 불순물을 이온주입하여 소스/드레인 영역을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a semiconductor device of the present invention, forming a columnar channel region by trench etching a semiconductor substrate, forming gate electrodes surrounding upper and side surfaces of the channel region, and trench etching on both sides of the gate electrode. And implanting impurities into the semiconductor substrate to form source / drain regions.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3e는 본 발명의 실시예에 따른 고속 트랜지스터의 제조 방법을 나타낸 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a high speed transistor according to an exemplary embodiment of the present invention.
도 3a에 도시된 바와 같이, 반도체기판(21)에 통상적인 반도체 소자의 소자 분리(Isolation; ISO) 방법 중 하나인 STI(Shallow Trench Isolation) 방법을 이용하여 필드산화막(도시 생략)을 형성하여 활성영역과 필드영역을 정의한다. 여기서, STI 방법은 통상적으로 반도체기판을 식각하여 홈을 형성하고 그 홈에 갭필특성이 우수한 절연막을 매립시켜 활성영역을 한정한다.As shown in FIG. 3A, a field oxide film (not shown) is formed on the semiconductor substrate 21 by using a shallow trench isolation (STI) method, which is one of conventional isolation (ISO) methods of semiconductor devices. Define the area and field area. In the STI method, a semiconductor substrate is typically etched to form a groove, and an insulating film having excellent gap fill characteristics is embedded in the groove to define an active region.
반도체기판(21)의 활성영역에 웰이온을 주입하여 웰(도시 생략)을 형성하고, 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 트렌치 마스크(22)를 형성한다. 이 때, 활성영역의 소정 부분(T)이 노출되되, 그 사이에 트렌치 마스크(22)가 소정 폭만큼 존재하며, 도면부호 T는 트랜지스터가 형성될 부분을 나타낸다.Well ions are implanted into the active region of the semiconductor substrate 21 to form wells (not shown), and a photoresist film is coated on the entire surface, and patterned by exposure and development to form a trench mask 22. At this time, a predetermined portion T of the active region is exposed, and a trench mask 22 is provided by a predetermined width therebetween, and T denotes a portion where the transistor is to be formed.
도 3b에 도시된 바와 같이, 트렌치 마스크(22)를 마스크로 이용하여 노출된 반도체기판(21)의 소정 부분을 식각하여 트렌치를 형성한다.As shown in FIG. 3B, the trench is formed by etching a predetermined portion of the exposed semiconductor substrate 21 using the trench mask 22 as a mask.
이 때, 트렌치 시각후 형성된 실리콘기둥은 후속 트랜지스터의 채널영역(23)이 형성될 부분이다.At this time, the silicon pillar formed after the trench viewing is the portion where the channel region 23 of the subsequent transistor is to be formed.
계속해서, 전면에 문턱전압 조절을 위한 불순물을 틸트이온주입한다.Subsequently, tilt ions are implanted into the front surface to adjust the threshold voltage.
도 3c에 도시된 바와 같이, 전면에 폴리실리콘(24)을 증착한 후, 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트전극을 패터닝하기 위한 게이트마스크(25)을 형성한다. 이 때, 게이트마스크(25)는 채널영역(23)상에만 형성되고 트렌치 식각된 부분은 노출된다.As shown in FIG. 3C, after the polysilicon 24 is deposited on the entire surface, a photosensitive film is coated on the entire surface and patterned by exposure and development to form a gate mask 25 for patterning the gate electrode. In this case, the gate mask 25 is formed only on the channel region 23, and the trench etched portion is exposed.
도 3d에 도시된 바와 같이, 게이트마스크(25)을 마스크로 이용하여 폴리실리콘(24)을 식각하여 실리콘기둥 형태의 채널영역(23)의 상면 및 측면을 모두 둘러싸는 게이트전극(24a)을 형성한 다음, 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 소스/드레인 영역을 형성하기 위한 이온주입마스크(26)를 형성한다.As shown in FIG. 3D, the polysilicon 24 is etched using the gate mask 25 as a mask to form a gate electrode 24a that surrounds both the top and side surfaces of the channel region 23 in the form of a silicon pillar. Then, a photoresist film is applied to the entire surface and patterned by exposure and development to form an ion implantation mask 26 for forming a source / drain region.
이온주입마스크(26)을 이용하여 고농도 불순물을 틸트이온주입하여 소스영역 (27b) 및 드레인 영역(27a)을 형성한 후, 소스 영역(27b) 및 드레인 영역(27a)에 이온주입된 불순물을 확산시키기 위한 열처리를 실시한다.Tilt-ion implantation of high concentration impurity using the ion implantation mask 26 to form the source region 27b and the drain region 27a, and then implant the ion implanted impurities into the source region 27b and the drain region 27a. Heat treatment is carried out.
도 3e에 도시된 바와 같이, 전면에 층간절연막(28)을 형성한다. 계속해서, 층간절연막(28)을 선택적으로 패터닝하여 게이트전극(24a)의 상측이 노출되는 콘택홀을 형성한 후, 콘택홀을 통해 게이트전극(24a)에 접속되는 금속콘택(29)을 형성한다.As shown in FIG. 3E, an interlayer insulating film 28 is formed on the entire surface. Subsequently, the interlayer insulating film 28 is selectively patterned to form a contact hole through which the upper side of the gate electrode 24a is exposed, and then a metal contact 29 connected to the gate electrode 24a is formed through the contact hole. .
도 4a 및 4b는 도 3e의 B-B'선에 따른 사시도 및 평면도로서, 채널영역(23)이 평면뿐만 아니라 양측면에서도 존재하여 단위면적당 전류량(CP)을 증가시킴을 알 수 있다.4A and 4B are a perspective view and a plan view along the line BB ′ of FIG. 3E, and it can be seen that the channel region 23 exists not only in the plane but also in both sides, thereby increasing the amount of current per unit area CP.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 트랜지스터의 제조 방법은 동일한 면적에서 동작속도가 빠른 트랜지스터를 구현할 수 있으로 고속동작이 요구되는 로직소자, 메모리소자에 적용가능한 효과가 있다.The method of manufacturing a transistor of the present invention as described above can implement a transistor having a high operating speed in the same area, there is an effect that can be applied to logic devices and memory devices that require high-speed operation.
Claims (6)
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| KR1020000080710A KR20020051487A (en) | 2000-12-22 | 2000-12-22 | Semiconductor device and method for fabricating the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100943483B1 (en) * | 2002-12-31 | 2010-02-22 | 동부일렉트로닉스 주식회사 | Method for forming a transistor in a semiconductor device |
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2000
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100943483B1 (en) * | 2002-12-31 | 2010-02-22 | 동부일렉트로닉스 주식회사 | Method for forming a transistor in a semiconductor device |
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