KR20020049938A - Method of forming an epi channel in a semiconductor device - Google Patents
Method of forming an epi channel in a semiconductor device Download PDFInfo
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- KR20020049938A KR20020049938A KR1020000079264A KR20000079264A KR20020049938A KR 20020049938 A KR20020049938 A KR 20020049938A KR 1020000079264 A KR1020000079264 A KR 1020000079264A KR 20000079264 A KR20000079264 A KR 20000079264A KR 20020049938 A KR20020049938 A KR 20020049938A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 29
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
Description
본 발명은 반도체 소자의 에피 채널 형성 방법에 관한 것으로, 특히 실리콘 에피층을 형성한 후 Ge 이온 주입 공정 및 LTP 공정을 실시하여 SiGe 에피층을 형성함으로써 실리콘 기판과의 스트레스를 줄일 수 있고, 이에 따라 원하는 두께의 SiGe 에피층을 균일하게 형성할 수 있어 소자의 특성을 향상시킬 수 있는 반도체 소자의 에피 채널 형성 방법에 관한 것이다.The present invention relates to a method for forming an epitaxial channel of a semiconductor device, and in particular, a silicon epitaxial layer is formed, and then a Ge ion implantation process and an LTP process are performed to form a SiGe epitaxial layer, thereby reducing stress with a silicon substrate. The present invention relates to a method for forming an epi channel of a semiconductor device capable of uniformly forming a SiGe epi layer having a desired thickness, thereby improving the characteristics of the device.
선택적 에피 성장(Selective Epi Growth)을 이용한 에피 채널 소자의 제조 공정에서 실리콘 에피층을 대신하여 SiGe 에피층을 형성하여 소자의 특성을 개선하고 있다. SiGe 에피층은 캐리어(carrier)의 이동도가 실리콘 에피층보다 상대적으로 빨라 전류 특성이 우수하고, 에너지 밴드갭(bandgap)이 실리콘보다 작기 때문에 실리콘을 캐핑(capping)으로 사용할 경우에는 게이트 산화막에서의 터널링 현상을 방지하여 누설 전류를 감소시키는 등 소자의 특성을 상당히 개선시킬 수 있다.In the epitaxial device manufacturing process using selective epitaxial growth, a SiGe epitaxial layer is formed in place of the silicon epitaxial layer to improve device characteristics. Since the SiGe epi layer has relatively higher carrier mobility than the silicon epi layer, the current characteristics are excellent, and the energy bandgap is smaller than that of silicon, so when silicon is used as a capping, The characteristics of the device can be significantly improved by preventing tunneling and reducing leakage current.
그러나, SiGe 에피층 성장 과정에서는 여러가지 해결해야 할 문제점이 존재한다. 첫째, SiGe의 격자 상수와 실리콘의 격자 상수가 다르기 때문에 실리콘 기판에 SiGe을 성장시킬 때 계면에서 두 층간에 스트레스가 발생되고, 이러한 스트레스는 격자의 왜곡을 일으켜 소자의 특성을 열화시킬 수 있다. 둘째, 이러한 두층간의 스트레스에 의하여 균일한 두께로 SiGe 에피층을 증착하는데 상당한 어려움이 있다. 이 때문에 일정 두께의 채널용 SiGe 에피층을 성장시키는 기술이 SiGe 에피 채널 형성 공정에 핵심 기술이 된다.However, there are various problems to be solved in the SiGe epilayer growth process. First, because the lattice constant of SiGe and the lattice constant of silicon are different, stress is generated between two layers at the interface when SiGe is grown on a silicon substrate, and such stress may cause lattice distortion to deteriorate device characteristics. Second, there is considerable difficulty in depositing a SiGe epi layer with a uniform thickness due to the stress between these two layers. For this reason, the technology of growing a SiGe epitaxial layer for a certain thickness becomes a key technology in the SiGe epitaxial channel formation process.
본 발명의 목적은 SiGe 에피층을 성장시킬 때 실리콘과의 계면에서 스트레스가 발생되지 않도록 함으로써 소자의 특성을 향상시킬 수 있는 반도체 소자의 에피 채널 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide an epi channel formation method of a semiconductor device capable of improving device characteristics by preventing stress from interfacing with silicon when growing an SiGe epi layer.
본 발명의 다른 목적은 균일한 두께로 SiGe 에피층을 성장시켜 소자의 특성을 향상시킬 수 있는 반도체 소자의 에피 채널 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming an epi channel of a semiconductor device capable of improving a device's characteristics by growing a SiGe epi layer with a uniform thickness.
본 발명에서는 실리콘 에피층을 형성한 후 Ge 이온 주입 공정 및 LTP 공정을 실시하여 SiGe 에피층을 형성함으로써 실리콘 기판과의 스트레스를 줄일 수 있고, 이에 따라 원하는 두께의 SiGe 에피층을 균일하게 형성할 수 있어 소자의 특성을 향상시킬 수 있다.In the present invention, after forming the silicon epilayer, the Ge ion implantation process and the LTP process may be performed to form a SiGe epilayer to reduce stress with the silicon substrate, thereby forming a SiGe epilayer having a desired thickness uniformly. Thereby, the characteristics of the device can be improved.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 에피 채널 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming an epi channel of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판12 : 패드 산화막11 semiconductor substrate 12 pad oxide film
13 : 패드 질화막14 : 열산화막13 pad nitride film 14 thermal oxide film
15 : 라이너 산화막16 : 절연막15 liner oxide film 16: insulating film
17 : 소자 분리막18 : 실리콘 에피층17 device isolation film 18 silicon epi layer
19 : SiGe 에피층19: SiGe epilayer
본 발명에 따른 반도체 소자의 에피 채널 형성 방법은 소자 분리막이 형성된 반도체 기판 상부의 소정 영역에 실리콘 에피층을 형성하는 단계와, 상기 실리콘 에피층에 Ge 이온 주입 공정을 실시한 후 LTP 공정을 실시하여 상기 실리콘 에피층을 SiGe 에피층으로 변형시키는 단계와, 상기 SiGe 에피층 상부에 게이트 산화막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.An epitaxial channel forming method of a semiconductor device according to the present invention includes forming a silicon epitaxial layer in a predetermined region on a semiconductor substrate on which a device isolation layer is formed, and performing an LTP process after performing a Ge ion implantation process on the silicon epitaxial layer. And converting the silicon epitaxial layer into a SiGe epitaxial layer, and forming a gate oxide layer on the SiGe epitaxial layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 에피 채널 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain an epi channel formation method of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 패드 산화막(12) 및 패드 질화막(13)을 순서적으로 형성한다. 액티브 영역과 필드 영역을 확정하는 마스크를 이용한 리소그라피 공정 및 식각 공정으로 패드 질화막(13) 및 패드 산화막(12)의 소정 영역을 식각하는 동시에 반도체 기판(11)을 소정 깊이로 식각하여 트렌치를 형성한다. 트렌치 측벽에 산화막(14)을 성장시켜 식각 공정에 의해 손상된 트렌치 측면 및 하부를 보상한 후 CVD 공정에 의해 전체 구조 상부에 라이너 산화막(15)을 형성한다. 트렌치가 매립되도록 전체 구조 상부에 절연막(16)을 형성한다.Referring to FIG. 1A, the pad oxide film 12 and the pad nitride film 13 are sequentially formed on the semiconductor substrate 11. The semiconductor substrate 11 is etched to a predetermined depth to form trenches by etching a predetermined area of the pad nitride film 13 and the pad oxide film 12 by a lithography process and an etching process using a mask for determining an active region and a field region. . After the oxide film 14 is grown on the trench sidewalls to compensate for the trench side and lower portions damaged by the etching process, the liner oxide film 15 is formed on the entire structure by the CVD process. An insulating film 16 is formed over the entire structure to fill the trench.
도 1(b)를 참조하면, CMP 공정으로 절연막(16)을 연마하여 패드 질화막(13)을 노출시킨다. 그리고, 계속적인 식각 공정에 의해 노출된 패드 질화막(13) 및 패드 산화막(12)을 제거하여 소자 분리막(17)을 형성한다. 반도체 기판(11) 상부에 스크린 산화막(도시안됨)을 형성한 후 에피 채널을 효과적으로 이용할 수 있게 SSR(Super Steep Retrograde) 이온 주입 공정을 실시한다. 세정 공정을 실시하여 스크린 산화막을 제거하고 H2베이크 공정을 실시한다. 그리고, 반도체 기판(11) 상부에 선택적 에피 성장 공정을 실시하여 에피 채널용 실리콘 에피층(18)을 성장시킨다. 실리콘 에피층(18)은 LPCVD 공정 또는 UHV CVD 공정을 이용하여 100∼500Å 정도의 두께로 성장시킨다. LPCVD 공정으로 실리콘 에피층(18)을 성장시키기 위해서는 HF, BOE 등의 산화물 식각 용액을 이용하여 전세정 공정을 실시한 후800∼1000℃의 온도에서 1∼5분간 수소 베이크 공정을 실시하고, 5Torr∼300Torr의 압력을 유지한 상태에서 SiH2Cl2가스와 HCl 가스를 각각 10∼500sccm 정도로 유입시켜 에피 실리콘층을 성장시킨다. 한편, UHV CVD 공정으로 실리콘 에피층(18)을 성장시키기 위해서는 400∼800℃의 온도와 1mTorr∼100Torr의 압력에서 성장시킨다.Referring to FIG. 1B, the insulating film 16 is polished by a CMP process to expose the pad nitride film 13. The pad nitride layer 13 and the pad oxide layer 12 exposed by the subsequent etching process are removed to form the device isolation layer 17. After forming a screen oxide film (not shown) on the semiconductor substrate 11, a super steep retrograde (SSR) ion implantation process is performed to effectively use an epi channel. The cleaning process is performed to remove the screen oxide film and the H 2 bake process is performed. The epitaxial silicon epitaxial layer 18 is grown by performing a selective epitaxial growth process on the semiconductor substrate 11. The silicon epi layer 18 is grown to a thickness of about 100 to 500 mW using an LPCVD process or a UHV CVD process. In order to grow the silicon epitaxial layer 18 by the LPCVD process, after performing a pre-cleaning step using an oxide etching solution such as HF, BOE, etc., a hydrogen bake process is performed at a temperature of 800 to 1000 ° C. for 1 to 5 minutes, and 5 Torr to While maintaining a pressure of 300 Torr, the epi silicon layer is grown by introducing SiH 2 Cl 2 gas and HCl gas about 10 to 500 sccm. On the other hand, in order to grow the silicon epitaxial layer 18 by the UHV CVD process, it grows at the temperature of 400-800 degreeC and the pressure of 1mTorr-100Torr.
도 1(c)를 참조하면, 실리콘 에피층(18)에 Ge 이온 주입 공정을 실시한 후 LTP(Laser Thermal Process) 공정을 실시하여 100∼500Å 정도의 두께로 SiGe 에피층(19)를 형성한다. 여기서, Ge 이온 주입 공정은 5∼50keV의 에너지와 1×1015∼2 ×1016atoms/㎠의 도우즈로 실시한다. 그리고, LTP 공정은 0.1∼2J/㎠의 에너지로 실시한다. 이후, SiGe 에피층(19) 상부에 게이트 산화막을 형성한다.Referring to FIG. 1C, after the Ge ion implantation process is performed on the silicon epitaxial layer 18, a laser thermal process (LTP) process is performed to form a SiGe epitaxial layer 19 having a thickness of about 100 to 500 kPa. Here, Ge ion implantation process is performed with the energy of 5-50 keV and the dose of 1 * 10 <15> -2 * 10 <16> atoms / cm <2>. The LTP step is performed at an energy of 0.1 to 2 J / cm 2. Thereafter, a gate oxide film is formed on the SiGe epi layer 19.
본 발명의 다른 실시 예로서, 실리콘 에피층을 형성한 후 Ge 이온 주입 공정 및 LTP 공정을 실시하여 1차 SiGe 에피층을 형성하고, 실리콘 에피층을 다시 형성하여 SiGe과 실리콘의 이중 구조의 에피 채널을 형성한다.As another embodiment of the present invention, after forming a silicon epi layer, a Ge ion implantation process and an LTP process are performed to form a primary SiGe epi layer, and the silicon epi layer is formed again to form an epi channel having a dual structure of SiGe and silicon. To form.
상술한 바와 같이 본 발명에 의하면 실리콘 에피층을 형성한 후 Ge 이온 주입 공정 및 LTP 공정을 실시하여 SiGe 에피층을 형성함으로써 실리콘 기판과의 스트레스를 줄일 수 있고, 이에 따라 원하는 두께의 SiGe 에피층을 균일하게 형성할 수 있어 소자의 특성을 향상시킬 수 있다.As described above, according to the present invention, a silicon epitaxial layer is formed and then a Ge ion implantation process and an LTP process are performed to form a SiGe epilayer, thereby reducing stress with a silicon substrate, thereby forming a SiGe epilayer having a desired thickness. Since it can form uniformly, the characteristic of an element can be improved.
Claims (9)
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| KR1020000079264A KR20020049938A (en) | 2000-12-20 | 2000-12-20 | Method of forming an epi channel in a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6730568B2 (en) | 2002-09-17 | 2004-05-04 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by boron-fluoride compound doping |
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2000
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6730568B2 (en) | 2002-09-17 | 2004-05-04 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by boron-fluoride compound doping |
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