KR100650861B1 - Method of manufacturing a flash memory device - Google Patents

Method of manufacturing a flash memory device Download PDF

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KR100650861B1
KR100650861B1 KR1020050114708A KR20050114708A KR100650861B1 KR 100650861 B1 KR100650861 B1 KR 100650861B1 KR 1020050114708 A KR1020050114708 A KR 1020050114708A KR 20050114708 A KR20050114708 A KR 20050114708A KR 100650861 B1 KR100650861 B1 KR 100650861B1
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method
flash memory
manufacturing
memory device
dielectric film
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KR1020050114708A
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Korean (ko)
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전광석
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers

Abstract

A method for manufacturing a flash memory device is provided to prevent the thinning and thickening both ends of a tunnel oxide layer by forming an isolation layer composed of a low-permittivity dielectric film and a spacer. A low-permittivity dielectric film is formed on a substrate(100). By patterning the dielectric film, a dielectric pattern is formed to expose the substrate. A spacer(106) is formed at both sidewalls of the low-permittivity dielectric pattern, thereby forming an isolation layer(102a) including the spacer and the dielectric pattern. An epitaxial layer(108) is selectively grown on the exposed substrate, thereby forming an active region.

Description

플래쉬 메모리 소자의 제조방법{Method of manufacturing a flash memory device} Method of manufacturing flash memory devices {Method of manufacturing a flash memory device}

도 1a 내지 도 1d는 본 발명에 따른 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 단면도이다. Figure 1a to 1d is a sectional view for explaining the manufacturing method of the flash memory device according to the present invention.

<도면의 주요부분에 대한 부호의 설명> <Description of the Related Art>

100 : 반도체 기판 102 : 저유전막 100: semiconductor substrate 102: low dielectric

102a : 저유전막 패턴 104 : 포토레지스트 패턴 102a: low dielectric film pattern 104: photoresist pattern

106 : 스페이서 108 : 에피택셜층 106: spacer 108: epitaxial layer

110 : 터널 산화막 112 : 폴리실리콘막 110: tunnel oxide film 112: polysilicon film

본 발명은 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히, 저유전 (Low-k) 물질의 매립한도에 대한 기술적 한계를 극복하고, 공정 단계를 단순화시킬 수 있는 플래쉬 메모리 소자의 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a flash memory device which can overcome the technical limitations and to simplify the process steps of the present invention relates to method of manufacturing a flash memory device, in particular, low-k (Low-k) embedded limit of the material .

플래쉬 메모리 소자에서 사용되는 트렌치 소자 분리막은 듀얼 트렌치 구조를 갖는다. A trench isolation film that is used in the flash memory device has a dual trench structure. 고전압이 인가되는 주변 영역에는 깊은 소자 분리막이 필요하기 때문에 소자 분리용 트렌치를 깊게 형성하고, 패턴 CD(Critical Dimension)가 작은 셀 영역에는 저유전 물질의 매립한도 때문에 상대적으로 소자 분리용 트렌치를 얕게 형성해야 한다. Because it requires a deep isolation film, the peripheral area being applied with a high voltage are formed deep for a device isolation trench pattern CD (Critical Dimension) is shallow, the for relative device isolation in the trench because of the buried limit of the low dielectric material small cell region forming Should be. 이에 대한 소자 분리막 형성방법에 대해 자세히 설명하면 다음과 같다. A detailed description for the isolation film forming method for this as follows.

반도체 기판상에 패드 산화막, 패드 질화막 및 포토레지스트 패턴을 형성한 후 포토레지스트 패턴을 마스크로 패드 질화막, 패드 산화막 및 반도체 기판의 일부를 식각하여 주변 영역에 폭이 넓은 제1 트렌치를 형성한다. And then on a semiconductor substrate to form a pad oxide, pad nitride and a photoresist pattern, a photoresist pattern etching a portion of the pad nitride layer, the pad oxide film and the semiconductor substrate as a mask to form the first trench is wider width in the peripheral region. 포토레지스트 패턴을 제거한 후 셀 영역의 패드 질화막, 패드 산화막 및 반도체 기판의 일부를 식각하여 제2 트렌치를 형성하는 동시에 주변 영역의 제1 트렌치를 더 깊게 식각하여 제1 트렌치가 제2 트렌치보다 더 깊은 깊이를 갖게 한다. After removing the photo-resist pattern at the same time by etching a portion of the pad nitride layer, the pad oxide film and the semiconductor substrate of the cell region to form a second trench and deeper etching the first trench in the area around the first trench is deeper than the second trench it has depth. 제1 및 제2 트렌치 내에 저유전막을 매립하여 소자 분리막을 형성한다. The buried a low dielectric film in the first and second trenches to form a device isolation film.

그러나, 상기와 같은 소자 분리막 구조는 제1 및 제2 트렌치 내에 매립되는 저유전막의 매립한도에 대한 제한을 받기 때문에 원하는 깊이로 소자 분리용 트렌치를 형성할 수 없다. However, elements such as the membrane structure first and it is not possible to form the device isolation trenches for the desired depth because of receiving a limit on the extent of the buried low dielectric film to be buried in the second trench. 이로 인해 설계 및 플래쉬 메모리 소자 상에서 전기적인 한계를 가져온다. This results in a limitation on the electrical design and the flash memory device.

상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 저유전막의 매립한 도에 대한 기술적 한계를 극복하여 공정을 단순화시키고, 소자 분리용 트렌치 매립시 매립 불량으로 인한 수율 저하를 막을 수 있는 플래쉬 메모리 소자의 제조방법을 제공하는 데 있다. In order to solve the above problems an object of the conceived invention is simplifying the process to overcome the technical limitations on the embedding degree of the low dielectric films and a flash memory that can plug the yield decreases due to the defective filling when the device isolation trench filled for there is provided a method of manufacturing the device.

본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조방법은, 반도체 기판상에 저유전막을 형성한 후 상기 저유전막의 소정 영역을 식각하여 상기 반도체 기판을 노출시키는 단계와, 상기 노출된 반도체 기판상에 에피택셜층을 선택적으로 성장시켜 액티브 영역을 형성하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법을 제공한다. Method of manufacturing a flash memory device according to an embodiment of the invention, and exposing the semiconductor substrate by etching predetermined regions of the low dielectric film after the formation of the low dielectric film on a semiconductor substrate, on said exposed semiconductor substrate selectively growing the epitaxial layer provides a process for the preparation of a flash memory device including the step of forming the active region.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다. Described in detail below, embodiments of the invention with reference to the accompanying drawings as follows.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조방법을 설명하기 위한 단면도이다. Figure 1a to 1d are cross-sectional views for explaining the manufacturing method of the flash memory device according to an embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(100) 상에 저유전막(102)을 형성한다. Referring to Figure 1a, thereby forming a low dielectric film 102 on a semiconductor substrate 100. 이때, 저유전막(102)은 HDP 산화막 또는 SOG(Spin On Glass)막을 1000Å 내지 7000Å의 두께로 증착하여 형성한다. At this time, the low dielectric film 102 is formed by depositing HDP oxide or SOG (Spin On Glass) film with a thickness of 1000Å to 7000Å. 저유전막(102) 상에 포토레지스트 패턴(104)을 형성한다. On the low dielectric film 102 to form a photoresist pattern 104.

도 1b를 참조하면, 포토레지스트 패턴(104)을 마스크로 반도체 기판(100)이 노출되도록 저유전막(102)을 식각하여 저유전막 패턴(102a)을 형성한다. Etching the low dielectric film 102 to form a low dielectric film pattern (102a) so that Referring to Figure 1b, a photoresist pattern 104, the semiconductor substrate 100 is exposed with a mask. 전체 구조 상부에 절연막을 형성한다. An insulating film is formed on the entire upper structure. 이때, 절연막은 질화막 또는 CVD 산화막을 50Å 내지 1000Å의 두께로 증착하여 형성한다. At this time, the insulating film is formed by depositing a nitride film or a CVD oxide film to a thickness of 50Å to about 1000Å. 절연막을 에치백(etchback)하여 저유전막 패턴(102a) 측벽에 스페이서(106)를 형성한다. The etch-back (etchback) on the insulating film to form a spacer 106 on the sidewalls low dielectric film pattern (102a). 이때, 스페이서(106)는 저유전막(102) 식각시 불순물이 발생하는데, 이 불순물에 의해 발생하는 아웃개싱(outgasing) 또는 트랩 차지(trap charge)를 방지하기 위해 형성하는 것이다. At this time, the spacer 106 to the impurity during the low dielectric film 102, the etching occurs, will be formed in order to prevent outgassing (outgasing) or charge traps (trap charge) generated by the impurities. 만약, 식각시 불순물이 발생하지 않는 저유전막(102)을 사용한다면 저유전막 패턴(102a) 측벽에 스페이서(106)를 형성하지 않아도 된다. If you are using the low dielectric film 102 is etched during the impurity does not occur is not necessary to form the low dielectric film pattern (102a), the spacer 106 to the side wall.

제1 및 제2 전처리 공정과 베이크(bake) 공정을 실시하는데 먼저, 제1 전처리 공정을 실시하여 반도체 기판 내의 유기물을 제거한다. The embodiment of first and second pre-processing step and the baking (bake) for carrying out the first step, the first pre-processing step to remove the organic material in the semiconductor substrate. 이때, 제1 전처리 공정으로는 황산 및 과산화수소수를 포함하는 혼합 용액을 이용한 습식 식각 또는 건식 식각을 이용한다. At this time, the first pre-processing step as is used in the wet etching process or dry etching using a mixed solution containing a number of sulfuric acid and hydrogen peroxide. 이어, 제2 전처리 공정을 실시하여 저유전막(102) 식각시 손상된 영역과 접합부의 자연 산화막을 제거한다. Next, second to conduct the pre-processing step to remove the native oxide film of a low dielectric film 102, the damaged region and the junction during etching. 이때, 제2 전처리 공정은 과산화수소, NF 4 또는 BOE 용액에 불산(HF)을 첨가한 혼합 용액을 이용하여 습식 식각을 실시하거나, 불산(HF) 및 순수(DI) 워터를 혼합한 혼합 용액을 이용하여 건식 식각을 실시한다. At this time, the second pre-processing step is a step of hydrogen peroxide, NF 4 or by using the mixed solution was added to hydrofluoric acid (HF) to the BOE solution is subjected to wet etching, or using a hydrofluoric acid (HF) and pure water (DI) mixing a mixed solution of water It will be subjected to dry etching. 이후, H 2 베이크 또는 진공(vacuum) 베이크 공정을 실시한다. Then, the H 2 bake is performed, or a vacuum (vacuum) baking process. 이때, 베이크 공정은 1Torr 내지 수백 Torr의 압력으로 챔버 내에서 또는 인시튜(in-situ)로 실시한다. At this time, the baking process is carried out in the chamber at a pressure of 1Torr to several hundred Torr or in-situ (in-situ).

도 1c를 참조하면, 노출된 반도체 기판(100) 상에 활성영역으로 사용되는 에 피택셜층(Epitaxial; 108)을 선택적으로 성장시킨다. Referring to Figure 1c, pitaek layer to be used as an active region on the exposed semiconductor substrate 100; thereby selectively growing the (Epitaxial 108). 이때, 에피택셜층(108)은 LP-CVD(Low Pressure-Chemical Vapor Deposition) 방식 또는 UHV(Ultra High Vacuum)-CVD 방식을 이용하여 600℃ 내지 1200℃의 온도에서 400Å 내지 9000Å의 두께로 성장시킨다. At this time, the epitaxial layer 108 is grown by LP-CVD (Low Pressure-Chemical Vapor Deposition) scheme or a UHV (Ultra High Vacuum) -CVD thickness of 400Å to 9000Å using a method at a temperature of 600 ℃ to 1200 ℃ . 여기서, 에피텍셜층(108) 성장시 DCS, HCl, H 2 , Si 2 H 6 , Cl 2 및 GeH 4 에 첨가 가스인 B 2 H 4 , PH 3 및 AsH 3 를 혼합한 혼합 가스를 사용하는데, 첨가 가스를 사용하는 이유는 반도체 기판(100)을 n형 또는 p형으로 형성하기 위해서이다. Here, in using the epitaxial layer 108 is grown upon a mixed gas by mixing the DCS, HCl, H 2, Si 2 H 6, a B 2 H additive gas to the Cl 2 and GeH 4 4, PH 3 and AsH 3, the reason for using the added gas is to form a semiconductor substrate 100 of n-type or p-type.

에피택셜층(108)을 형성함으로써 저유전막 패턴(102a) 및 스페이서(106)로 구성된 소자 분리막에 의해 분리되는 액티브 영역이 형성된다. The active region is formed which is separated by an isolation film consisting of a low dielectric film pattern (102a) and the spacer (106) by forming an epitaxial layer (108).

도 1d를 참조하면, 전체 구조상에 터널 산화막(110) 및 플로팅 게이트용 폴리실리콘막(112)을 형성한다. Referring to Figure 1d, and the whole structure forming a tunnel oxide film 110 and polysilicon film 112 for floating gate.

이상으로 본 발명에 따른 플래쉬 메모리 소자의 제조를 완료한다. Thus completing the manufacture of the flash memory cell according to the invention as above.

반도체 기판(100)이 노출되도록 저유전막(102)의 소정 영역을 식각하여 저유전막 패턴(102a)을 형성한 후 저유전막 패턴(102a) 측벽에 스페이서(106)를 형성하여 저유전막 패턴(102a)과 스페이서(106)로 구성된 소자 분리막을 형성하고, 노출된 반도체 기판(100) 상에 에피택셜층(108)을 성장시킴으로써 소자 분리막에 의해 분리되는 액티브 영역이 형성된다. To form a semiconductor substrate 100 is a by etching predetermined regions of the low dielectric film 102 so as to be exposed to form a low dielectric film pattern (102a) after the spacer 106 on the sidewalls low dielectric film pattern (102a), the low dielectric film pattern (102a) and forming a device isolation film consisting of a spacer 106, an active region isolated by the device isolation film is formed by growing an epitaxial layer (108) on the exposed semiconductor substrate 100. 이로 인하여 저유전막의 매립한도에 대한 기술적 한계를 극복할 수 있고, 터널 산화막(110) 형성시 터널 산화막(110) 양끝(A)이 얇아지거나 두꺼워지는 것을 방지할 수 있으며, 전체적으로 공정이 단순화된다. Due to this it is possible to overcome the technical limitations of the embedded limit of the low dielectric film, to prevent the tunnel oxide film 110, forming the tunnel oxide film 110 at both ends (A) is to be thinner or thicker, and simplifies the whole process.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. Although the teachings of the present invention is specifically described in accordance with the preferred embodiment, the above-described embodiment is for a description thereof, it should be noted that not for the limitation. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. In addition, one of ordinary experts in the art will appreciate the various embodiments are possible examples within the scope of the technical idea of ​​the present invention.

상술한 바와 같이 본 발명에 의하면, 반도체 기판상의 소정 영역에 저유전막 패턴을 형성한 후 저유전막 패턴 측벽에 스페이서를 형성하여 저유전막 패턴과 스페이서로 구성된 소자 분리막을 형성하고, 노출된 반도체 기판상에 에피택셜층을 선택적으로 성장시킴으로써, 소자 분리막에 의해 분리되는 액티브 영역이 형성된다. According to the present invention, as described above, after forming the low dielectric film pattern at a predetermined region on the semiconductor substrate to form a spacer on the low dielectric film pattern side wall to form a device isolation film consisting of a low dielectric film pattern and the spacer, on the exposed semiconductor substrate by selectively growing an epitaxial layer, an active region is formed which is separated by a device isolation film. 이로 인해, 저유전막의 매립한도에 대한 제한이 없어져 매립한도 때문에 소자 분리막으로 사용하지 못했던 저유전 물질들을 효과적으로 사용할 수 있다. As a result, since the limited extent eliminated landfill for landfill lower limit of the dielectric can be a low-k dielectric material did not use the device isolation effectively. 또한, 트렌치를 매립하는 공정 단계를 줄일 수 있고, 매립 불량으로 인한 수율 저하를 막을 수 있다. Further, it is possible to reduce the process steps for filling the trenches, it becomes possible to prevent the yield decreases due to the defective filling.

또한, 터널 산화막 형성시 터널 산화막 양끝부분이 얇아지거나 두꺼워지는 현상을 방지함으로써 이를 방지하기 위한 공정이 필요치 않아 공정 단계가 단순화 될 수 있다. Also, a process to avoid this can be a simple process step not required by preventing a phenomenon that the tunnel oxide film formed during the thin tunnel oxide layer or both ends of thicker.

Claims (9)

  1. 반도체 기판상에 저유전막을 형성한 후 상기 저유전막의 소정 영역을 식각하여 상기 반도체 기판을 노출시키는 단계; After the formation of the low dielectric film on a semiconductor substrate exposing the semiconductor substrate by etching predetermined regions of the low dielectric film; And
    상기 노출된 반도체 기판상에 에피택셜층을 선택적으로 성장시켜 액티브 영역을 형성하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법. The method of the flash memory device by selectively growing an epitaxial layer on the exposed semiconductor substrate including forming an active region.
  2. 제1항에 있어서, 상기 저유전막은 1000Å 내지 7000Å의 두께로 형성하는 플래쉬 메모리 소자의 제조방법. The method of claim 1, wherein the method for manufacturing a flash memory device formed with a thickness of the low dielectric film is 1000Å to 7000Å.
  3. 제1항에 있어서, 상기 식각된 저유전막 측벽에 스페이서를 형성하는 반도체 소자의 제조방법. 2. The method of claim 1, for manufacturing a semiconductor device forming a spacer on a side wall of the low-k dielectric etch.
  4. 제1항에 있어서, 상기 저유전막을 식각한 후 제1 및 제2 전처리 공정과 베이크 공정을 실시하는 단계를 더 포함하는 플래쉬 메모리 소자의 제조방법. The method of claim 1, wherein the method for manufacturing a flash memory device further comprising: after etching the low dielectric film subjected to the first and second pre-processing step and the baking step.
  5. 제4항에 있어서, 상기 제1 전처리 공정은 황산 및 과산화수소수를 포함하는 혼합 용액을 이용하여 습식 식각 또는 건식 식각 공정을 실시하여 유기물을 제거하는 플래쉬 메모리 소자의 제조방법. The method of claim 4, wherein the first pre-processing step is a method of manufacturing a flash memory device to remove the organic matter by carrying out a wet etching or a dry etching process using a mixed solution containing a number of sulfuric acid and hydrogen peroxide.
  6. 제4항에 있어서, 상기 제2 전처리 공정은 과산화수소, NF 4 또는 BOE 용액에 불산을 첨가한 혼합 용액을 이용하여 습식 식각을 실시하거나 불산 및 순수 워터를 혼합한 혼합 용액을 이용한 건식 식각을 실시하여 자연 산화막을 제거하는 플래쉬 메모리 소자의 제조방법. The method of claim 4, wherein the second pre-processing step is a step of hydrogen peroxide, NF 4 or by using the mixed solution by the addition of hydrofluoric acid to the BOE solution is subjected to dry etching using the mixture solution was carried out, or mixture of hydrofluoric acid and pure water to wet etching the method of the flash memory device to remove the native oxide film.
  7. 제4항에 있어서, 상기 베이크는 H 2 또는 진공에서 1Torr 내지 수백 Torr의 압력으로 실시하는 플래쉬 메모리 소자의 제조방법. The method of claim 4, wherein the baking is a method of manufacturing a flash memory device for performing a pressure of 1Torr to several hundred Torr in H 2 or a vacuum.
  8. 제1항에 있어서, 상기 에피택셜층은 LP-CVD 방식 또는 UHV-CVD 방식을 이용하여 600℃ 내지 1200℃의 온도에서 400Å 내지 9000Å의 두께로 성장시키는 플래쉬 메모리 소자의 제조방법. The method of manufacturing a flash memory device which the epitaxial layer is grown by LP-CVD method or a UHV-CVD method of 400Å to about 9000Å at a temperature of 600 ℃ to 1200 ℃ thickness using in claim 1.
  9. 제1항에 있어서, 상기 에피텍셜층 성장시 DCS, HCl, H 2 , Si 2 H 6 , Cl 2 및 GeH 4 에 첨가 가스인 B 2 H 4 , PH 3 및 AsH 3 를 혼합한 혼합 가스를 사용하는 플래쉬 메모리 소자의 제조방법. The method of claim 1, wherein the epitaxial layer growth when DCS, HCl, H 2, Si 2 H 6, a B 2 H additive gas to the Cl 2 and GeH 4 4, a mixed gas by mixing the PH 3 and AsH 3 method for manufacturing a flash memory device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851327B2 (en) 2007-12-18 2010-12-14 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device including forming a single-crystalline semiconductor material in a first area and forming a second device isolation pattern on a second area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851327B2 (en) 2007-12-18 2010-12-14 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device including forming a single-crystalline semiconductor material in a first area and forming a second device isolation pattern on a second area
US8350336B2 (en) 2007-12-18 2013-01-08 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same

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