KR20020049125A - Device for protecting a semiconductor device from an ESD - Google Patents

Device for protecting a semiconductor device from an ESD Download PDF

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Publication number
KR20020049125A
KR20020049125A KR1020000078219A KR20000078219A KR20020049125A KR 20020049125 A KR20020049125 A KR 20020049125A KR 1020000078219 A KR1020000078219 A KR 1020000078219A KR 20000078219 A KR20000078219 A KR 20000078219A KR 20020049125 A KR20020049125 A KR 20020049125A
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KR
South Korea
Prior art keywords
gate
drain
contacts
source
protection device
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Application number
KR1020000078219A
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Korean (ko)
Inventor
최낙헌
전찬희
Original Assignee
박종섭
주식회사 하이닉스반도체
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Priority to KR1020000078219A priority Critical patent/KR20020049125A/en
Publication of KR20020049125A publication Critical patent/KR20020049125A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: An electrostatic discharge protection device is provided to prevent thermal damage, by dispersing the quantity of current in every path formed under the gate of the electrostatic discharge protection device such that the current flows from the drain of the electrostatic discharge protection device to the source. CONSTITUTION: The gate(24), the drain(22) and the source(20) are formed in the electrostatic discharge protection device. A plurality of contacts(26) are formed on the gate and a drain region. The section areas of the contacts formed in the drain region are different depending upon the position of the contacts. The section area of the contacts formed in the drain region becomes large as it goes far away from the gate.

Description

반도체 디바이스의 정전기 보호 소자{Device for protecting a semiconductor device from an ESD}Device for protecting a semiconductor device from an ESD

본 발명은 반도체 디바이스의 정전기 보호 소자에 관한 것으로서, 보다 상세하게는 정전기(EDS) 펄스가 인가되는 드레인 쪽 컨택의 형상을 변화시켜서 과다한 전류에도 손상되지 않고 능동적으로 동작되도록 개선한 반도체 디바이스의 정전기 보호 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection element of a semiconductor device. More particularly, the electrostatic protection of a semiconductor device is improved by changing the shape of a drain-side contact to which an electrostatic discharge (EDS) pulse is applied so as to be actively operated without being damaged by excessive current. It relates to an element.

통상, 반도체 디바이스는 정전기에 대한 대책을 갖도록 설계되며, 일 예로써 정전기 보호 소자가 구성된다.Typically, semiconductor devices are designed to have a countermeasure against static electricity, for example, an electrostatic protection element is constructed.

정전기 보호 소자는 정전기 펄스가 드레인에 인가되면 많은 양의 전류를 소스로 흘려서 인접한 다른 소자들이 정전기 펄스에 의하여 영향을 받는 것을 차단하여 다른 소자들을 보호하는 기능을 수행한다.When the electrostatic pulse is applied to the drain, the electrostatic protection element flows a large amount of current to the source, thereby protecting other elements from being affected by the electrostatic pulse.

이를 위하여 정전기 보호 소자는 도 1 및 도 2와 같이 소스(10), 드레인(12) 및 게이트(14)가 구성되고, 소스(10)와 드레인(12)에는 컨택(16)이 형성된다.To this end, as shown in FIGS. 1 and 2, the electrostatic protection device includes a source 10, a drain 12, and a gate 14, and contacts 16 are formed on the source 10 and the drain 12.

여기에서 컨택(16)은 소스(10) 영역과 드레인(12) 영역에 많은 수로 형성되면서 일정한 형태로 배열되며 각각 같은 용적을 갖도록 설계된다.Here, the contacts 16 are formed in a large number in the source 10 region and the drain 12 region, are arranged in a constant shape, and are designed to have the same volume, respectively.

드레인(12) 영역의 컨택(16)으로 정전기 펄스(EDS pulse)가 인가되며, 이 정전기 펄스는 드레인(12)에서 소스(10) 쪽으로 이동하여 소모된다.An electrostatic pulse (EDS pulse) is applied to the contact 16 in the drain 12 region, and the electrostatic pulse travels from the drain 12 toward the source 10 and is consumed.

그러나, 종래의 정전기 보호 소자는 경로 A와 경로 B를 대비할 때 경로 A에서 과도한 전류 편중 현상이 발생되며, 그에 따라서 발열이 생겨서 높은 전압의 정전기 펄스가 인가될 때 열적 파괴 현상이 발생되어서 정전기 보호 소자가 손상된다.However, in the conventional electrostatic protection device, excessive current bias occurs in the path A when the path A and the path B are compared, and thus heat generation occurs and thermal breakdown occurs when a high voltage electrostatic pulse is applied. Is damaged.

이러한 문제점을 해결하기 위해서 정전기 보호 소자의 크기를 충분히 크게 설계하여야 하지만, 고집적회 추세에 따라서 정전기 보호 소자에 할애되는 면적이 최소화 최적화됨에 따라서 제한이 따르는 문제점이 있었다.In order to solve this problem, the size of the static electricity protection device should be designed to be large enough, but according to the high integration trend, there is a problem in that the area devoted to the static electricity protection device is minimized and optimized.

결국, 상술한 종래의 정전기 보호 소자는 그 구조적 문제점으로 인하여 과도한 정전기 펄스에 대한 손상이 발생되는 문제점이 있다.As a result, the above-described conventional electrostatic protection device has a problem that damage to excessive electrostatic pulse is generated due to its structural problems.

본 발명의 목적은 정전기 보호 소자의 컨택 구조를 개선시켜서 과도한 정전기 펄스가 인가되어도 드레인에서 소스에 이르는 경로 별로 전류가 집중되는 현상을 완화시켜서 정전기 보호 소자에 열적 손상이 발생되는 것을 방지함에 있다.An object of the present invention is to improve the contact structure of the electrostatic protection device to mitigate the phenomenon that the current is concentrated in the path from the drain to the source even if excessive electrostatic pulse is applied to prevent thermal damage to the electrostatic protection device.

도 1은 종래의 반도체 디바이스의 정전기 보호 소자의 레이 아웃도1 is a layout view of an electrostatic protection element of a conventional semiconductor device

도 2는 도 1의 정전기 보호 소자의 단면도2 is a cross-sectional view of the electrostatic protection device of FIG.

도 3은 본 발명에 따른 반도체 디바이스의 정전기 보호 소자의 실시예를 나타내는 레이아웃도3 is a layout showing an embodiment of the electrostatic protection element of the semiconductor device according to the present invention;

본 발명에 따른 반도체 디바이스의 정전기 보호 소자는 게이트와 드레인 및 소스가 형성되며, 상기 게이트와 드레인 영역의 상부에 다수의 컨택들이 형성되고, 상기 드레인 영역에 형성되는 컨택들은 위치에 따라서 단면적이 다르게 구성된다.In the electrostatic protection device of the semiconductor device according to the present invention, a gate, a drain, and a source are formed, and a plurality of contacts are formed on the gate and the drain region, and the contacts formed in the drain region have different cross-sectional areas according to positions. do.

여기에서 드레인 영역에 형성되는 컨택들은 게이트에 멀어질수록 단면적이 점점 크게 형성됨이 바람직하다.Here, it is preferable that the contacts formed in the drain region have a larger cross-sectional area as the distance from the gate increases.

이하, 본 발명에 따른 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 반도체 디바이스의 정전기 보호 소자는 드레인에서 소스에 이르는 전류 흐름 경로 별로 전류가 분할되어 흐를수 있도록 컨택의 구조가 개선된다.In the electrostatic protection device of the semiconductor device according to the present invention, the structure of the contact is improved so that the current is divided and flows for each current flow path from the drain to the source.

도 3을 참조하면, 정전기 보호 소자는 소스(20)와 드레인(22) 및 게이트(24)로 이루어지며, 소스(20)와 드레인(22)의 상부에 다수의 컨택(26)이 형성되고, 컨택(26)들은 해당 영역에서 일정한 매트릭스 형태로 배열된다.Referring to FIG. 3, the electrostatic protection element includes a source 20, a drain 22, and a gate 24, and a plurality of contacts 26 are formed on the source 20 and the drain 22. The contacts 26 are arranged in a constant matrix form in the area.

이 중 소스(20) 영역에 형성되는 컨택(26)은 단면적이 동일하게 형성되어서 매트릭스 형상으로 배열된다. 이와 다르게, 드레인(22) 영역에 형성되는 컨택(26)은 게이트(24)에 가까운 열의 단면적이 최소가 되고 게이트(24)에 멀어질수록 해당 열의 단면적이 점점 증가되어서 게이트(24)에 가장 먼 열의 단면적이 최대가 되도록 구성된다.The contacts 26 formed in the region of the source 20 have the same cross-sectional area and are arranged in a matrix. Alternatively, the contact 26 formed in the drain 22 region has the smallest cross-sectional area of the column close to the gate 24 and as the distance from the gate 24 increases, the cross-sectional area of the column gradually increases to the furthest from the gate 24. The cross-sectional area of the column is configured to be maximum.

상술한 바와 같이 구성됨으로써 드레인에서 소스로 전류가 흐르는 경로별로전류가 분산되어서 과도한 정전기 펄스가 인가될 때 열적 손상의 발생이 억제될 수 있다.By configuring as described above, the current is distributed for each path through which the current flows from the drain to the source so that occurrence of thermal damage can be suppressed when an excessive electrostatic pulse is applied.

구체적으로, 게이트(24)에 가까운 컨택(26)으로는 정전기 펄스에 의한 전류가 소량 유입되고, 게이트(24)에 먼 컨택(26)으로는 정전기 펄스에 의한 전류가 다량 유입된다.Specifically, a small amount of electric current flows into the contact 26 near the gate 24, and a large amount of current flows into the contact 26 far from the gate 24.

그리고, 게이트(24)에 가까운 컨택(26)으로 유입된 전류는 도 2의 경로 A를 통하여 소스(10)로 흐르게되며, 게이트(24)에 먼 컨택(26)으로 유입된 전류는 도 2의 경로 B를 통하여 소스(10)로 흐르게된다. 결국 컨택(26)의 단면적 차이는 전류의 흐르는 양을 경로에 따라 조절하는 역할을 한다.The current flowing into the contact 26 close to the gate 24 flows to the source 10 through the path A of FIG. 2, and the current flowing into the contact 26 far from the gate 24 is shown in FIG. 2. Flow through path B to source 10. As a result, the cross-sectional area difference of the contact 26 serves to adjust the amount of current flowing along the path.

결국, 전류가 분산되어서 드레인(12)에서 소스(10)로 흐르므로 과도한 정전기 펄스가 인가되어도 그에 따른 열적 손상이 방지된다.As a result, current is distributed and flows from the drain 12 to the source 10, so that even if excessive electrostatic pulses are applied, thermal damage thereof is prevented.

따라서, 본 발명에 의하면 정전기 펄스에 의하여 정전기 보호 소자의 드레인에서 소스로 흐르는 전류의 양이 게이트 하부에 형성되는 경로 별로 분산되므로 열적 손상이 발생되는 것이 방지되는 효과가 있다.Therefore, according to the present invention, since the amount of current flowing from the drain of the electrostatic protection element to the source by the electrostatic pulse is distributed for each path formed under the gate, thermal damage is prevented from occurring.

Claims (2)

게이트와 드레인 및 소스가 형성되며,Gates and drains and sources are formed, 상기 게이트와 드레인 영역의 상부에 다수의 컨택들이 형성되고,A plurality of contacts are formed on the gate and drain region, 상기 드레인 영역에 형성되는 컨택들은 위치에 따라서 단면적이 다르게 구성됨을 특징으로 하는 정전기 보호 소자.The contacts formed in the drain region have a different cross-sectional area depending on the position of the electrostatic protection element. 제 1 항에 있어서,The method of claim 1, 상기 드레인 영역에 형성되는 컨택들은 게이트에 멀어질수록 상기 단면적이 점점 크게 형성됨을 특징으로 하는 정전기 보호 소자.And the contacts formed in the drain region become larger in cross-sectional area as they move away from the gate.
KR1020000078219A 2000-12-19 2000-12-19 Device for protecting a semiconductor device from an ESD KR20020049125A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8928033B2 (en) 2010-11-15 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor device
US9318502B2 (en) 2014-09-15 2016-04-19 Samsung Electronics Co., Ltd. Nonvolatile memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8928033B2 (en) 2010-11-15 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor device
US9362220B2 (en) 2010-11-15 2016-06-07 Samsung Electronics Co., Ltd. Semiconductor device
US9318502B2 (en) 2014-09-15 2016-04-19 Samsung Electronics Co., Ltd. Nonvolatile memory device

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