KR20020041585A - Word line driving circuit - Google Patents

Abstract

PURPOSE: A word line driving circuit is provided to prevent time loss, reduces the number of transistors and a layout area, and quickly activates a word line. CONSTITUTION: A word line driving circuit includes a first conductive transistor(Q1) and a second conductive transistor(Q2). A gate of the first conductive transistor(Q1) is connected to a power-supply voltage, a source is connected to a ground terminal, a drain is connected to a sub-word line. The drain of the first conductive transistor(Q1) is connected to a drain of the second conductive transistor(Q2). A gate of the second conductive transistor(Q2) is connected to an output signal of the main word line driver, a source of the second conductive transistor(Q2) is connected to an output signal of the sub-word line driver.

Description

Word line driving circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to word line driver circuits suitable for highly integrated memory devices.

In general, a word line driving circuit in a semiconductor memory device decodes a row address and a column address connected to a memory cell to drive or deactivate a word line connected to the memory cell.

The spacing of word line wiring becomes tighter as the size of the memory cell decreases, and a semiconductor memory device having a hierarchical word line structure is used to improve such a phenomenon.

Since the hierarchical word line driver circuit has a structure in which a plurality of sub word line drivers are connected to each main word line driver, the spacing between word lines can be reduced.

Hereinafter, a conventional word line driver circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a conventional self boosted word line driving circuit, and FIG. 2 is a circuit diagram illustrating a conventional pseudo static word line driving circuit.

The conventional self boosting word line driving circuit is composed of three NMOS transistors Q1, Q2, and Q3, as shown in FIG.

That is, the output signal MWLB of the main word line driver (MWD) (not shown) is applied to the gate, the source is connected to the ground terminal GND, and the drain is connected to the word line SWL. A second NMOS transistor Q2 connected to a first NMOS transistor Q1, a source connected to an opposite phase MWL of the MWLB, a boosted power supply Vpp inside the chip, and having a drain as an output terminal; A gate is connected to the drain of the second NMOS transistor Q2, a source is connected to the drain of the first NMOS transistor Q1, and an output signal of a sub word line decoder (not shown) (Sub Word LineDecoder; SWD) The third NMOS transistor Q3 has a drain connected to the FX.

The boosted power supply Vpp is a potential equal to or greater than the minimum cell data voltage + cell threshold voltage Vt, and the drain of the first NMOS transistor Q1 and the source of the third NMOS transistor Q3 become a common output terminal.

The conventional virtual stack type word line driving circuit is composed of two NMOS transistors Q1 and Q2 and one PMOS transistor Q3 as shown in FIG.

That is, the first NMOS transistor Q1 is connected to the gate of the output signal MWLB of the main word line driver, the source is connected to the ground terminal GND, and the drain is connected to the word line SWL. The drain is connected to SWL, the source is connected to the ground terminal GND, and the second NMOS transistor Q2 to which the output signal FXB of the sub word line decoder is applied to the gate, and the first NMOS transistor Q1 A drain is connected to the drain, and an output signal of the main word line driver is applied to the gate, and a PMOS transistor Q3 is connected to a signal FX having an opposite phase of FXB to the source.

Meanwhile, the NMOS transistor Q4 and the capacitor C which are not described in FIGS. 1 and 2 are memory cells connected to the word line SWL and the bit line.

3 is an operation waveform diagram of a conventional self boosting word line driving circuit, and FIG. 4 is an operation waveform diagram of a conventional virtual stack type word line driving circuit.

As shown in Fig. 3, the output signal MWLB of the main word line driver goes to " Low ", while the opposite phase MWL signal transitions from " Low " to " High " and its potential is at the Vpp level.

This is the voltage generated by the chip with a power supply that is higher than the "High" potential of the memory cell and the threshold potential of the minimum memory cell.

Since the gate of the third NMOS transistor Q3 is at the Vpp level, the drain thereof rises to the Vpp + Vt potential by a booststrap.

Since the boosted node is the gate of the second NMOS transistor Q2, which is a pull-up transistor of the sub word line SWL, when the FX becomes "High", the potential of the SWL becomes the second. V potential, which is the potential of FX, is loaded without decreasing the Vt of the NMOS transistor Q2.

As shown in FIG. 4, when the output signal MWLB of the main word line driver transitions from "High" to "Low" to activate the word line, the first NMOS transistor Q1 is turned off and the PMOS transistor Q3 is turned on. Let's do it.

Subsequently, when the output signal FXB of the sub word line driver becomes "High", the second NMOS transistor Q2 is turned off to prepare to activate the sub word line, and when the FX becomes "High" or Vpp level, the PMOS transistor ( Through Q3), the sub word line is at the Vpp level without Vt drop.

However, in the conventional word line driving circuit as described above, there are the following problems.

First, the self-boosting method reduces layout area by laying out three NMOS transistors because the N-well area is not needed, but it is necessary to wait for the boosting node to be boosted between MWL and FX. The speed is slowed to activate the line.

Second, the virtual stack method has no time loss, which is advantageous for high speed, but is composed of CMOS (two NMOS transistors and one PMOS transistor), which limits the miniaturization of memory devices.

Disclosure of Invention The present invention has been made to solve the above-described problems, and an object thereof is to provide a word line driving circuit which prevents time loss and simultaneously reduces the number of transistors and reduces the layout area.

1 is a circuit diagram showing a conventional self-powered word line driving circuit.

2 is a circuit diagram illustrating a conventional virtual stack type word line driver circuit.

3 is an operation waveform diagram of a conventional self boosting word line driver circuit.

4 is an operation waveform diagram of a word line driving circuit of a conventional virtual stack method.

5 is a circuit diagram showing a word line driving circuit according to the present invention;

Explanation of symbols for the main parts of the drawings

Q1: NMOS transistor Q2: PMOS transistor

Q3: NMOS transistor C: capacitor

The word line driving circuit according to the present invention for achieving the above object is a first conductivity type transistor is connected to the power supply voltage to the gate, the source is connected to the ground terminal, the drain is connected to the sub word line, and the first conductive A drain is connected to the drain of the type transistor, the gate is connected to the output signal of the main word line driver, the source is characterized in that it comprises a second conductive transistor is connected to the output signal of the sub word line driver.

Hereinafter, a word line driving circuit according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram showing a word line driving circuit according to the present invention.

As illustrated in FIG. 5, an NMOS transistor Q1 having a power supply voltage VDD connected to a gate, a source connected to a ground terminal GND, and a drain connected to a sub word line SWL, and the NMOS transistor ( A drain is connected to the drain of Q1, the gate is connected to the output signal MWLB of the main word line driver, and the source is composed of a PMOS transistor Q2 connected to the output signal FX of the sub word line driver.

In the word line driving circuit, an NMOS transistor Q3 having a gate connected to a sub word line SWL, a source (or a drain) connected to a bit line, and a capacitor C connected to a drain (or source) ) Memory cells are connected.

Referring to the operation of the word line driving circuit according to the present invention configured as described above are as follows.

First, when the output signal MWLB of the main word line driver transitions from "High" to "Low" in order to activate the word line, the PMOS transistor Q2 is turned on.

Thereafter, when the output signal FX of the sub word line driver becomes "High" from "Low" to Vpp level, the sub word line SWL becomes Vpp level without dropping Vt through the PMOS transistor Q2.

When the output signal MWLB of the main word line driver goes from "Low" to "High", the potential of the sub word line SWL is lowered to the ground (GND) level by the NMOS transistor Q1 and the NMOS transistor of the memory cell. Turn off (Q3).

As described above, the word line driving circuit according to the present invention has the following effects.

In other words, by constructing a word line driving circuit using two MOS transistors, the layout area can be reduced, the chip size can be reduced, and the time line can be reduced, thereby enabling the word line to be activated quickly.

Claims (2)

A first conductivity type transistor having a supply voltage connected to a gate, a source connected to a ground terminal, and a drain connected to a sub word line; And a second conductive transistor connected to a drain of the first conductive transistor, a gate connected to an output signal of a main word line driver, and a source connected to an output signal of a sub word line driver. Line driving circuit. 2. The word line driver circuit according to claim 1, wherein the first conductivity type is N type and the second conductivity type is P type.