KR20020040231A - Method for manufacturing gate in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a gate of a semiconductor device is provided to form a dual metal gate by depositing a metal layer on an NMOS region and a PMOS region. CONSTITUTION: An isolation layer(11), an NMOS region(12a), and a PMOS region(12b) are formed on a semiconductor substrate(10). A gate insulating layer(13) is deposited on the semiconductor substrate(10). The first metal layer(14) is deposited on the gate insulating layer(13). The first metal layer(14) is formed by one of TiNx, WNx, TaNx, MoNx, and TiAlNx. The first metal layer(14) is deposited by using one of a sputtering deposition method, a single atom deposition method, and a remote plasma chemical vapor deposition method. A photoresist layer pattern is formed on the first metal layer(14). The second metal layer(16) and a hard mask layer(17) are deposited on the first metal layer(14) and the nitrated the first metal layer(14a). A dual gate is formed by performing a patterning process.

Description

METHOOD FOR MANUFACTURING GATE IN SEMICONDUCTOR DEVICE

The present invention relates to a method of manufacturing a gate of a semiconductor device, and more particularly to a method of manufacturing a dual metal gate.

As the degree of integration of semiconductors increases, the gate oxide films of semiconductor devices continue to become thinner. However, when the thickness of the gate oxide film is about 30 GPa or less, direct tunneling occurs, whereby a leakage current occurs in the semiconductor device, resulting in a decrease in electrical characteristics and high power consumption. In addition, the refresh characteristics in the DRAM are also reduced. Therefore, in recent years, research has been conducted to form a dielectric material having a high dielectric constant into a gate oxide film of a semiconductor device.

On the other hand, polysilicon gate electrodes, polyside gate electrodes, and the like have been used as gate electrodes in semiconductor devices. The polysilicon gate has problems such as an increase in the effective thickness of the gate insulating film due to the gate depletion phenomenon, a dopant penetration phenomenon from the p + or n + polysilicon gate to the substrate, and a change in the threshold voltage due to the dopant distribution variation.

Therefore, the development of a gate electrode having a new material and a new structure that can replace the gate using a conventional polysilicon has been required, the development of a metal gate electrode has been actively promoted in accordance with this demand.

Such metal gates can be deposited by sputtering or chemical vapor deposition, and have surface channels in order to form CMOS transistors capable of high-speed processing, which requires the use of dual metal gates. . Such a dual metal gate has to form two metal layers having different work functions in the NMOS and the PMOS, respectively. In forming the respective metal layers, an additional step of a mask step is required. In addition to the complexity of the manufacturing cost increases the problem.

In addition, recently, in order to solve the above problems, after the deposition of a single metal layer, an approach of adding nitrogen ion implantation to the PMOS has been attempted to have different work functions, but it is difficult to apply to the mass production process and nitrogen ion There is a problem that damage and deterioration of the gate oxide film due to the injection.

Accordingly, the present invention has been made to solve the above problems, a method of manufacturing a gate of a semiconductor device to form a dual metal gate by depositing a metal layer on the NMOS and PMOS region, and having a different work function in the metal layer. The purpose is to provide.

1A to 1C are cross-sectional views of a gate manufacturing method of a semiconductor device of the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor substrate 11 device isolation film

12a, 12b: NMOS and PMOS region 13: Gate insulating film

14: first metal layer 14a: nitrided first metal layer

15 photosensitive film pattern 16 second metal layer

17: hard mask

In order to achieve the above object, the present invention provides a semiconductor substrate comprising: defining a NMOS and PMOS region; Depositing a gate insulating film on the semiconductor substrate; Depositing a first metal layer on the gate insulating layer; Forming a photoresist pattern on the first metal layer of any one of the NMOS and PMOS regions; Nitriding a predetermined portion of the first metal layer using the photoresist pattern as an etch barrier; And removing the photoresist pattern to form a metal gate by depositing a second metal layer on the first metal layer on the NMOS and PMOS regions.

The first metal layer functions as a metal gate electrode barrier layer and is formed of any one of TiNx, WNx, TaNx, MoNx, and TiAlNx. At this time, x range of the first metal layer Nx is 0 to 0.5. In addition, the first metal layer is deposited in a thickness of 20 ~ 300Å range, by any one of sputtering deposition, monoatomic deposition and remote plasma chemical vapor deposition method, wherein the remote plasma chemical vapor deposition method is ECR Deposition is performed using an electron cyclotron resonance method. In addition, the remote plasma chemical vapor deposition method uses a frequency of 2.0 ~ 9GHz, and proceeds using one of helium, argon, krypton, and xeron during plasma excitation.

The nitriding process of the first metal layer is characterized by using a remote plasma nitriding method. This method proceeds using one of nitride ions and activated nitrogen, and the nitride method using nitride ions proceeds to apply a negative bias to the semiconductor substrate to inject nitrogen ions in a low energy region. In this case, the low energy region is in the range of 10 to 100 eV. In addition, the nitriding method using the activated nitrogen is performed by one of an electron cyclotron resonance (ECR) and a radical line slot antenna (RLSA) method, and plasma excitation using a frequency range of 2.0 to 9 GHz at a temperature of 50 to 450 ° C. Proceed with one of cy helium, argon, krypton, and xeron.

In addition, in the method of nitriding the first metal layer, the source of nitrogen may proceed in the temperature range of 50 ~ 450 ℃ using one of N2, NH3, ND3.

The second metal layer is formed of a tungsten film in a thickness of 300 to 1500 kPa.

(Example)

Hereinafter, exemplary embodiments of a method for manufacturing a gate of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views of a gate manufacturing method of a semiconductor device of the present invention.

First, referring to FIG. 1A, a semiconductor substrate 10 including an isolation layer 11 and NMOS and PMOS regions 12a and 12b is provided. Then, a gate insulating film 13 is deposited on the semiconductor substrate 10. The gate insulating layer 13 may be generally deposited as a silicon oxide film, and may also be formed by a thermal oxidation film by a furnace in a wet or dry manner at a temperature of 650 to 900 ° C. The gate insulating film 13 can also be formed of an insulating film having various metal oxides and high dielectric constants.

Then, the first metal layer 14 is deposited on the gate insulating layer 13. The first metal layer 14 serves as a metal gate electrode barrier layer and is formed of any one of TiNx, WNx, TaNx, MoNx, and TiAlNx. At this time, the x range of the first metal layer Nx is 0 to 0.5. In addition, the first metal layer 14 is deposited in a thickness range of 20 to 300Å, and is deposited through any one of sputtering deposition method, monoatomic deposition method, and remote plasma chemical vapor deposition method, wherein the remote plasma chemical vapor deposition method is used. Is deposited using an electron cyclotron resonance (ECR) method. In addition, the remote plasma chemical vapor deposition method uses a frequency of 2.0 ~ 9GHz, and proceeds using one of helium, argon, krypton, and xeron during plasma excitation.

Next, referring to FIG. 1B, a photosensitive film pattern 15 is formed on one of the NMOS and PMOS regions 12a and 12b, for example, on the first metal layer 14 above the NMOS region 12a. Thereafter, a nitrogen-containing process is performed using the photoresist pattern 15 as an etch barrier to form the nitrided first metal layer 14a on the PMOS region 12b. The work function of the nitrided first metal layer 14a formed as described above and the first metal layer 14 on the NMOS region 12a is different.

Here, the nitrogen-containing process is carried out by a remote plasma nitriding method. The nitrogen-containing process is a means for controlling the amount of nitrogen, and the first metal layer 14 is nitrided using a remote plasma chemical vapor deposition method. This nitrates the metal layer in the range of 20 to 100 microseconds, which can be free from plasma damage.

The remote plasma chemical vapor deposition method is performed using one of nitride ions and activated nitrogen. The nitride method using nitride ions proceeds to apply a negative bias to the semiconductor substrate to inject nitrogen ions in a low energy region. At this time, the low energy range is in the range of 10 ~ 100eV. In addition, the nitriding method using the activated nitrogen proceeds by one of electron cyclotron resonance (ECR) and radical line slot antenna (RLSA) methods, using a frequency of 2.0 to 9 GHz in a temperature range of 50 to 450 ° C., and plasma The excitation proceeds using one of helium, argon, krypton, and xeron.

In addition, in the method of nitriding the first metal layer, the source of nitrogen may be performed at a temperature of 50 to 450 ° C. using one of N 2, NH 3, and ND 3.

Next, referring to FIG. 1C, after the photoresist pattern 15 is removed, the second metal layer 14 may be formed on the first metal layer 14 and the nitrided first metal layer 14a formed on the NMOS and PMOS regions 12a and 12b. 16) and the hard mask film 17 are sequentially deposited. Here, the second metal layer 16 is preferably formed of a tungsten film in the range of 300 to 1500 kPa in thickness. Then, after the hard mask film 17 is partially patterned, as is known, the second metal layer 16 and the first metal layer on the NMOS and PMOS regions 12a and 12b are formed using the hard mask film 17 as an etch barrier. The metal layer, the nitrided first metal layers 14 and 14a, and the gate insulating layer are sequentially patterned to form dual gates of the semiconductor device.

As described in detail above, a nitrogen-containing process is performed on one of the first metal layers 14 formed on the NMOS and PMOS regions, that is, the first metal layer on the PMOS region, thereby producing a metal layer having different work functions. Form. Thereafter, after forming the second metal layer on the first metal layer having different work functions, the dual metal gate is formed by performing a patterning process.

At this time, plasma damage and deterioration are prevented on the gate insulating film by using the remote plasma chemical vapor deposition method.

Accordingly, when forming the dual metal gate of the high-density semiconductor device, a first metal layer having a different work function is additionally formed once in a mask step, thereby resulting in process simplification and manufacturing cost reduction.

In addition, it can implement in various changes within the range which does not deviate from the summary of this invention.

Claims (16)

Providing a semiconductor substrate defining an NMOS and a PMOS region; Depositing a gate insulating film on the semiconductor substrate; Depositing a first metal layer on the gate insulating layer; Forming a photoresist pattern on the first metal layer of any one of the NMOS and PMOS regions; Nitriding a predetermined portion of the first metal layer using the photoresist pattern as an etch barrier; And After removing the photoresist pattern, forming a metal gate by depositing a second metal layer on the first metal layer on the NMOS and PMOS regions. The method of claim 1, And the first metal layer serves as a metal gate electrode barrier layer. The method of claim 1, The first metal layer is a gate manufacturing method of a semiconductor device, characterized in that consisting of any one of TiNx, WNx, TaNx, MoNx and TiAlNx. The method of claim 3, wherein X range of the first metal layer Nx is 0 to 0.5. The method of claim 1, The first metal layer is a gate manufacturing method of the semiconductor device, characterized in that deposited in the range of 20 ~ 300Å thickness. The method of claim 1, The first metal layer is a gate manufacturing method of a semiconductor device, characterized in that deposited by any one of sputtering deposition method, monoatomic deposition method and remote plasma chemical vapor deposition method. The method of claim 6, The remote plasma chemical vapor deposition method uses an electron cyclotron resonance (ECR) method. The method of claim 7, wherein The remote plasma chemical vapor deposition method uses a frequency of 2.0 ~ 9GHz, the plasma manufacturing method of the semiconductor device gate, characterized in that proceeding using one of helium, argon, krypton, and xeron. The method of claim 1, The nitriding process of the first metal layer uses a remote plasma nitridation method. The method of claim 9, The method of manufacturing a gate of a semiconductor device according to claim 1, wherein the remote plasma nitridation method is performed using one of nitride ions and activated nitrogen. The method of claim 10, In the nitriding method using the nitride ion, a negative bias is applied to the semiconductor substrate to inject nitrogen ions in a low energy region into the semiconductor device. The method of claim 11, The low energy region is a gate manufacturing method of a semiconductor device, characterized in that 10 to 100eV range. The method of claim 10, The nitriding method using the activated nitrogen is performed by one of electron cyclotron resonance (ECR) and radical line slot antenna (RLSA) methods. The method of claim 1, In the method of nitriding the first metal layer, the source of nitrogen proceeds in the temperature range of 50 ~ 450 ℃ using one of N2, NH3, ND3. The method of claim 13, The first metal layer nitriding method uses a frequency range of 2.0 to 9 GHz in a temperature range of 50 to 450 ° C. to fabricate a gate of a semiconductor device, wherein the plasma is excited using one of helium, argon, krypton, and xeron. Way. The method of claim 1, The second metal layer is a tungsten film is a gate manufacturing method of a semiconductor device, characterized in that formed in the thickness range 300 ~ 1500Å.