KR20020038248A - Method of forming a test pattern for measuring a sidewall capacitance and a leakage characteristic in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a test pattern is provided to measure sidewall capacitance and a leakage current characteristic of a semiconductor device, by forming a bit line of a surpentine structure on a wafer, by forming a sidewall in the surpentine structure and by filling an electrode material to form an upper electrode. CONSTITUTION: A bit line(20) and a bit line sidewall(30) are formed on a wafer(10). A metal contact for connecting an electrode is formed at both ends of the bit line. A plug filling material is applied on the entire surface including the metal contact. The plug filling material is patterned to form the upper electrode.

Description

Method of forming a test pattern for measuring a sidewall capacitance and a leakage characteristic in a semiconductor device

The present invention relates to a test pattern forming method for measuring sidewall capacitance and leakage characteristics of a semiconductor device, and more particularly, to a test pattern forming method useful for measuring bitline sidewall capacitance or leakage current.

In general, the most important parameters in memory semiconductors are the bitline capacitors and bitline sidewall leakage currents. The bit line capacitor is closely related to the efficiency of inputting and outputting signals of the DRAM. In general, it is common sense to measure capacitance on a flat plate, but it is very difficult to measure capacitance when there is a very fine and topology such as a sidewall of a bit line. In the past, the capacitance at the bit line was only available in the state where most processes were completed, so the measurement was very complicated and the time loss was very large. In addition, in the case of the leakage characteristic, the refresh characteristic is measured, and therefore, a large number of causes had to be obtained.

Accordingly, the present invention can measure sidewall capacitance and leakage current by forming a bit line on a wafer by a sherpentine structure, forming a sidewall in the structure, and then filling an electrode material to form an upper electrode. An object of the present invention is to provide a test pattern forming method for measuring sidewall capacitance and leakage characteristics of a semiconductor device.

1A is a plan view of a state where a bit line and a bit line sidewall of a sherpentine structure are formed on a wafer;

FIG. 1B is a plan view of a metal contact for forming electrode contact when measured in FIG. 1A; FIG.

1C is a plan view of a state in which a plug embedding material such as polysilicon or tungsten is embedded over an entire surface to form a contact plug in FIG. 1B;

FIG. 1D is a plan view of the plug buried material of FIG. 1C in the patterned state; FIG.

FIG. 2 is a cross-sectional view of a part of FIG. 1C taken out and cut;

* Explanation of symbols for the main parts of the drawings

10: wafer 20: bit line

30: bit line sidewall 40: metal contact

50: landfill material

According to an aspect of the present invention, there is provided a method of forming a test pattern for measuring capacitance and leakage characteristics of a semiconductor device, the method including: forming bit lines and bit line sidewalls on a wafer;

Forming metal contacts at both ends of the bit line to connect electrodes when measured;

Embedding a plug embedding material over the entire surface including the metal contact;

Patterning the plug embedding material to form an upper electrode.

The plug buried material is buried by a chemical vapor deposition method, and the bit line has a sherpentine structure.

The plug buried material is formed of any one of TiN, tungsten and polysilicon.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1A is a plan view of a state where a bit line and a bit line sidewall of a sherpentin structure are formed on a wafer. As shown in FIG. 1A, a conductive material is coated on the wafer 10 and then patterned to form a bit line 20 having a sherpentin structure. An insulating material is coated on the bit line 20, and a front side etching process is performed to form sidewalls 30 on the sidewalls of the bit line.

FIG. 1B is a plan view of a metal contact for forming electrode contact when measured in FIG. 1A; FIG. Both ends of the bit line 20 as shown in FIG. That is, the metal contact 40 is formed on the capturing pad portion.

FIG. 1C is a plan view showing a plug embedding material such as polysilicon or tungsten on the entire surface of the contact plug in FIG. 1B. As shown, a plug buried material 50 such as tungsten or polysilicon is applied by chemical vapor deposition to fill the space between the bit lines 20 to form a contact plug on top of the entire structure of FIG. 1C.

FIG. 1D is a plan view of the plug buried material of FIG. 1C in a patterned state. FIG.

Since the plug embedding material is applied to the entire surface of the wafer as shown in FIG. 1D, the plug embedding material is patterned to separate and probe the test pattern. As a result, the upper electrode 60 is formed. Here, the plug embedding material is formed of any one of TiN and tungsten polysilicon.

FIG. 2 is a cross-sectional view of a part of FIG. 1C taken out and cut.

As shown, sidewalls 30 made of an insulating material are formed on the upper and sidewalls of the bit line 20, and an upper electrode 60 is formed thereon.

Both ends of the bit line and the upper electrode serve as measurement terminals. That is, these electrodes can be used to measure sidewall capacitance and leakage current of the bit line.

As described above, according to the present invention, a sidewall capacitance and leakage current are formed by forming a bit line on a wafer in a sherpentine structure, forming a sidewall in the structure, and then filling an electrode material to form an upper electrode. It can be measured.

Although the present invention has been described by way of example, various modifications can be made by those skilled in the art. Therefore, the present invention is not limited to the above-described embodiments but is defined by the claims.

Claims (4)

Forming bitlines and bitline sidewalls on the wafer; Forming metal contacts at both ends of the bit line to connect electrodes when measured; Embedding a plug embedding material over the entire surface including the metal contact; A method of forming a test pattern for measuring sidewall capacitance and leakage characteristics of a semiconductor device, the method including forming a top electrode by patterning a plug buried material. The method of claim 1, The method of forming a test pattern for measuring sidewall capacitance and leakage characteristics of a semiconductor device, wherein the plug buried material is buried by chemical vapor deposition. The method of claim 1, And the bit line has a sherpentine structure. The method of claim 1, The method of forming a test pattern for measuring sidewall capacitance and leakage characteristics of a semiconductor device, wherein the plug filling material is formed of any one of TiN, tungsten, and polysilicon.