KR20020030872A - solder mask or dielectric materials coated lead frame and manufacturing method - Google Patents

solder mask or dielectric materials coated lead frame and manufacturing method Download PDF

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Publication number
KR20020030872A
KR20020030872A KR1020000061195A KR20000061195A KR20020030872A KR 20020030872 A KR20020030872 A KR 20020030872A KR 1020000061195 A KR1020000061195 A KR 1020000061195A KR 20000061195 A KR20000061195 A KR 20000061195A KR 20020030872 A KR20020030872 A KR 20020030872A
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South Korea
Prior art keywords
lead frame
solder mask
lead
wire bonding
wire
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KR1020000061195A
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Korean (ko)
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KR100342403B1 (en
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권오유
김은주
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김 무
주식회사 아큐텍반도체기술
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A lead frame on which a solder mask is mounted is provided to fabricate a thinner package and to decrease the number of processes, by mounting the solder mask or insulating material on the lead frame of a metallic material so that an additional molding process for protecting a bonding region becomes unnecessary after a wire bonding process. CONSTITUTION: The lead frame of a metallic material as a pad(11) on which a semiconductor chip(15) is mounted, a lead(12) and a tie bar is patterned to have a radial type. A solder mask layer of an insulation material is mounted on the lead from the outside of a wire bonding region(A) to a packaging line to prevent damage to the lead when the patterned lead frame is transferred in a transfer line. A plating layer is plated in the wire bonding region and a solder region(B) of the lead frame on which the solder mask(14) is mounted. The semiconductor chip mounted on the pad and the inner lead(12a) of the lead frame are wire-bonded by a gold wire and electrically conducted. The semiconductor chip and the gold wire are prevented from being exposed to form an encapsulating unit for protecting the wire bonding region.

Description

솔더마스크가 장착된 리드프레임 및 그 제조방법{solder mask or dielectric materials coated lead frame and manufacturing method}Lead frame with solder mask and manufacturing method thereof {solder mask or dielectric materials coated lead frame and manufacturing method}

본 발명은 리드프레임에 솔더마스크(solder mask) 또는 폴리이마이드 테이프(polyimide tape)등과 같은 절연물질(dielectrical material)이 장착되는 리드프레임 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame in which a dielectric material such as a solder mask or a polyimide tape is mounted on the lead frame, and a method of manufacturing the same.

더욱 상세하게는, 금속재질의 리드프레임에 솔더마스크 또는 절연물질을 장착하여 와이어본딩후 본딩 영역을 보호하기 위한 별도의 몰딩작업이 불필요하여 보다 얇은 경박단소형의 패키지를 제작할 수 있도록 한 솔더마스크가 장착된 리드프레임 및 그 제조방법에 관한 것이다.More specifically, solder mask or insulation material is attached to the lead frame made of metal, so that no soldering is required to protect the bonding area after wire bonding. It relates to a mounted lead frame and a method of manufacturing the same.

일반적으로, 반도체패키지의 리드프레임(lead frame)은 반도체칩과 인쇄회로기판과 같은 전기, 전자장치를 전기적으로 도통시키도록 연결해주는 경박단소(輕薄短小)형의 매개수단으로서 사용되고 있다.In general, a lead frame of a semiconductor package is used as a medium and thin type medium and medium for connecting electrically and electronic devices such as semiconductor chips and printed circuit boards to be electrically connected.

전술한 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(tape carrier package)패키지, 글래스밀봉 패키지, 금속밀봉 패키지등이 있다. 이들은 다이패드에 대해 실장방법에 따라 삽입형과 표면실장(surface mount technology)형으로 분류되며, 삽입형의 대표적인 패키지는 DIP(dual in-line package), PGA(pin grid array)등이 있고, 표면실장형의 대표적인 패키지로서는 QFP(quad flat package),PLCC(plastic leaded chip carrier), CLCC(ceramic leaded chip carrier), BGA(ball grid array)등이 있다.The semiconductor package described above may be a resin sealing package, a tape carrier package (TCP) package, a glass sealing package, a metal sealing package, or the like, according to its type. These are classified into insert type and surface mount technology type according to the mounting method for die pads. Representative packages of the insert type include DIP (dual in-line package) and PGA (pin grid array). Typical packages include quad flat package (QFP), plastic leaded chip carrier (PLCC), ceramic leaded chip carrier (CLCC), and ball grid array (BGA).

도 1에 도시된 바와 같이, 종래 기술에 의한 전형적인 리드프레임 패키지는, 반도체칩(15)이 장착되는 패드(11), 리드(12) 및 타이바(13)(tie bar)로서 방산형의 형태를 갖도록 패턴화(patterning)되는 구리, 철, 니켈, 알미늄, 이들 합금으로서 형성되는 금속재질의 리드프레임(10)과, 패턴화된 리드프레임(10)이 이송라인에서 이송시 리드(12)가 손상되는 것을 방지할 수 있도록 와이어본딩 영역(A)의 외곽부에 테이프가 장착된 리드프레임(10)의 와이어본딩영역(A)과 솔더 영역(B)에 각각 적용되는 은도금 및 솔더도금으로서 이중도금되는 도금층과, 패드(11)에 탑제되는 반도체칩(15)과 리드프레임(10)의 이너리드(12a)를 와이어본딩시켜 전기적으로 도통가능하게 연결하는 골드와이어(16)와, 반도체칩(15)과 골드와이어(16)부위를 산화 및 부식등으로부터 보호할 수 있도록 외부를 에폭시수지에 의해 몰딩처리하는 몰딩부(18)를 구비하게 된다.As shown in FIG. 1, a typical leadframe package according to the prior art is in the form of a dissipation type as a pad 11, a lead 12, and a tie bar on which a semiconductor chip 15 is mounted. Copper, iron, nickel, aluminum patterned so as to have a lead frame 10 of the metal material formed as these alloys, and the patterned lead frame 10 when the lead 12 is transported in the transfer line Silver plating and solder plating are respectively applied to the wire bonding area A and the solder area B of the lead frame 10 in which the tape is mounted on the outer portion of the wire bonding area A so as to prevent damage. The gold layer 16 connected to the plated layer, the semiconductor chip 15 mounted on the pad 11, and the inner lead 12a of the lead frame 10 to be electrically conductively connected, and the semiconductor chip 15. ) And gold wire (16) to protect from oxidation and corrosion It is provided with a molding section 18 for handling molded parts by the epoxy resin.

이때, 종래의 전형적인 리드프레임을 제조하는 작업공정은, 구리, 구리합금 또는 철합금계의 기판을 식각법(etching) 또는 스템핑 방식으로 패턴을 형성하는 단계와, 와이어본딩이 이루어지는 반도체칩과 이너리드(inner lead)부에 와이어본딩(wire bonding)을 위한 은도금 또는 금도금을 실시하는 단계와, 이송라인에서 리드의 보호와 다운셋(down set)시의 안정성을 위하여 테이핑하는 단계와, 리드프레임의 다이패드에 반도체칩을 장착하여 반도체칩과 리드프레임의 전기적인 연결을 위하여 골드와이어(gold wire)로 반도체칩과 리드프레임의 이너리드를 와이어본딩하는 단계와, 본딩 영역을 보호하기 위하여 리드프레임의 아웃리드를 제외한 리드프레임의 전후면을 에폭시계의 몰딩제로서 몰딩성형하는 단계와, 리드프레임 후면의 솔더마스크에 선택적으로 개방된 부위에 주석-납 성분의 솔더볼(solder ball)을 장착하는 단계를 포함하여 리드프레임을 제조하게 된다.At this time, the work process of manufacturing a typical lead frame, the step of forming a pattern of the copper, copper alloy or iron alloy substrate by etching or stamping method, the semiconductor chip and the inner wire bonding Performing silver plating or gold plating for wire bonding on the inner lead, taping for protection of the lead in the transfer line and stability during downset, and Mounting a semiconductor chip on the die pad to wirebond the inner lead of the semiconductor chip and the leadframe with gold wires for electrical connection between the semiconductor chip and the leadframe, and to protect the bonding area of the leadframe. Molding the front and rear surfaces of the lead frame excluding the outlead with an epoxy-based molding agent, and selectively opening the solder mask on the rear side of the lead frame. The lead frame is manufactured by attaching a solder ball of a tin-lead component to the uneven portion.

그러나, 전술한 바와 같이 전형적인 리드프레임을 제조하는 경우 아래와 같은 문제점을 갖게된다.However, when manufacturing a typical lead frame as described above has the following problems.

전술한 테이핑 공정에서 리드프레임의 전면을 고가의 테이프로서 도포한 후 일정부분(이너리드 외각의 적은 부분)을 제외한 테이프를 다시 제거하는 작업을 함에 따라 전면에 도포되는 고가의 테이프 사용으로 인한 원가비용이 상승되는 문제점과, 테이프의 도포 및 이를 제거하는 공정으로 인해 작업성이 떨어지는 문제점을 갖게된다.In the taping process described above, the front surface of the lead frame is applied as an expensive tape, and then the tape is removed again except for a certain portion (less part of the inner lid), so that the expensive tape applied to the front surface is used. Due to this rising problem and the process of applying and removing the tape, there is a problem of poor workability.

또한, 리드프레임의 패드에 반도체칩을 장착하여 와이어본딩 후, 본딩 영역을 포함하여 전면을 소정두께로서 몰딩성형함에 따라 리드프레임의 전체 두께가 증가되는 문제점과, 이로 인해 리드프레임을 인쇄회로기판에 장착하는 인쇄회로기판의 설계시 제한을 받게되는 문제점을 갖게된다.In addition, after the semiconductor chip is mounted on the pad of the lead frame by wire bonding, the overall thickness of the lead frame is increased by molding the front surface with a predetermined thickness including the bonding area, and thus the lead frame is attached to the printed circuit board. There is a problem that is limited in the design of the printed circuit board to be mounted.

또한, 와이어 본딩영역과 솔더 접합부에 기능상 적용되는 도금이 상이하여 부위에 따라 은도금 또는 솔더도금에 의한 이중도금을 하게되므로 부위에 따른 선택적인 도금을 위하여 외부 마스크 설계 및 이를 제어하는 공정이 추가로 요구되는 문제점을 갖게된다.In addition, since the plating applied to the wire bonding area and the solder joint is different from each other, double plating is performed by silver plating or solder plating depending on the part, and thus an external mask design and a process for controlling the same are required for selective plating according to the part. You have a problem.

따라서, 본 발명의 목적은, 금속재질의 리드프레임에 솔더마스크 또는 절연소재를 장착하여 노출부위에 전면도금(PPF)을 실시한 후 와이어본딩을 실시하고, 와이어본딩후 본딩 영역을 보호하기 위한 별도의 몰딩작업이 불필요하게 되어 보다 얇은 패키지(30%이상 향상됨)를 제작하며, 이로 인한 작업공수 단축으로 제작비용을 절감할 수 있도록 한 솔더마스크가 장착된 리드프레임 및 그 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to attach a solder mask or an insulating material to a lead frame made of metal, and perform wire bonding after exposing the front surface (PPF) to an exposed part, and to separate the bonding area to protect the bonding area after wire bonding. It is to provide a lead frame equipped with a solder mask and a method of manufacturing the same, which makes a thinner package (more than 30% improved) due to the need for no molding work and thus reduces manufacturing costs by reducing the labor time.

본 발명의 다른 목적은, 패턴성형후 이송라인에서 리드의 보호와 다운셋시의 안정성을 확보하기 위하여 테이핑하는 작업공정이 불필요하여 원가비용 및 제작비용을 절감할 수 있도록 한 솔더마스크가 장착된 리드프레임 및 그 제조방법을 제공하는 것이다.Another object of the present invention, the lead is equipped with a solder mask to reduce the cost and manufacturing cost is unnecessary because the tape work process is unnecessary to ensure the protection of the lead in the transfer line after pattern molding and to ensure the stability during downset It is to provide a frame and a method of manufacturing the same.

본 발명의 또 다른 목적은, 리드프레임의 마스킹부위를 후도금으로서 전면도금함에 따라 아웃리드부를 솔더도금하는 작업공정이 불필요하여 작업공수 단축으로 인해 제작비용 및 폐수처리비용을 절감할 수 있고, 종래의 몰딩후 별도의 솔더도금을 하지않고 전면도금을 함에 따라 환경규제대상인 납(Pb)을 사용하지 않아 환경친화적인 도금을 할 수 있도록 한 솔더마스크가 장착된 리드프레임 및 그 제조방법을 제공하는 것이다.Still another object of the present invention is to reduce the manufacturing cost and wastewater treatment cost due to the reduction of the labor time by eliminating the need for a solder plating process of the outlead part as the entire surface of the lead frame is plated as a post plating. It is to provide a lead frame equipped with a solder mask and a method of manufacturing the same, which allows for environmentally friendly plating without the use of lead (Pb), which is an environmental regulation target, due to the front plating without separate solder plating after molding. .

도 1은 종래 기술에 의한 전형적인 리드프레임 패키지의 구성도,1 is a block diagram of a typical leadframe package according to the prior art,

도 2는 본 발명에 의한 솔더마스크가 장착된 리드프레임의 개략도,2 is a schematic view of a lead frame equipped with a solder mask according to the present invention;

도 3은 본 발명에 의한 솔더마스크가 장착된 리드프레임에 칩이 장착된 상태도,3 is a state in which a chip is mounted on a lead frame equipped with a solder mask according to the present invention;

도 4는 본 발명에 의한 솔더마스크가 장착된 리드프레임을 제조하는 방법을 나타내는 흐름도 이다.4 is a flowchart illustrating a method of manufacturing a lead frame having a solder mask according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10; 리드프레임10; Leadframe

11; 패드11; pad

12; 리드12; lead

12a; 이너리드(inner lead)12a; Inner lead

12b; 아웃리드(outer lead)12b; Out lead

13; 타이바(tie bar)13; Tie bar

14; 솔더마스크14; Solder mask

15; 반도체칩15; Semiconductor chip

A; 와이어본딩 영역A; Wirebonding area

B; 솔더 영역B; Solder area

전술한 본 발명의 목적은, 반도체칩이 장착되는 패드, 리드 및 타이바로서 방산형의 형태를 갖도록 패턴화되는 금속재질의 리드프레임과, 패턴화된 리드프레임이 이송라인에서 이송시 리드가 손상되는 것을 방지할 수 있도록 와이어본딩 영역의 외곽부터 패키징라인까지의 리드에 장착되는 솔더마스크층과, 솔더마스크가 장착된 리드프레임의 와이어본딩 영역과 솔더 영역에 전면도금되는 도금층과, 패드에 탑제되는 반도체칩과 리드프레임의 이너리드를 와이어본딩시켜 전기적으로 도통가능하게 연결하는 골드와이어와, 반도체칩과 골드와이어의 노출을 방지하여 와이어본딩 영역을 보호할 수 있도록 봉지하는 봉지부를 구비하는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임을 제공함에 의해 달성된다.The object of the present invention described above is that a lead frame of a metal material patterned to have a dissipation type as pads, leads, and tie bars on which semiconductor chips are mounted, and leads are damaged when the patterned lead frame is transferred in a transfer line The solder mask layer is mounted on the lead from the outside of the wire bonding area to the packaging line to prevent it from being formed, the wire bonding area of the lead frame on which the solder mask is mounted, the plating layer which is plated on the solder area, and the pad And a gold wire that electrically connects the inner lead of the semiconductor chip and the lead frame to be electrically connected to each other, and an encapsulation part that is encapsulated to protect the wire bonding area by preventing the semiconductor chip and the gold wire from being exposed. This is accomplished by providing a leadframe with a solder mask.

바람직한 실시예에 의하면, 전술한 리드프레임의 리드가 이송라인에서 이송시 손상되는 것을 방지할 수 있도록 와이어본딩 영역의 외곽부터 패키징라인까지의 리드에 폴리이마이드 테이프가 장착될 수 있다.According to a preferred embodiment, the polyimide tape may be mounted on the lead from the outside of the wire bonding area to the packaging line so as to prevent the lead of the above-described lead frame from being damaged during transfer in the transfer line.

바람직한 실시예에 의하면, 전술한 솔더마스크층은 포토이메이징공법, 폴리이마이드를 소재로 하는 적외선 타입의 리퀴드솔더마스크 잉크 및 절연물질등을 사용한 레이저가공법, 플라즈마 에칭방식, 실크스크린프린팅, 메탈마스크를 이용한 도포법, 분사 및 투여법을 이용한 도포법 및 정묘법에 의한 도포법중 어느 하나를 선택하여 장착될 수 있다.According to a preferred embodiment, the solder mask layer described above is a photo-imaging method, a laser processing method using an infrared type liquid solder mask ink and an insulating material made of polyimide, plasma etching method, silk screen printing, metal mask Any one of the coating method using the coating method, the spraying and the administering method, and the coating method by the drawing method can be selected and mounted.

바람직한 실시예에 의하면, 전술한 리드프레임의 와이어본딩 영역과 솔더 영역에 걸쳐 전면도금되는 도금층은 니켈/파라듐, 니켈/금도금, 금-은합금도금 및 니켈중 어느 하나를 선택하여 도금될 수 있다.According to a preferred embodiment, the plating layer which is plated over the wire bonding region and the solder region of the lead frame described above may be plated by selecting any one of nickel / paradium, nickel / gold plating, gold-silver alloy plating, and nickel.

전술한 본 발명의 목적은, 반도체칩이 장착되는 패드, 리드 및 타이바로서 방산형의 형태를 갖도록 금속재질의 리드프레임을 패턴화시키는 단계와, 패턴화된 리드프레임이 이송라인에서 이송시 리드가 손상되는 것을 방지할 수 있도록 와이어본딩 영역의 외곽부터 패키징라인까지의 리드에 솔더마스크를 장착하는 단계와, 솔더마스크가 장착된 리드프레임의 와이어본딩 영역과 솔더 영역에 걸쳐 전면도금하는 단계와, 패드에 탑제되는 반도체칩과 리드프레임의 이너리드를 골드와이어로서 전기적으로 연결되도록 와어어본딩시키는 단계와, 반도체칩과 골드와이어의 노출을 방지하여 와이어본딩 영역을 봉지하여 보호할 수 있도록 봉지부를 성형하는 단계와, 단품패키지의 트리밍과 리드프레임의 아웃리드를 포밍하는 단계를 포함하는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임의 제조방법을 제공함에 의해 달성된다.An object of the present invention described above is to pattern a lead frame made of metal so as to have a dissipation type as pads, leads, and tie bars on which semiconductor chips are mounted, and when the leaded patterned lead frame is transferred in a transfer line, Mounting a solder mask on the leads from the outside of the wire bonding area to the packaging line to prevent damage, and forcing the surface over the wire bonding area and the solder area of the lead frame on which the solder mask is mounted; Wire-bonding the inner chip of the semiconductor chip and the lead frame mounted on the wire to be electrically connected as gold wires, and forming an encapsulation portion to seal and protect the wire bonding area by preventing the semiconductor chip and the gold wire from being exposed. And trimming the single package and forming outleads of the leadframe. The solder mask is achieved by providing a method of manufacturing a lead frame for mounting.

바람직한 실시예에 의하면, 전술한 솔더마스크가 장착된 리드프레임의 와이어본딩 영역은 은도금 또는 금도금으로서 부분적으로 도금하며, 리드프레임의 솔더 영역은 솔더도금으로서 부분적으로 도금시킬 수 있다.According to a preferred embodiment, the wire bonding region of the lead frame on which the aforementioned solder mask is mounted may be partially plated as silver plating or gold plating, and the solder region of the lead frame may be partially plated as solder plating.

이하, 본 발명의 바람직한 실시예를 첨부도면에 따라 상세하게 설명하되, 이는 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도로 상세하게 설명하기 위한 것이지, 이로 인해 본 발명의 기술적인 범주가 한정되는 것을 의미하지는 않는 것이다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, which are intended to be described in detail to be easily carried out by those skilled in the art to which the present invention pertains, and thus the present invention It does not mean that the technical scope of the is limited.

도 2 내지 도 4에 도시된 바와 같이, 반도체칩(15)이 장착되는 패드(11), 리드(12) 및 타이바(13)(tie bar)로서 방산형의 형태를 갖도록 패턴화(patterning)되는 구리, 철, 니켈, 알미늄 또는 이들 합금으로서 형성되는 금속재질의 리드프레임(10)과, 패턴화된 리드프레임(10)이 이송라인에서 이송시 리드(12)가 손상되는 것을 방지할 수 있도록 와이어본딩 영역(A)의 외곽부터 패키징라인(L)까지의 리드(12)에 장착되는 솔더마스크(14)와, 솔더마스크(14)가 장착된 리드프레임(10)의 와이어본딩 영역(A)과 솔더 영역(B)에 전면도금되는 도금층과, 패드(11)에 탑제되는 반도체칩(15)과 리드프레임(10)의 이너리드(12a)를 와이어본딩시켜 전기적으로 도통가능하게 연결하는 골드와이어(16)와, 반도체칩(15)과 골드와이어(16)의 노출을 방지하여 와이어본딩 영역을 보호할 수 있도록 에폭시수지에 의해 봉지하는 봉지부(17)를 구비한다.2 to 4, the pad 11, the lead 12, and the tie bar 13 on which the semiconductor chip 15 is mounted are patterned to have a dissipation type. The lead frame 10 and the patterned lead frame 10 made of copper, iron, nickel, aluminum, or a metal material formed as these alloys can be prevented from damaging the lead 12 during transfer in a transfer line. The solder mask 14 mounted on the lead 12 from the outside of the wire bonding area A to the packaging line L, and the wire bonding area A of the lead frame 10 on which the solder mask 14 is mounted. And a gold layer electrically connected to each other by wire-bonding the plated layer overlying the solder region B, the semiconductor chip 15 mounted on the pad 11, and the inner lead 12a of the lead frame 10. And the epoxy so as to protect the wire bonding region by preventing the semiconductor chip 15 and the gold wire 16 from being exposed. The sealing part 17 is sealed by the resin.

이때, 전술한 리드프레임(10)의 리드(12)가 이송라인에서 이송시 손상되는 것을 방지할 수 있도록 와이어본딩 영역(A)의 외곽부터 패키징라인(L)까지의 리드(12)에 폴리이마이드 테이프(미도시됨)와 같은 절연테이프가 장착될 수 있다.At this time, the polyimide in the lead 12 from the outside of the wire bonding region (A) to the packaging line (L) to prevent the above-described lead 12 of the lead frame 10 is damaged during the transfer in the transfer line Insulating tape, such as tape (not shown), may be mounted.

또한, 전술한 리드프레임(10)의 와이어본딩 영역(A)과 솔더 영역(B)에 걸쳐 전면도금되는 도금층은 니켈/파라듐(palladium), 니켈/금도금, 니켈/금-은합금도금중 어느 하나를 선택하여 도금될 수 있다.In addition, the plating layer which is plated over the wire bonding region A and the solder region B of the lead frame 10 described above may be any one of nickel / palladium, nickel / gold plating, and nickel / gold-silver alloy plating. It can be plated by selecting.

이하에서, 본 발명에 의한 솔더마스크가 장착된 리드프레임의 제조방법을 첨부도면을 참조하여 설명하면 아래와 같다.Hereinafter, a method for manufacturing a lead frame equipped with a solder mask according to the present invention will be described with reference to the accompanying drawings.

도 4에 도시된 바와 같이, 금속재질인 리드프레임(10) 소재를 전처리하여 세정시킨다(S10 참조).As shown in FIG. 4, the material of the lead frame 10, which is a metal material, is pretreated and cleaned (see S10).

전술한 리드프레임(10)을 식각법(etching) 또는 스템핑 방식으로 반도체칩이 장착되는 패드(11), 리드(12) 및 타이바(13)(tie bar)로서 구성된 방산형의 형태를 갖도록 패턴화시킨다(S20 참조). 이때 리드프레임(10)으로서 구리, 알미늄, 구리합금, 니켈/철, 철합금계중 어느 하나가 사용되는 것이 바람직하다.The lead frame 10 described above has a shape of a dissipation type configured as a pad 11, a lead 12, and a tie bar on which a semiconductor chip is mounted by etching or stamping. Patterning (see S20). At this time, it is preferable that any one of copper, aluminum, a copper alloy, nickel / iron, and an iron alloy system is used as the lead frame 10.

패턴화된 리드프레임(10)의 이송라인에서 이송시 리드(12)가 손상되는 것을 방지할 수 있도록 본딩 영역(A)의 외곽부터 패키징라인(L)까지를 솔더마스크 또는 절연테이프등과 같은 절연물질을 장착한다(S30 참조).Insulation such as solder mask or insulating tape from the outside of the bonding area A to the packaging line L to prevent the lead 12 from being damaged during transfer in the transfer line of the patterned lead frame 10. Mount the material (see S30).

이때, 절연물질(dielectric material)로서 폴리이마이드 테이프가 사용되는 것이 바람직하며, 솔더마스크는 포토이메이징공법(photoimaging) 또는 폴리이마이드를 소재로 하는 적외선 타입(IR type)의 리퀴드솔더마스크 잉크(liquid solder mask ink) 및 절연물질등을 사용한 레이저가공법 또는 플라즈마 에칭방식(plasma etching type), 실크스크린프린팅(silk screen printing), 메탈마스크(metal mask)를 이용한 도포법, 분사(injection) 및 투여(dispensing)법을 이용한 도포법, 정묘법(dotting)에 의한 도포법중 어느 하나를 사용하는 것이 바람직하다.In this case, it is preferable that a polyimide tape is used as a dielectric material, and the solder mask is a liquid solder mask ink of an infrared type (IR type) made of photoimaging or polyimide. laser or plasma etching using ink and insulating materials, silk screen printing, coating using metal mask, injection and dispensing It is preferable to use any one of the coating method using and the coating method by the dotting method.

솔더마스크(14)가 장착된 리드프레임(10)의 와이어본딩 영역(A)과 솔더 영역(B)에 걸쳐 니켈/파라듐, 니켈/금도금, 니켈/금-은합금 도금으로서 전면을 도금처리한다(S40 참조).The entire surface is plated with nickel / paradium, nickel / gold plating, and nickel / gold-silver alloy plating over the wire bonding area A and the solder area B of the lead frame 10 on which the solder mask 14 is mounted. (See S40).

솔더마스킹된 리드프레임(12)의 앞면의 패드(11)에 반도체칩(15)을 장착하고, 반도체칩(15)과 리드프레임(10)의 전기적 연결을 위하여 골드와이어(16)로서 반도체칩(15)과 리드프레임(10)의 이너리드(12a)를 와이어본딩 처리한다(S50 참조).The semiconductor chip 15 is mounted on the pad 11 on the front surface of the solder masked lead frame 12, and the semiconductor chip 15 is formed as a gold wire 16 for electrical connection between the semiconductor chip 15 and the lead frame 10. 15) and the inner lead 12a of the lead frame 10 are wire bonded (see S50).

반도체칩(15) 또는 골드와이어(16)등이 외부로 노출되는 것을 방지하여 리드프레임(10)의 와이어본딩 영역(A)을 외부에서 가해지는 충격, 부식등으로부터 보호할 수 있도록 와이어본딩 영역(A)을 포함한 솔더마스크(14)가 시작하는 부위까지에폭시수지에 의해 부분적으로 봉지(encapsulation)하는 작업을 실시한다(S60 참조).The wire bonding region is formed to prevent the semiconductor chip 15 or the gold wire 16 from being exposed to the outside so as to protect the wire bonding region A of the lead frame 10 from external impact or corrosion. Partly encapsulation is performed by the epoxy resin to the starting point of the solder mask 14 including A) (see S60).

리드프레임(10)의 단품패키지를 마무리작업하여 완성하는 트리밍(trimming)작업과 아웃리드(12b)의 포밍(forming)작업을 실시한다(S70 참조).A trimming operation for finishing the finished single package of the lead frame 10 and a forming operation of the outlead 12b are performed (see S70).

다음, 단품패키지를 인쇄회로기판(mother board)에 장착하는 후속공정으로 운반되는 것이다.Next, the single package is transported to a subsequent process of mounting on a mother board.

이상에서와 같이, 바람직한 실시예에 의하면 아래와 같은 이점을 갖는다.As mentioned above, according to a preferable embodiment, it has the following advantages.

금속재질의 리드프레임에 솔더마스크 또는 절연소재를 장착하여 와이어본딩후 본딩 영역을 보호하기 위한 별도의 몰딩작업이 불필요하게 되어 보다 얇은 패키지(thin package)를 제작가능하며, 이로 인한 작업공수 단축으로 제작비용을 현저하게 절감할 수 있다.It is possible to manufacture thin package by attaching solder mask or insulating material to metal lead frame, so that no separate molding work is needed to protect the bonding area after wire bonding. The cost can be significantly reduced.

또한, 리드프레임의 패턴성형후 이송라인에서 리드의 보호와 다운셋시의 안정성을 확보하기 위하여 테이핑하는 작업공정이 불필요하여 원가비용 및 제작비용을 절감할 수 있다.In addition, in order to ensure the protection of the lead in the transfer line after pattern molding of the lead frame and to ensure the stability during downset, a tapering process is unnecessary, thereby reducing cost and manufacturing costs.

또한, 솔더마스킹된 리드프레임의 마스킹부위를 후도금으로서 전면도금함에 따라 아웃리드부를 솔더도금하는 작업공정이 불필요하여 작업공수 단축으로 인해 제작비용 및 폐수처리비용을 절감할 수 있도록 한 이점을 갖는다.In addition, since the front surface of the masking portion of the solder masked lead frame is plated as a front plate, a work process for soldering outlead parts is unnecessary, thereby reducing manufacturing cost and wastewater treatment cost due to shortening of labor time.

Claims (5)

반도체칩이 장착되는 패드, 리드 및 타이바로서 방산형의 형태를 갖도록 패턴화되는 금속재질의 리드프레임;A lead frame made of a metal material patterned to have a dissipation type as pads, leads, and tie bars on which semiconductor chips are mounted; 상기 패턴화된 리드프레임이 이송라인에서 이송시 리드가 손상되는 것을 방지할 수 있도록 와이어본딩 영역의 외곽부터 패키징라인까지의 리드에 장착되는 절연소재의 솔더마스크층;A solder mask layer of an insulating material mounted on a lead from an outer side of a wire bonding area to a packaging line to prevent the lead from being damaged when the patterned lead frame is transferred in a transfer line; 솔더마스크가 장착된 리드프레임의 와이어본딩 영역과 솔더 영역에 전면도금되는 도금층;A plated layer overlying the wire bonding region and the solder region of the lead frame on which the solder mask is mounted; 상기 패드에 탑제되는 반도체칩과 상기 리드프레임의 이너리드를 와이어본딩시켜 전기적으로 도통가능하게 연결하는 골드와이어; 및Gold wires electrically connected to each other by wire-bonding the semiconductor chip mounted on the pad and the inner lead of the lead frame; And 상기 반도체칩과 골드와이어의 노출을 방지하여 상기 와이어본딩 영역을 보호할 수 있도록 봉지하는 봉지부를 구비하는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임.And a sealing part encapsulating the semiconductor chip and the gold wire so as to protect the wire bonding region. 제 1 항에 있어서, 상기 솔더마스크의 절연소재로서 폴리이마이드 테이프, 적외선 타입의 리퀴드 솔더마스크 잉크, 포토이메이지어블 솔더마스크 및 절연물질중 어느 하나가 사용되는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임.The solder mask-mounted lead according to claim 1, wherein any one of polyimide tape, infrared type liquid solder mask ink, photoimatable solder mask, and an insulating material is used as the insulating material of the solder mask. frame. 제 1 항에 있어서, 상기 도금층은 니켈/파라듐, 니켈/금도금, 니켈/금-은합금도금중 어느 하나를 선택하여 도금되는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임.The lead frame according to claim 1, wherein the plating layer is plated by selecting any one of nickel / palladium, nickel / gold plating, and nickel / gold-silver alloy plating. 반도체칩이 장착되는 패드, 리드 및 타이바로서 방산형의 형태를 갖도록 금속재질의 리드프레임을 패턴화시키는 단계;Patterning a lead frame made of metal so as to have a dissipation type as pads, leads, and tie bars on which semiconductor chips are mounted; 상기 패턴화된 리드프레임이 이송라인에서 이송시 리드가 손상되는 것을 방지할 수 있도록 와이어본딩 영역의 외곽부터 패키징라인까지의 리드에 솔더마스크를 장착하는 단계;Mounting a solder mask on a lead from an outer side of a wire bonding area to a packaging line to prevent the lead from being damaged when the patterned lead frame is transferred in a transfer line; 솔더마스크층이 장착된 리드프레임의 와이어본딩 영역과 솔더 영역에 걸쳐 전면도금하는 단계;Front plating the wire bonding area and the solder area of the lead frame on which the solder mask layer is mounted; 상기 패드에 탑제되는 반도체칩과 상기 리드프레임의 이너리드를 골드와이어로서 전기적으로 연결되도록 와어어본딩시키는 단계;Wire-bonding the semiconductor chip mounted on the pad and the inner lead of the lead frame to be electrically connected as gold wires; 상기 반도체칩과 골드와이어의 노출을 방지하여 상기 와이어본딩 영역을 봉지하여 보호할 수 있도록 봉지부를 성형하는 단계; 및Forming an encapsulation part to prevent the semiconductor chip and the gold wire from being exposed to encapsulate and protect the wire bonding region; And 단품패키지의 트리밍과 상기 리드프레임의 아웃리드를 포밍하는 단계를 포함하는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임의 제조방법.The method of manufacturing a lead frame with a solder mask, characterized in that it comprises the step of trimming the single-piece package and the out lead of the lead frame. 제 4 항에 있어서, 상기 솔더마스크층은;The method of claim 4, wherein the solder mask layer; 포토이메이징공법, 폴리이마이드를 소재로 하는 적외선 타입의 리퀴드솔더마스크 잉크 및 절연물질등을 사용한 레이저가공법, 플라즈마 에칭방식, 실크스크린프린팅, 메탈마스크를 이용한 도포법, 분사 및 투여법을 이용한 도포법 및 정묘법에 의한 도포법중 어느 하나를 선택하여 장착되는 것을 특징으로 하는 솔더마스크가 장착된 리드프레임의 제조방법.Photo-imaging method, laser processing method using infrared type liquid solder mask ink and insulating material made of polyimide, plasma etching method, silk screen printing, coating method using metal mask, spray method and spray method A method of manufacturing a lead frame with a solder mask, characterized in that any one of the coating method by the drawing method is selected and mounted.
KR1020000061195A 2000-10-18 2000-10-18 solder mask or dielectric materials coated lead frame and manufacturing method KR100342403B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170004448A (en) * 2015-07-02 2017-01-11 주식회사 에스에프에이반도체 manufacturing method of semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170004448A (en) * 2015-07-02 2017-01-11 주식회사 에스에프에이반도체 manufacturing method of semiconductor package

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