JPH0210859A - Semiconductor lead frame - Google Patents
Semiconductor lead frameInfo
- Publication number
- JPH0210859A JPH0210859A JP16201588A JP16201588A JPH0210859A JP H0210859 A JPH0210859 A JP H0210859A JP 16201588 A JP16201588 A JP 16201588A JP 16201588 A JP16201588 A JP 16201588A JP H0210859 A JPH0210859 A JP H0210859A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- lead
- layer
- solder
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000007747 plating Methods 0.000 claims abstract description 53
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910001174 tin-lead alloy Inorganic materials 0.000 claims abstract description 18
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 238000004080 punching Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 48
- 229910000510 noble metal Inorganic materials 0.000 abstract description 5
- 239000011347 resin Substances 0.000 description 18
- 229920005989 resin Polymers 0.000 description 18
- 239000000463 material Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 239000000956 alloy Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 235000012771 pancakes Nutrition 0.000 description 2
- 239000000088 plastic resin Substances 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- DOBRDRYODQBAMW-UHFFFAOYSA-N copper(i) cyanide Chemical compound [Cu+].N#[C-] DOBRDRYODQBAMW-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910000597 tin-copper alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体用リードフレームに関し、特に、リード
フレームの品質を向上して半導体装置の信頬性を向上し
た半導体用リードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for semiconductors, and more particularly to a lead frame for semiconductors that improves the quality of the lead frame and improves the reliability of a semiconductor device.
一般にｒｃパッケージを製造する場合、素子固定部、イ
ンナーリード部、アウターリード部、外枠等よりなるリ
ードフレームを用いて行われている。これは第４図に示
すように、ＩＣチップ固定部７上にＩＣチップ１６をチ
ップボンディングした後、ＩＣチップ１６とインナーリ
ード５の先端部６のＡｇめっき１Ｊ１２をＡｕ、ＡＩ、
Ｃｕ等の極細線１５でワイヤボンディングする。これは
、次の理由による。即ち、リードフレームは銅条（ＣＡ
１９４ 、Ｃ５０５、リン青銅等）、鉄条（４２合金、
コバール、ステンレス等）等の金属基体から形成されて
おり、この金属基体のままではＡｕ線等のワイヤボンデ
ィングが困難もしくは不可能に近くなるため、ボンディ
ングする部分のみにボンディング性の良い貴金属（Ａｇ
層１２）を部分的にめっきしている。このように、■Ｃ
チップ１６とインナーリード５の先端部６がワイヤボン
ディングされた後、第５図に示すように、プラスチック
樹脂１８でモールドされる。この後、更に半導体装置（
ＩＣパッケージ）をプリント基板等に取り付ける際の接
着性を付与するため、アウターリード部３を含む部分に
錫、半田（錫−鉛合金等）の完成品めっき層１１が設け
られ、最後に外枠部を切り落として完成品とする。Generally, when manufacturing an RC package, a lead frame including an element fixing part, an inner lead part, an outer lead part, an outer frame, etc. is used. As shown in FIG. 4, after chip-bonding the IC chip 16 onto the IC chip fixing part 7, the Ag plating 1J12 of the IC chip 16 and the tip part 6 of the inner lead 5 is changed to Au, AI,
Wire bonding is performed using a very fine wire 15 made of Cu or the like. This is due to the following reason. That is, the lead frame is made of copper strip (CA
194, C505, phosphor bronze, etc.), wire (42 alloy,
It is made of a metal base such as Kovar, stainless steel, etc., and if this metal base remains as it is, wire bonding of Au wire etc. will be difficult or almost impossible.
Layer 12) is partially plated. In this way, ■C
After the chip 16 and the tip 6 of the inner lead 5 are wire-bonded, they are molded with a plastic resin 18, as shown in FIG. After this, further semiconductor devices (
In order to provide adhesive properties when attaching the IC package to a printed circuit board, etc., a finished product plating layer 11 of tin or solder (tin-lead alloy, etc.) is provided on the portion including the outer lead portion 3, and finally the outer frame Cut off the parts to make the finished product.
しかし、このＩＣパッケージの製造方法ではプラスチッ
ク樹脂でモールドした後に行う完成品めっき工程の前処
理として、酸、アルカリ等を使用するため、樹脂と金属
リード材の隙間に酸等が侵入し、これによって塩の残留
等が発生する。また、熔融めっき時には２００℃を越え
る熱衝撃を与えるため、樹脂封止材にクランクが発生す
る等の種々の問題が提起されている。このため、この完
成品めっき工程がＩＣパッケージの信頼性を低下させる
要因となっている。また、組立て後、めっきメーカー等
へ移動するため、作業工程が複雑となり、コストアンプ
の原因となる。However, in this IC package manufacturing method, acids, alkalis, etc. are used as a pretreatment for the plating process of the finished product after molding with plastic resin, so acids, etc. enter the gap between the resin and the metal lead material, and this causes Residual salt etc. will occur. Furthermore, since a thermal shock exceeding 200° C. is applied during melt plating, various problems have been raised, such as the generation of cranks in the resin sealing material. Therefore, this finished product plating process is a factor that reduces the reliability of the IC package. Furthermore, after assembly, the work is moved to a plating manufacturer, etc., which complicates the work process and increases costs.
そこで、このような問題を解決するため、特開昭５１−
１１５７７５号公報に示されるものが提案されている。Therefore, in order to solve such problems,
The one shown in Japanese Patent No. 115775 has been proposed.
これはボンディング性の良い貴金属（Ａｇ層１２）を部
分的に設けたリードフレームに予めアウターリード部に
錫−鉛合金層を設けたものである。また、この他に特開
昭５８−５２８６０号公報に示されるように、アウタリ
ート部の半田付は性を向−トするため、アウターリード
部に鉛層と錫層の２層を設ける方法も提案されている。This is a lead frame in which a noble metal (Ag layer 12) with good bonding properties is partially provided, and a tin-lead alloy layer is previously provided on the outer lead portion. In addition, as shown in Japanese Unexamined Patent Publication No. 58-52860, a method of providing two layers, a lead layer and a tin layer, on the outer lead part was also proposed in order to improve the soldering properties of the outer lead part. has been done.
〔発明が解決しようとする課題］
しかし、従来の半導体用リードフレームによると、以下
の問題点を有している。[Problems to be Solved by the Invention] However, conventional lead frames for semiconductors have the following problems.
（１）特開昭５１−１１５７７５号の場合ＩＣの高集積
化および高機能化に伴いｒｃチップが大型化しており、
樹脂モールドエリアと半田めっきエリアの重なりが狭く
なっている。このため、半田めっきエリアの位置精度の
面から樹脂モールド外でリードフレーム素材が露出する
ことがあり、この露出面から鉄条の４２合金あるいはＣ
ｕ合金材の腐食が発生する恐軌がある。また、樹脂モー
ルドの前にめっき層を設けるため、金型に接する部分に
もめっき層が存在し、金型封止圧力と１８０℃に近い熱
によりこのめっき層が太き（変形し、モールド金型内に
半田が付着したり、ダムバー切断時に変形により生じる
半田パリが残るという問題もある。(1) In the case of JP-A-51-115775, RC chips are becoming larger as ICs become more highly integrated and functional.
The overlap between the resin mold area and the solder plating area is narrow. For this reason, the lead frame material may be exposed outside the resin mold due to the positional accuracy of the solder plating area.
There is a fear that corrosion of u-alloy material will occur. In addition, since a plating layer is provided before the resin mold, there is also a plating layer in the part that comes into contact with the mold, and the mold sealing pressure and heat close to 180°C cause this plating layer to thicken (deform) and mold the mold. There are also problems such as solder adhering to the inside of the mold and solder flakes remaining due to deformation when cutting the dam bar.
（２）特開昭５８−５２８６０号の場合アウターリード
部に鉛と錫の２Ｎを形成するが、インナーリード部には
貴金属めっきが施されていないため、Ａｕ線を用いたＩ
Ｃチップとインナーリード部の配線が困難である。(2) In the case of JP-A-58-52860, 2N of lead and tin is formed on the outer lead part, but since the inner lead part is not plated with noble metal, the I
Wiring between the C chip and the inner lead part is difficult.
また、樹脂モールド近傍にはリードフレーム素材が露出
する欠点がある。Another disadvantage is that the lead frame material is exposed near the resin mold.
従って、本発明の目的は半田めっき層の変形を抑え、金
型への半田付着をなくして品質を向上することができる
半導体用リードフレームを提供することである。Accordingly, an object of the present invention is to provide a semiconductor lead frame that can suppress deformation of the solder plating layer, eliminate solder adhesion to the mold, and improve quality.
本発明の他の目的は樹脂近傍でリードフレーム素材の露
出を防止し、半導体装置の信頼性を向上した半導体用リ
ードフレームを提供することである。Another object of the present invention is to provide a semiconductor lead frame that prevents the lead frame material from being exposed near the resin and improves the reliability of the semiconductor device.
本発明は以上述べた目的を実現するため、金属基板上に
３μｍ以下の厚さで錫もしくは錫−鉛合金の第１層を形
成し、かつ、アウターリード部のみ厚さが３μｍを越え
るように更に錫もしくは錫−鉛合金の第２Ｎを形成した
半導体用リードフレームを提供する。In order to achieve the above-mentioned object, the present invention forms a first layer of tin or tin-lead alloy with a thickness of 3 μm or less on a metal substrate, and has a thickness of only the outer lead portion exceeding 3 μm. Furthermore, a semiconductor lead frame is provided in which a second N layer of tin or a tin-lead alloy is formed.
即ち、本発明の半導体用リードフレームはリードフレー
ム金属基板上に３μｍ以下の厚さで錫あるいは錫−鉛合
金等の薄い半田めっき層が設けられており、更に、薄い
半田めっき層上のアウターリード部のみに合計厚が３μ
ｍを越えるように錫あるいは錫−鉛合金の厚い半田めっ
き層が設けられている。また、インナーリード先端部に
はボンディング性の良い貴金属めっき層（本実施例では
Ａｇめっき層）が設けられており、ＩＣチップとインナ
ーリード部の配線を容易にしている。薄い半田めっき層
の厚さを３μｍ以下で設けることにより樹脂封止の際、
モールド金型による錫あるいは錫−銅合金等の半田めっ
き層の変形を抑えることができ、これによりモールド金
型への半田の付着および半田ばりの発生がなくなる。ま
た、インナーリード部にも半田めっき層が設けられてい
るため、樹脂封止の際、樹脂近傍でリードフレーム素材
が露出するのを防ぐことができる。厚い半田めっき層の
厚さを３μｍを越えるようにすると、組立工程での熱履
歴を経た後も良好な半田濡れ性を確保することができる
。また、必要に応じて、金属基体に予め銅めっき層を０
．５μｍ程度設けてから薄い半田めっき層および厚い半
田めっき層を設けても良く、これによって金属基体と半
田めっき層の密着性を向上させることができる。That is, in the semiconductor lead frame of the present invention, a thin solder plating layer such as tin or tin-lead alloy is provided on the lead frame metal substrate with a thickness of 3 μm or less, and an outer lead on the thin solder plating layer is provided. The total thickness is 3μ only in the section.
A thick solder plating layer of tin or tin-lead alloy is provided so as to exceed m. In addition, a noble metal plating layer (Ag plating layer in this embodiment) with good bonding properties is provided at the tip of the inner lead to facilitate wiring between the IC chip and the inner lead. By providing a thin solder plating layer with a thickness of 3 μm or less, during resin sealing,
Deformation of the solder plating layer of tin or tin-copper alloy due to the molding die can be suppressed, thereby eliminating adhesion of solder to the molding die and generation of solder burrs. Furthermore, since the inner lead portion is also provided with a solder plating layer, it is possible to prevent the lead frame material from being exposed near the resin during resin sealing. When the thickness of the thick solder plating layer exceeds 3 μm, good solder wettability can be ensured even after the thermal history in the assembly process. In addition, if necessary, a copper plating layer may be applied to the metal substrate in advance.
．． A thin solder plating layer and a thick solder plating layer may be provided after a thickness of about 5 μm, and thereby the adhesion between the metal substrate and the solder plating layer can be improved.
以下、本発明の半導体用リードフレームを詳細に説明す
る。Hereinafter, the semiconductor lead frame of the present invention will be explained in detail.
第１図（ａ）、（ｂｌは本発明の一実施例を示し、４２
合金を素材とした金属条をプレス加工によって打ち抜く
ことにより、リードフレーム外枠２、アウターリード部
３、ダムバー４、インナーリード部５、ＩＣチップ固定
部７およびパイロットホール８を所定パターンで形成し
てリードフレーム１用の金属基体とする。FIG. 1(a), (bl shows one embodiment of the present invention, 42
A lead frame outer frame 2, an outer lead part 3, a dam bar 4, an inner lead part 5, an IC chip fixing part 7, and a pilot hole 8 are formed in a predetermined pattern by punching a metal strip made of an alloy by press working. A metal base for lead frame 1.
この金属基体上には錫が７０％混入した錫−鉛合金の薄
い半田めっき層１０が２μｍの厚さで設けられており、
更に、薄い半田めっき層１０上のアウターリード部３の
みに同じく錫が７０％混入した錫−鉛合金の厚い半田め
っきＪｉｉｌｌが６μｍの厚さで設けられている。また
、インナーリード先端部６にはＡｇめっきＦＪ１２が６
μｍの１７さて設けられており、ＩＣチップ（図示せず
）との配線接続時にワイヤ接続が容易に行えるようにな
ついる。これは特にＡｇめっき層に限定するものではな
く、ボンディング性の良い貴金属めっきであれば良く、
Ａｕめっき層でも良い。On this metal base, a thin solder plating layer 10 of a tin-lead alloy containing 70% tin is provided with a thickness of 2 μm.
Further, a thick solder plating made of a tin-lead alloy containing 70% tin is provided only on the outer lead portion 3 on the thin solder plating layer 10 to a thickness of 6 μm. In addition, the inner lead tip 6 is coated with Ag plating FJ12.
17 .mu.m is provided to facilitate wire connection when wiring to an IC chip (not shown). This is not particularly limited to the Ag plating layer, but any noble metal plating with good bonding properties may be used.
An Au plating layer may also be used.
第２図はこのリードフレームを用いてＩＣパンケージに
組立てた状態を示し、ＩＣチップ固定部７上にＡｇペー
スト１７を介してＩＣチップ１６が設けられており、こ
のＩＣチップ１６とインナーリード先端部６上のＡｇめ
っき層１２とがＡｕワイヤ１５によってワイヤボンディ
ングされている。また、厚い半田めっき層１１０近くま
でモールド樹脂１８が施されており、ＩＣチップ１６等
がその内部で樹脂封止されている。外枠部２やダムバー
４は樹脂封止の後、切断される。FIG. 2 shows a state in which this lead frame is assembled into an IC pancake. An IC chip 16 is provided on the IC chip fixing part 7 via Ag paste 17, and this IC chip 16 and the tip of the inner lead The Ag plating layer 12 on the top 6 is wire-bonded with an Au wire 15 . Furthermore, a molding resin 18 is applied up to the vicinity of the thick solder plating layer 110, and the IC chip 16 and the like are sealed with the resin inside. After the outer frame portion 2 and the dam bar 4 are sealed with resin, they are cut.
このような半導体リードフレームはアウターリード部３
以外に３μｍ以下の厚さで薄い半田めっき層１０が設け
られているため、樹脂封止の際、モールド金型の内部で
は薄い半田めっき層１０の部分でリードフレーム１を支
持すれば良いので薄い半田めっきＮｉ１ｌが変形するこ
ともなく、これによって金型へのめっきの付着がなくな
り、また、半田パリの発生を防ぐことができる。また、
アウターリード部３は厚さ３μｍを越えるように厚い半
田めっき層１１が設けられているため、組立工程での熱
履歴を受けても良好な半田濡れ性を確保することができ
る。このことは、後述する実験結果で明らかとなってい
る。更に、インナーリード部５にも半田めっきＮ１０が
設けられているため、樹脂近傍からリードフレーム素材
が露出することがない。In such a semiconductor lead frame, the outer lead portion 3
In addition, since a thin solder plating layer 10 with a thickness of 3 μm or less is provided, the lead frame 1 only needs to be supported by the thin solder plating layer 10 inside the mold during resin sealing. The solder plating Ni1l is not deformed, thereby eliminating adhesion of the plating to the mold and preventing the occurrence of solder flakes. Also,
Since the outer lead portion 3 is provided with a thick solder plating layer 11 having a thickness exceeding 3 μm, good solder wettability can be ensured even when subjected to heat history during the assembly process. This has become clear from the experimental results described below. Furthermore, since the inner lead portion 5 is also provided with solder plating N10, the lead frame material is not exposed from the vicinity of the resin.
第３図は本発明の第２の実施例を示し、プレス加工によ
って打ち抜いたリードフレーム１に所定の前処理を施し
た後、シアン化銅めっき浴によって０．５μｍの銅めっ
きＮ１３を設けたものであり、この後、厚さ２μｍの錫
−鉛合金の薄い半田めっき層１０を設け、更にアウター
リード部３のみに厚さ６μｍの錫−鉛合金の厚い半田め
っき層１１を設ける。この両半田めっき層１０．１１の
形成前に銅めっき層１３を設けることによって薄い半田
めっきＪＷＩＯと金属基体との密着性を向上させること
ができる。FIG. 3 shows a second embodiment of the present invention, in which a lead frame 1 punched out by press processing is subjected to a predetermined pretreatment, and then copper plating N13 of 0.5 μm is provided in a copper cyanide plating bath. After this, a thin solder plating layer 10 of a tin-lead alloy with a thickness of 2 μm is provided, and a thick solder plating layer 11 of a tin-lead alloy with a thickness of 6 μm is further provided only on the outer lead portion 3. By providing the copper plating layer 13 before forming both solder plating layers 10 and 11, it is possible to improve the adhesion between the thin solder plating JWIO and the metal substrate.
次表は以上述べた第１および第２の実施例および従来の
半導体用リードフレームの実験結果を示し、半田めっき
厚と、モールド金型への半田付着およびパッケージ耐湿
性との関係を表す。The following table shows the experimental results of the first and second embodiments and conventional semiconductor lead frames described above, and shows the relationship between the solder plating thickness, solder adhesion to the mold, and package moisture resistance.
（１１モ一ルド金型半田付着
半田層の融点１８３℃以下の１７５℃でモールドした場
合に金型への半田付着の発生の有無で判定を行う。(11 Molded Mold Solder Adhesion Judgment is made based on the presence or absence of solder adhesion to the mold when molding is performed at 175°C, which is below the melting point of the solder layer, 183°C.
○：半田イ」着なし ×：半田付着有り（２）パッケ
ージ耐湿性
ＩＣパンケージ完成後、１２１’Ｃ２気圧飽和水蒸気下
で耐湿性を評価する。○: No solder adhesion ×: Solder adhesion (2) Package moisture resistance After completing the IC pancake, moisture resistance was evaluated under saturated steam at 121'C2 atmospheres.
○： ２００ ｈｒ以上合格
Ｘ ： ２００ ｈｒ以下で腐食発生
以上の結果から明らかなように、従来例と比較して完成
品めっきを無くすことにより半導体の耐湿性を大幅に向
上することができることが判る。また、樹脂封止の際、
金型付着によるトラブルがなくなり、品質を向上させる
こともできる。○: Passed for 200 hr or more. . Also, when sealing with resin,
Problems caused by mold adhesion are eliminated, and quality can also be improved.
以上説明した通り、本発明の半導体用リードフレームに
よると、金属基板上に３μｍ以下の厚さで錫もしくは錫
−鉛合金の第１層を形成し、アウターリード部のみ厚さ
が３μｍ以上となるように更に錫もしくは錫−鉛合金の
第２層を形成したため、樹脂封止の際、モールド金型に
よる半田めっきの変形を抑え、モールド金型内への半田
付着をなくして品質を向上することができる。また、樹
脂近傍でリードフレーム素材の露出を防止し、半導体装
置の信顧性を向上することができる。As explained above, according to the semiconductor lead frame of the present invention, the first layer of tin or tin-lead alloy is formed on the metal substrate with a thickness of 3 μm or less, and only the outer lead portion has a thickness of 3 μm or more. In addition, since a second layer of tin or tin-lead alloy is formed, the deformation of the solder plating caused by the mold during resin sealing is suppressed, and the quality is improved by eliminating solder adhesion inside the mold. I can do it. Further, exposure of the lead frame material near the resin can be prevented, and reliability of the semiconductor device can be improved.
第１図（ａｌ、（ｂｌは本発明の一実施例を示し、（ａ
）はその平面図、Ｔｂ）は側面図、第２図は本発明のリ
ードフレームを用いた組立て状態を示す説明図、第３図
は本発明の第２の実施例を示す説明図、第４図および第
５図は従来の半導体用リードフレームを示す断面図。
符号の説明
１−・−・・−−−−一半導体用リードフレーム２−−
−−−−−−−−−リードフレーム外枠３−・・−−−
−−アウトリード部
４・−−−一一一−−−−−ダムバーFIG. 1 (al, (bl) shows an embodiment of the present invention, (a
) is a plan view thereof, Tb) is a side view, FIG. 2 is an explanatory diagram showing an assembled state using the lead frame of the present invention, FIG. 3 is an explanatory diagram showing a second embodiment of the present invention, FIG. 5 is a sectional view showing a conventional semiconductor lead frame. Explanation of symbols 1--------1 lead frame for semiconductor 2--
−−−−−−−−−Lead frame outer frame 3−・・−−−
--- Out lead part 4 --- 111 --- Dam bar
Claims (2)
ウターリード部、および素子固定部等を形成された金属
基板によって構成された半導体用リードフレームにおい
て、 前記金属基板の全面に３μｍ以下の厚さで 形成された錫もしくは錫−鉛合金の第１のめっき層と、
前記アウターリード部のみに前記第１層との合計層で３
μｍ以上の厚さで形成された錫もしくは錫−鉛合金の第
２のめっき層を有することを特徴とする半導体用リード
フレーム。(1) In a semiconductor lead frame constituted by a metal substrate on which an outer frame, an inner lead portion, an outer lead portion, an element fixing portion, etc. are formed by punching, a thickness of 3 μm or less is provided on the entire surface of the metal substrate. A first plating layer of tin or tin-lead alloy formed;
The total number of layers including the first layer is 3 in the outer lead portion only.
A semiconductor lead frame characterized by having a second plating layer of tin or tin-lead alloy formed with a thickness of μm or more.
て銅めっき層が形成されている請求項第１項記載の半導
体用リードフレーム。(2) The semiconductor lead frame according to claim 1, wherein a copper plating layer is formed on the entire surface of the metal substrate prior to forming the first layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63162015A JP2503595B2 (en) | 1988-06-29 | 1988-06-29 | Semiconductor lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63162015A JP2503595B2 (en) | 1988-06-29 | 1988-06-29 | Semiconductor lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0210859A true JPH0210859A (en) | 1990-01-16 |
| JP2503595B2 JP2503595B2 (en) | 1996-06-05 |
Family
ID=15746429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63162015A Expired - Lifetime JP2503595B2 (en) | 1988-06-29 | 1988-06-29 | Semiconductor lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2503595B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH034554A (en) * | 1989-06-01 | 1991-01-10 | Shinko Electric Ind Co Ltd | Lead frame |
| JPH04165659A (en) * | 1990-10-30 | 1992-06-11 | Nec Corp | Lead frame for resin-sealed semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62105457A (en) * | 1985-11-01 | 1987-05-15 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-06-29 JP JP63162015A patent/JP2503595B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62105457A (en) * | 1985-11-01 | 1987-05-15 | Hitachi Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH034554A (en) * | 1989-06-01 | 1991-01-10 | Shinko Electric Ind Co Ltd | Lead frame |
| JPH04165659A (en) * | 1990-10-30 | 1992-06-11 | Nec Corp | Lead frame for resin-sealed semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2503595B2 (en) | 1996-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6194777B1 (en) | Leadframes with selective palladium plating | |
| US7368328B2 (en) | Semiconductor device having post-mold nickel/palladium/gold plated leads | |
| KR100548091B1 (en) | Semiconductor device | |
| US8435867B2 (en) | Method of manufacturing semiconductor device and method of manufacturing electronic device | |
| TWI291756B (en) | Low cost lead-free preplated leadframe having improved adhesion and solderability | |
| US6828660B2 (en) | Semiconductor device with double nickel-plated leadframe | |
| KR20080034081A (en) | Semiconductor device and manufacturing method of the same | |
| JP2001230360A (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| JP2989406B2 (en) | Preplated frame for semiconductor device and method of manufacturing the same | |
| US20040183166A1 (en) | Preplated leadframe without precious metal | |
| JPH0210859A (en) | Semiconductor lead frame | |
| JPH0216761A (en) | Manufacture of lead frame and semiconductor device using same | |
| JPH02222567A (en) | Lead frame | |
| KR100342403B1 (en) | solder mask or dielectric materials coated lead frame and manufacturing method | |
| EP0380176A1 (en) | method for producing a solderable finish on metal frames for semiconductors | |
| KR100230751B1 (en) | Semiconductor package manufacturing method | |
| JPH01223755A (en) | Lead frame for semiconductor device | |
| KR20000009009A (en) | Lead frame and semiconductor package using thereof | |
| JP4668729B2 (en) | Manufacturing method of semiconductor device | |
| JPS6347343B2 (en) | ||
| KR20070015164A (en) | External palladium plating structure of semiconductor component and semiconductor device manufacturing method | |
| JP2000061684A (en) | JOINING MATERIAL IN PLACE OF Pb AND MOUNTED ELECTRONIC PARTS ALLOY-PLATED FOR MOUNTING-JOINING WITH THE SAME | |
| KR19990030504A (en) | Leadframe for Integrated Circuit Package and Manufacturing Method Thereof | |
| JP2003243596A (en) | Lead frame, semiconductor device and manufacturing method for semiconductor device | |
| JPH02125631A (en) | Semiconductor device, its manufacture, and wire bonding apparatus used therein |