KR20020028491A - Method for forming a pattern of a semiconductor device - Google Patents

Method for forming a pattern of a semiconductor device Download PDF

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Publication number
KR20020028491A
KR20020028491A KR1020000059514A KR20000059514A KR20020028491A KR 20020028491 A KR20020028491 A KR 20020028491A KR 1020000059514 A KR1020000059514 A KR 1020000059514A KR 20000059514 A KR20000059514 A KR 20000059514A KR 20020028491 A KR20020028491 A KR 20020028491A
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South Korea
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hard mask
pattern
conductive layer
forming
photoresist
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KR1020000059514A
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Korean (ko)
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문정언
이금범
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000059514A priority Critical patent/KR20020028491A/en
Publication of KR20020028491A publication Critical patent/KR20020028491A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

PURPOSE: A method for fabricating a pattern of a semiconductor device is provided to prevent a defect caused by an electrical connection even when the interval between patterns is very narrow, by making a hard mask etched to have the sidewall of a vertical type and by preventing a loss of a photoresist layer so that the conductive layer pattern have an excellent type. CONSTITUTION: After the hard mask(4) is formed on the conductive layer(3) while the conductive layer is formed on a semiconductor substrate(1), a photoresist layer pattern is formed on the hard mask. The hard mask in an exposed portion is etched by using the photoresist layer pattern as a mask, and a polymer layer is formed on the photoresist layer pattern. After the exposed portion of the conductive layer is etched to form a conductive layer pattern, the remaining polymer layer and photoresist layer pattern are sequentially eliminated.

Description

반도체 소자의 패턴 형성 방법 {Method for forming a pattern of a semiconductor device}Method for forming a pattern of a semiconductor device

본 발명은 반도체 소자의 패턴 형성 방법에 관한 것으로, 특히, 배선 또는 전극을 형성하는 과정에서 측벽의 형태가 수직하게 형성될 수 있도록 한 반도체 소자의 패턴 형성 방법에 관한 것이다.The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a pattern of a semiconductor device such that the sidewalls may be formed vertically in the process of forming a wiring or an electrode.

일반적으로 반도체 소자의 집적도가 증가됨에 따라 패턴의 크기 및 패턴간의간격이 더욱 감소된다. 그러므로 디램(DRAM)과 같은 메모리 소자의 제조 공정에서 비트라인과 전하저장전극 사이의 간격이 미세화되기 때문에 패터닝 과정에서 발생되는 불량에 의해 전기적인 접속이 발생될 수 있다. 그래서 비트라인과 전하저장전극의 전기적인 접속이 방지되도록 비트라인의 양측부에 스페이서를 형성하며, 스페이서를 이용하여 자기정렬식각(Self Align Etch) 방식으로 콘택홀을 형성하므로써 전하저장전극의 형성이 용이해지도록 한다.In general, as the degree of integration of semiconductor devices increases, the size of the pattern and the spacing between the patterns are further reduced. Therefore, since the gap between the bit line and the charge storage electrode is miniaturized in the manufacturing process of a memory device such as DRAM, electrical connection may be generated due to a defect generated during the patterning process. Therefore, spacers are formed at both sides of the bit line to prevent electrical connection between the bit line and the charge storage electrode, and the formation of the charge storage electrode is formed by forming contact holes using a self alignment etching method using the spacer. Make it easy.

그런데 종래의 방법으로 비트라인을 형성할 경우 패터닝을 위한 식각 과정에서 폴리리실리콘과 텅스텐 실리사이드로 이루어진 비트라인상에 형성된 하드 마스크의 상부 모서리가 돌출되는 현상(Top Notch)이 발생되거나 비트라인의 측벽이 불균일하게 예를들어, 경사지게 패터닝되는 문제점이 발생된다. 이러한 현상은 하드 마스크로 사용되는 질화막의 막질과 식각 선택비에 의해 발생되는데, 이에 의해 비트라인과 전하저장전극간의 전기적인 접속이 발생되거나 후속 공정의 진행이 어려워진다.However, when the bit line is formed by the conventional method, a top notch of the hard mask formed on the bit line formed of polysilicon and tungsten silicide occurs in the etching process for patterning, or a sidewall of the bit line is formed. This non-uniformity, for example, causes the problem of patterning obliquely. This phenomenon is caused by the film quality and etching selectivity of the nitride film used as a hard mask, which causes an electrical connection between the bit line and the charge storage electrode or makes it difficult to proceed with the subsequent process.

따라서 본 발명은 도전층상에 감광막과의 식각 선택비가 높은 BCB를 이용하여 하드 마스크를 형성하고 식각 과정에서 감광막의 표면에 폴리머층이 형성되도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 패턴 형성 방법을 제공하는 데 그 목적이 있다.Therefore, the present invention can solve the above-mentioned disadvantages by forming a hard mask using BCB having a high etching selectivity with the photoresist on the conductive layer and forming a polymer layer on the surface of the photoresist during the etching process. The purpose is to provide.

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 패턴 형성 방법을 설명하기 위한 단면도.1 to 4 are cross-sectional views illustrating a method for forming a pattern of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

1: 반도체 기판2: 절연막1: semiconductor substrate 2: insulating film

3: 도전층4: 하드 마스크3: conductive layer 4: hard mask

5: 감광막 패턴6: 폴리머층5: photosensitive film pattern 6: polymer layer

본 발명에 따른 반도체 소자의 패턴 형성 방법은 반도체 기판상에 도전층이 형성된 상태에서 도전층상에 산화물 성분의 하드 마스크를 형성한 후 하드 마스크상에 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 이용하여 노출된 부분의 하드 마스크를 식각하되, 감광막 패턴의 표면에 폴리머층이 생성되도록 하는 단계와, 도전층의 노출된 부분을 식각하여 도전층 패턴을 형성한 후 잔류된 폴리머층 및 감광막 패턴을 순차적으로 제거하는 단계를 포함하여 이루어 진다.According to the present invention, a method of forming a pattern of a semiconductor device includes forming a hard mask of an oxide component on a conductive layer in a state where a conductive layer is formed on a semiconductor substrate, and then forming a photoresist pattern on the hard mask, and using the photoresist pattern as a mask. Etching the hard mask of the exposed portion using a polymer layer on the surface of the photoresist pattern, etching the exposed portion of the conductive layer to form a conductive layer pattern, and then removing the remaining polymer layer and the photoresist pattern It consists of removing sequentially.

상기 하드 마스크는 산화물 성분의 BCB로 형성되며, C4F8와 아르곤(Ar)을 소오스 가스로 이용한 플라즈마 식각 공정으로 식각되고, 상기 플라즈마 식각 공정시 아웃 페이져 펄스 모듈레이션 방식이 적용된다.The hard mask is formed of BCB of an oxide component, and is etched by a plasma etching process using C 4 F 8 and argon (Ar) as a source gas, and an out phaser pulse modulation method is applied during the plasma etching process.

그러면 이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Next, the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 패턴 형성 방법을 설명하기 위한 소자의 단면도이다.1 to 4 are cross-sectional views of devices for explaining a method of forming a pattern of a semiconductor device according to the present invention.

도 1은 절연막(2)이 형성된 반도체 기판(1)상에 도전층(3)이 형성된 상태에서 상기 도전층(3)을 패터닝하기 위하여 상기 도전층(3)상에 하드 마스크(4)를 형성하고 상기 하드 마스크(4)상에 감광막 패턴(5)을 형성한 상태의 단면도로서, 상기 하드 마스크(4)는 산화막 성분의 BCB(Benzo Cyclotro Butene)로 형성한다.1 shows a hard mask 4 formed on the conductive layer 3 to pattern the conductive layer 3 in a state where the conductive layer 3 is formed on the semiconductor substrate 1 on which the insulating film 2 is formed. And as a cross-sectional view of the photosensitive film pattern 5 formed on the hard mask 4, the hard mask 4 is formed of BCB (Benzo Cyclotro Butene) of the oxide film component.

도 2는 상기 감광막 패턴(5)을 마스크로 이용하여 노출된 부분의 상기 하드마스크(4)를 식각한 상태의 단면도로서, 상기 식각 공정은 C4F8와 아르곤(Ar)을 소오스 가스로 이용한 플라즈마 식각 방식으로 실시하며, 아웃 페이져 펄스 모듈레이션(Out Phase Pulse Modulation) 방식 즉, 소정의 주기를 갖는 펄스의 공급에 따라 소오스 가스가 공급되면 바이어스 전력의 공급이 중단되고, 소오스 가스의 공급이 중단되면 바이어스 전력이 공급되도록 하는 방식을 적용한다.FIG. 2 is a cross-sectional view of an exposed portion of the hard mask 4 by using the photoresist pattern 5 as a mask, and the etching process uses C 4 F 8 and argon (Ar) as a source gas. When the source gas is supplied according to the out phase pulse modulation method, that is, the supply of the pulse having a predetermined period, the supply of the bias power is stopped and the supply of the source gas is stopped. Applies a manner in which bias power is supplied.

이때, 다른 물질에 비해 식각시 측벽의 형태가 양호하게 형성되는 BCB를 사용하므로써 상기 하드 마스크(4)의 패터닝된 측벽이 수직한 형태를 갖게 된다. 또한, 아웃 페이져 펄스 모듈레이션 방식을 적용하므로써 순간적인 직류(DC) 바이어스의 증가에 의해 이온의 충돌(Ion Bambardment)이 증가되고, 중성 상태를 유지하는 가스의 분해가 발생된다. 즉, 식각 가스인 C4F8는 F2및 CF4와 같이 휘발성이 강한 가스 상태로 분리되고, 나머지 C2성분은 휘발되지 않고 상기 감광막 패턴(5)상에 잔류되어 폴리머(Polymer)층(6)을 형성하게 된다. 따라서 상기 하드 마스크(4) 측벽이 수직한 형태로 식각되고, 상기 폴리머층(6)에 의해 감광막 패턴(5)의 손실이 방지된다.At this time, the patterned sidewall of the hard mask 4 has a vertical shape by using BCB which has a better shape of the sidewalls during etching than other materials. In addition, by applying the out phaser pulse modulation method, an ion collision is increased by an instantaneous increase in DC bias, and decomposition of a gas maintaining a neutral state occurs. That is, the etching gas C 4 F 8 is separated into a highly volatile gas state such as F 2 and CF 4, and the remaining C 2 components remain on the photosensitive film pattern 5 without being volatilized to form a polymer layer ( 6) is formed. Accordingly, sidewalls of the hard mask 4 are etched vertically, and loss of the photoresist pattern 5 is prevented by the polymer layer 6.

도 3은 상기 도 2의 상태에서 상기 도전층(3)의 노출된 부분을 식각하므로써 도전층 패턴(3a)이 형성된 상태의 단면도로서, 상기 폴리머층(6)의 생성으로 인해 감광막 패턴(5)의 손실이 방지되어 도전층과의 식각 선택비가 높게 유지되고, 상기 하드 마스크(4)의 측벽이 수직한 형태로 유지되어 양호한 형태를 갖는 도전층 패턴(3a)이 형성된다.FIG. 3 is a cross-sectional view of the conductive layer pattern 3a formed by etching the exposed portion of the conductive layer 3 in the state of FIG. 2, and the photoresist pattern 5 is formed due to the formation of the polymer layer 6. Loss is prevented so that the etch selectivity with the conductive layer is kept high, and the sidewalls of the hard mask 4 are kept vertical to form a conductive layer pattern 3a having a good shape.

도 4는 잔류된 상기 폴리머층(6) 및 감광막 패턴(5)을 순차적으로 제거한 상태의 단면도이다.4 is a cross-sectional view of the polymer layer 6 and the photoresist pattern 5 that are sequentially removed.

상술한 바와 같이 본 발명은 도전층상에 감광막과의 식각 선택비가 높으며 식각시 측벽의 형태가 양호해지는 산화막 성분의 BCB를 이용하여 하드 마스크를 형성하고, 식각 과정에서 감광막의 표면에 폴리머층이 형성되도록 하므로써 하드 마스크의 측벽이 수직한 형태로 식각되고 상기 폴리머층에 의해 감광막의 손실이 방지된다. 그러므로 하드 마스크의 측벽이 수직한 형태로 식각되고, 감광막의 손실이 방지되어 도전층 패턴의 형태가 양호해지므로써 패턴간의 간격이 미세한 경우에도 전기적인 접속으로 인한 불량이 방지되며 후속 공정의 진행이 용이해 진다.As described above, in the present invention, a hard mask is formed by using BCB of an oxide component having a high etching selectivity with a photoresist layer and a good sidewall shape during etching, and a polymer layer is formed on the surface of the photoresist layer during etching. As a result, the sidewalls of the hard mask are etched vertically, and the polymer layer prevents the loss of the photoresist film. Therefore, the sidewalls of the hard mask are etched vertically, and the loss of the photoresist layer is prevented, so that the shape of the conductive layer pattern is good, thereby preventing defects due to electrical connection even when the intervals between the patterns are minute. It becomes

Claims (4)

반도체 기판상에 도전층이 형성된 상태에서 상기 도전층상에 하드 마스크를 형성한 후 상기 하드 마스크상에 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern on the hard mask after forming a hard mask on the conductive layer while the conductive layer is formed on the semiconductor substrate; 상기 감광막 패턴을 마스크로 이용하여 노출된 부분의 상기 하드 마스크를 식각하되, 상기 감광막 패턴의 표면에 폴리머층이 생성되도록 하는 단계와,Etching the hard mask of the exposed portion using the photoresist pattern as a mask, wherein a polymer layer is formed on a surface of the photoresist pattern; 상기 도전층의 노출된 부분을 식각하여 도전층 패턴을 형성한 후 잔류된 상기 폴리머층 및 감광막 패턴을 순차적으로 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 패턴 형성 방법.And etching the exposed portion of the conductive layer to form a conductive layer pattern, and then sequentially removing the remaining polymer layer and the photoresist pattern. 제 1 항에 있어서,The method of claim 1, 상기 하드 마스크는 산화물 성분의 BCB로 형성된 것을 특징으로 하는 반도체 소자의 패턴 형성 방법.And said hard mask is formed of BCB of an oxide component. 제 1 항에 있어서,The method of claim 1, 상기 하드 마스크는 C4F8와 아르곤(Ar)을 소오스 가스로 이용한 플라즈마 식각 공정으로 식각되는 것을 특징으로 하는 반도체 소자의 패턴 형성 방법.The hard mask may be etched by a plasma etching process using C 4 F 8 and argon (Ar) as a source gas. 제 3 항에 있어서,The method of claim 3, wherein 상기 플라즈마 식각 공정시 아웃 페이져 펄스 모듈레이션 방식이 적용되는 것을 특징으로 하는 반도체 소자의 패턴 형성 방법.The out phaser pulse modulation method is applied during the plasma etching process.
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