KR20020028285A - Encoder using convolutional encoding way and turbo encoding way in imt-2000 system - Google Patents

Abstract

PURPOSE: An encoder for mixing a convolutional encoding method and a turbo encoding method in an IMT(International Mobile Telecommunication)-2000 system is provided to simply perform the design and manufacture process of the encoder and minimize a manufacture cost by satisfying the convolutional encoding method and the turbo encoding method. CONSTITUTION: A control unit(100) receives speed information of input bit data from a call process control unit(1), outputs a turbo control signal in case that the speed of the input bit data is larger than a reference value, and outputs a convolutional control signal in case that the speed of the input bit data is lower than the reference value. A memory for interleaver(200) receives voice, character, and video input bit data from an RF(Radio Frequency) block(2), receives the convolutional control signal from the control unit(100), and performs a simple buffering function to output the received voice, character and video input bit data, and receives the turbo control signal from the control unit(100) and performs an interleaver memory function to output the received voice, character, and video input bit data. A convolutional encoding process unit(300) receives the convolutional control signal from the control unit(100), receives the voice, character and video input bit data from the memory for interleaver(200), performs a convolutional encoding process of the input bit data, and outputs an output signal with 4 bits(C1-C4) to an IF(Intermediate Frequency) block(3). The first turbo encoding process unit(400) receives the turbo control signal from the control unit(100), receives the voice, character and video input bit data from the RF block(2), and performs a turbo encoding process of the input bit data, outputs an output signal with 2 bits(Y0,Y1) to the IF block(3). The second encoding process unit(500) receives the turbo control signal from the control unit(100), receives the voice, character, and video input bit data interleaved through the memory for interleaver(200), performs the turbo encoding process of the input bit data, and outputs an output signal with 2 bits(Y'0,Y'1) to the IF block(3). A switch(600) receives the convolutional control signal from the control unit(100) and connects the memory for interleaver(200) to the convolutional encoding process unit(300), and receives the turbo control signal from the control unit(100) and connects the memory for interleaver(200) to the second encoding process unit(500).

Description

ENCODER USING CONVOLUTIONAL ENCODING WAY AND TURBO ENCODING WAY IN IMT-2000 SYSTEM}

The present invention relates to an encoder in which a convolutional encoding method and a turbo encoding method are mixed in an International Mobile Telecommunication (IMT) -2000 system. The present invention relates to an encoder in which a convolutional encoding method and a turbo encoding method are mixed in an IMT-2000 system that simultaneously satisfies a convolutional encoding method and a turbo encoding method when implementing an encoder of an IMT-2000 base station system.

As is well known, conventional mobile communication systems use only a convolutional encoding scheme capable of encoding only low-speed data. However, with the development of the IMT-2000 system, a turbo encoding scheme that supports speeds of more than 14400bps is needed, which allows developers to use convolutional and turbo encoders to accommodate both low and high speed data of the IMT-2000 system. We studied how to implement each system separately.

However, the above-described encoder for the IMT-2000 system has to separately install a convolutional encoder and a turbo encoder in the system, which not only complicates the structure of the IMT-2000 system but also causes a problem in that the implementation is difficult and the system cost increases. .

Accordingly, the present invention has been made to solve the conventional problems as described above, the object of the present invention is to implement an encoder suitable for the IMT-2000 system IMM-2000 system for enabling to implement a simpler and more economical encoder In the present invention, there is provided an encoder in which a convolutional encoding method and a turbo encoding method are mixed.

In order to achieve the above object, the encoder, which combines the convolutional encoding method and the turbo encoding method in the IMT-2000 system of the present invention, receives the speed information of the input bit data from the call processing controller, which is an upper block, and then inputs the input bit data. A controller for outputting a turbo control signal when the speed is greater than or equal to the reference value, and outputting a convolutional control signal when the speed is less than the reference value;

Receiving audio, text and video input bit data from the RF block, which is a preceding block, and simultaneously receiving a convolutional control signal from the controller, performing a simple buffering function and outputting it, while receiving a turbo control signal from the controller, the interleaver memory. An interleaver memory for outputting after performing a function;

When receiving the convolutional control signal from the controller and receiving audio, text and video input bit data from the interleaver memory, the 4-bit output signal of "C0, C1, C2, C3" is processed by convolutional encoding of the input bit data. A convolutional encoding processor for outputting the IF block;

After receiving the turbo control signal from the controller and receiving the audio, text and video input bit data from the RF block, which is a preceding block, turbo encoding the input bit data to output a 2-bit output signal of "Y0, Y1" to the IF. A first turbo encoding processor outputting the block;

After receiving the turbo control signal from the control unit and receiving the interleaver-processed voice, text and video input bit data through the interleaver memory, turbo encoding the input bit memory to process "Y'0, Y'1". A second turbo encoding processor configured to output a 2-bit output signal to the IF block; And

Connected to the signal output terminal of the interleaver memory and the signal input terminals of the convolutional encoding processing unit and the second turbo encoding processing unit, and upon receiving the convolutional control signal from the control unit, connects the interleaver memory and the convolutional encoding processing unit, Receiving a turbo control signal is characterized by consisting of a switch for connecting the memory for the interleaver and the second turbo encoding processing unit.

1 is a functional block diagram illustrating a configuration of an encoder in which a convolutional encoding method and a turbo encoding method are mixed in an IMT-2000 system according to an embodiment of the present invention;

FIG. 2 is a functional block diagram illustrating a detailed configuration of a convolutional encoding processing unit in an encoder mixed with a convolutional encoding method and a turbo encoding method in the IMT-2000 system according to FIG. 1;

FIG. 3 is a functional block diagram illustrating a detailed configuration of a first turbo encoding processor in an encoder in which a convolutional encoding method and a turbo encoding method are mixed in the IMT-2000 system according to FIG. 1;

FIG. 4 is a functional block diagram illustrating a detailed configuration of a second turbo encoding processing unit in an encoder in which a convolutional encoding method and a turbo encoding method are mixed in the IMT-2000 system according to FIG. 1;

FIG. 5 is a reference diagram for describing an interleaver processing process of an interleaver memory in an encoder that mixes a convolutional encoding method and a turbo encoding method in the IMT-2000 system according to FIG. 1.

<Explanation of symbols for main parts of the drawings>

100 control unit 200 interleaver memory

300: convolutional encoding processing unit 301: first D flip-flop

302: second D flip-flop 303: third D flip-flop

304: fourth D flip-flop 305: fifth D flip-flop

306: sixth D flip-flop 307: seventh D flip-flop

308: 8D flip-flop 309: 1st XOR gate

310: second XOR gate 311: third XOR gate

312: fourth XOR gate 400: first turbo encoding processor

401: 9th D flip-flop 402: 10th D flip-flop

403: 11D flip-flop 404: 5th XOR gate

405: sixth XOR gate 406: seventh XOR gate

407: Eighth XOR gate 500: Second turbo encoding processing unit

501: 12th flip-flop 502: 13th flip-flop

503: 14th flip-flop 504: 9th XOR gate

505: 10th XOR gate 506: 11th XOR gate

507: 12th XOR gate 600: switch

Hereinafter, an encoder in which a convolutional encoding method and a turbo encoding method are mixed in an IMT-2000 system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a functional block diagram of an encoder in which a convolutional encoding method and a turbo encoding method are mixed in an IMT-2000 system according to an embodiment of the present invention, and is a convolutional encoding in an IMT-2000 system according to an embodiment of the present invention. The encoder and the turbo encoding method are mixed by the controller 100, the interleaver memory 200, the convolutional encoding processor 300, the first turbo encoding processor 400, and the second turbo encoding processor ( 500 and a switch 600.

The control unit 100 receives the speed information of the input bit data from the call processing control unit 1, which is an upper block, and then transmits a turbo control signal to the interleaver memory 200 when the speed of the input bit data is equal to or greater than 14400 bps. The output signal is output to the convolutional encoding processing unit 300, the first turbo encoding processing unit 400, the second turbo encoding processing unit 500, and the switch 600, and if the convolutional control signal is less than 14400bps, the interleaver memory 200 is output. , The convolutional encoding processor 300, the first turbo encoding processor 400, the second turbo encoding processor 500, and the switch 600.

In addition, the interleaver memory 200 receives a voice, text, and video input bit data from a radio frequency (RF) block 2, which is a front end block, and simultaneously receives a convolution control signal from the controller 100. After performing the buffering function, the input bit data is output to the convolutional encoding processing unit 300, and when the turbo control signal is received from the control unit 100, the input bit data is processed by an interleaver and the second bit is processed. It serves to output to the turbo encoding processing unit 500.

On the other hand, when the convolutional encoding processing unit 300 receives the convolutional control signal from the control unit 100 and receives voice, text, and video input bit data from the interleaver memory 200, the convolutional encoding of the input bit data is performed. By processing, it outputs 4-bit output signal of "C0, C1, C2, C3" to IF (Intermediate Frequency) Block (3), 1, 2, 3, 4, 5, 6, 7 , 8D Flip-Flop (301, 302, 303, 304, 305, 306, 307, 308), and the first Exclusive OR Gate (hereinafter referred to as "XOR gate"). 309, a second XOR gate 310, a third XOR gate 311, and a fourth XOR gate 312.

In this case, the first, second, third, fourth, fifth, sixth, seventh, and eighth D flip-flops 301, 302, 303, 304, 305, 306, 307, and 308 mounted in the convolutional encoding processing unit 300 may be used. It is connected in series to the signal output terminal of the interleaver memory 200, and receives voice, text, and video input bit data in order from the interleaver memory 200, and then shifts each bit by one bit. .

In addition, the first XOR gate 309 mounted in the convolutional encoding processor 300 may include the first, second, third, fourth, fifth, sixth, seventh, eighth flip-flops 301, 302, 303, 304, and 305. , Input / output bit data of the first D flip-flop 301 and the second, third, fourth, sixth, eighth flip-flops 302, 303, 304, 306, Exclusive OR (OR) operation of the output bit data of 308 serves to output the "C0" output signal to the IF block (3).

On the other hand, the second XOR gate 310 mounted in the convolutional encoding processing unit 300 is the first, 2, 3, 4, 5, 6, 7, 8D flip-flop (301, 302, 303, 304, 305) Input / output bit data of the first D flip-flop 301 and outputs of the third, fourth, fifth, and eight D flip-flops 303, 304, 305, and 308 at each shift point of the first, second, third, fourth, third, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fifth, fourth, fifth, fourth, fifth, third, fourth, fifth, fourth, third, fourth, third, fourth, third, fourth, third, fourth, third, fourth, third, third, fourth, third and third embodiments Exclusive or arithmetic operation on the bit data serves to output the "C1" output signal to the IF block (3).

In addition, the third XOR gate 311 mounted in the convolutional encoding processor 300 may include the first, second, third, fourth, fifth, sixth, seventh and eighth flip-flops 301, 302, 303, 304, and 305. and the output bit data of 306, 307, 308) wherein the 1 D flip-flop (input bit data, and wherein the 2, 5, 7, 8 D flip-flops (302, 305, 307, 308) 301) for each shift point, of the The exclusive OR operation is performed to output the "C2" output signal to the IF block 3.

The fourth XOR gate 312 mounted in the convolutional encoding processor 300 may include the first, second, third, fourth, fifth, sixth, seventh, eighth flip-flops 301, 302, 303, 304, and 305. Input bit data of the first D flip-flop 301 and the third, fourth, five, seven, and eight D flip-flops 303, 304, 305, 307, and 308 at each shift point of the first, second, third, fourth, third, fourth, fourth, fourth, fourth, fifth, fourth, fifth, fourth, fifth, fourth, fifth, fourth, fifth, fourth, fifth, third, fourth, fifth, third, fourth, fourth, fifth, third, fourth, third, fourth, third, fourth, third, fourth, third, third, third, fourth, third, third, third, third, third, third, third, fourth, fourth, third, third, third, third, fourth, third, third, third, third, third, third, fourth, fifth, third, third, fourth, fifth, third, fourth, third, third, third, fourth, third, third, fourth, third, fourth, third, third, fourth, fourth, fifth ,,,, / ,, and third and fourth, as shown in The output bit data of the output bit data is subjected to the exclusive OR operation to output the " C3 " output signal to the IF block 3.

Meanwhile, when the first turbo encoding processor 400 receives the turbo control signal from the controller 100 and receives voice, text, and video input bit data from the RF block 2, which is a preceding block, the input bit data Turbo encoding process to output a 2-bit output signal of "Y0, Y1" to the IF block (3), the ninth, 10, 11 D flip-flop (401, 402, 403), the fifth XOR gate 404, a sixth XOR gate 405, a seventh XOR gate 406, and an eighth XOR gate 407.

In this case, the ninth, 10, and 11 D flip-flops 401, 402, and 403 mounted in the first turbo encoding processor 400 are connected in series to the signal output terminal of the RF block 2, which is a front block, respectively. After receiving the audio, text and video input bit data from the RF block 2 in order, it serves to shift each bit by one bit.

In addition, the fifth XOR gate 404 mounted in the first turbo encoding processor 400 may shift the ninth D flip-flop at every shift point of the ninth, 10, and 11D flip-flops 401, 402, and 403. The input / output bit data of the 401 and the output bit data of the eleventh D flip-flop 403 serve to output the "Y0" output signal to the IF block 3 by an exclusive OR operation.

Meanwhile, the sixth XOR gate 405 mounted in the first turbo encoding processor 400 may shift the ninth D flip-flop every shift time of the ninth, 10, and 11D flip-flops 401, 402, and 403. Outputting the " Y1 " output signal to the IF block 3 by performing an exclusive OR operation on the input / output bit data of the 401 and the output bit data of the 10 th and 11 D flip-flops 402 and 403. Do it.

In addition, a seventh XOR gate 406 mounted in the first turbo encoding processor 400 may shift the tenth and eleven D flips at every shift point of the ninth, tenth, and eleven D flip-flops 401, 402, and 403. The output bit data of the flops 402 and 403 is subjected to an exclusive OR operation, and then outputs to the eighth XOR gate 407.

In addition, an eighth XOR gate 407 mounted in the first turbo encoding processor 400 is connected to the seventh XOR gate 406 so that the ninth, 10, and 11D flip-flops 401, 402, and 403 are provided. The bit data output from the RF block 2, which is the front block, and the output bit data of the seventh XOR gate 406 at each shift point of the X-axis gate 406, and then perform an exclusive OR operation to the ninth D flip-flop 401. It plays a role of outputting.

Meanwhile, when the second turbo encoding processor 500 receives the turbo control signal from the controller 100 and receives the interleaver processed voice, text and video input bit data through the interleaver memory 200, the second turbo encoding processor 500 receives the turbo control signal. Turbo encoding the input bit memory to output a 2-bit output signal of " Y'0, Y'1 " to the IF block 3. The 12th, 13th, 14D flip-flops 501, 502, 503, a ninth XOR gate 504, a tenth XOR gate 505, an eleventh XOR gate 506, and a twelfth XOR gate 507.

In this case, the twelfth, thirteenth, and fourteenth D flip-flops 501, 502, and 503 mounted in the second turbo encoding processor 500 are connected in series to signal output terminals of the interleaver memory 200, respectively. After receiving the interleaver-processed voice, text, and video input bit data through the memory 200 in order, each bit is shifted by one bit.

In addition, a ninth XOR gate 504 mounted in the second turbo encoding processor 500 may shift the twelfth D flip-flop at every shift point of the twelfth, thirteen, and fourteenth D flip-flops 501, 502, and 503. The input / output bit data of the 501 and the output bit data of the fourteenth D flip-flop 503 are processed to perform an exclusive OR operation to output a "Y'0" output signal to the IF block 3. .

Meanwhile, the tenth XOR gate 505 mounted in the second turbo encoding processor 500 may shift the twelfth D flip-flop at every shift point of the twelfth, thirteen, and fourteenth D flip-flops 501, 502, and 503. Output the "Y'1" output signal to the IF block 3 by performing an exclusive OR operation on the input / output bit data of 501 and the output bit data of the 13th and 14D flip-flops 502 and 503. It plays a role.

In addition, an eleventh XOR gate 506 mounted in the second turbo encoding processor 500 may shift the thirteenth and fourteenth D flips at every shift point of the twelfth, thirteenth, and fourteenth D flip-flops 501, 502, and 503. The output bit data of the flops 502 and 503 is subjected to an exclusive OR operation and then output to the twelfth XOR gate 507.

A twelfth XOR gate 507 mounted in the second turbo encoding processor 500 is connected to the eleventh XOR gate 506 so that the twelfth, thirteenth, and fourteenth D flip-flops 501, 502, and 503 are connected. The bit data output from the interleaver memory 200 and the output bit data of the eleventh XOR gate 506 are subjected to an exclusive or arithmetic operation at each shift point of the shift point, and then output to the twelfth D flip-flop 507. It plays a role.

The switch 600 is connected to a signal output terminal of the interleaver memory 200 and signal input terminals of the convolutional encoding processor 300 and the second turbo encoding processor 500 to control the convolution from the controller 100. When the signal is received, the interleaver memory 200 and the convolutional encoding processor 300 are connected, and when the turbo control signal is received from the controller 100, the interleaver memory 200 and the second turbo encoding processor 500 are connected. ) Is connected.

Next, an operation process of an encoder in which the convolutional encoding method and the turbo encoding method are mixed in the IMT-2000 system having the above configuration will be described with reference to FIGS. 1, 2, 3, and 4.

First, a process of turbo encoding a voice, text, and video input bit data having a speed of 14400 bps or more will be described below.

First, the control unit 100 receives the speed information of the input bit data from the call processing control unit 1, which is an upper block, and then determines whether the speed of the input bit data is 14400 bps or more.

At this time, if the speed of the input bit data is 14400bps or more, the control unit 100 is the interleaver memory 200, the convolutional encoding processing unit 300, the first turbo encoding processing unit 400, the second turbo encoding processing unit And a turbo control signal to the switch 600.

Then, the interleaver memory 200 is set for interleaver memory processing after receiving the turbo control signal from the controller 100, while the switch 600 receives the turbo control signal from the controller 100. At the same time, the interleaver memory 200 and the second turbo encoding processor 500 are connected.

In addition, the first turbo encoding processor 400 and the second turbo encoding processor 500 are shifted to a driving state after receiving the turbo control signal from the controller 100, and the convolutional encoding processor 300 is ready for operation. Transition to state

Thereafter, the ninth, 10, and 11 D flip-flops 401, 402, and 403 mounted in the first turbo encoding processor 400 receive voice, text, and video input bit data from the RF block 2, which is the front block. Are received in order and then shifted by one bit each.

In this case, the seventh XOR gate 406 mounted in the first turbo encoding processor 400 may shift the tenth and eleven D flips at every shift time of the ninth, tenth, and eleven D flip-flops 401, 402, and 403. The output bit data of the flops 402 and 403 are subjected to an Exclusive OR operation and then output to the eighth XOR gate 407, and the eighth XOR gate 407 is the ninth, 10, and 11 D flip-flops. The ninth D after an exclusive OR operation is performed on the bit data output from the RF block 2 which is the front block and the output bit data of the seventh XOR gate 406 at each shift point of the 401, 402, 403. Output to flip-flop 401.

On the other hand, the fifth XOR gate 404 mounted in the first turbo encoding processor 400 may shift the ninth D flip-flop at every shift point of the ninth, 10, and 11 D flip-flops 401, 402, and 403. The input / output bit data of 401 and the output bit data of the eleventh D flip-flop 403 are processed by the exclusive OR operation to output a "Y0" output signal to the IF block 3, and the sixth The XOR gate 405 has input / output bit data of the ninth D flip-flop 401 and the tenth and 11 D flips at every shift point of the ninth, 10, and 11 D flip-flops 401, 402, and 403. The output bit data of the flops 402 and 403 is subjected to an Exclusive OR operation to output the " Y1 " output signal to the IF block 3.

Meanwhile, the twelfth, thirteenth, and fourteenth D flip-flops 501, 502, and 503 mounted in the second turbo encoding processor 500 may interleave the voice, text, and video input bits through the interleaver memory 200. Receive data in order and shift one bit each. The interleaver processing operation of the above-described interleaver memory 200 will be described with reference to FIG. 5. The above-described interleaver processing operation means that the input data I ₁ ,..., I _N are input to the interleaver memory 200. When input in the horizontal direction, the outputs (O ₁ ,..., O _N ) of the interleaver memory 200 are output in the vertical direction. As a result, the interleaver processing operation of the above-described interleaver memory 200 means that the input data direction to the memory and the output data direction are different.

At this time, the eleventh XOR gate 506 mounted in the second turbo encoding processor 500 shifts the thirteenth, fourteenth D flips at every shift point of the twelfth, thirteenth, and fourteenth D flip-flops 501, 502, and 503. The output bit data of the flops 502 and 503 are subjected to an Exclusive OR operation, and then output to the twelfth XOR gate 507, and the twelfth XOR gate 507 is connected to the twelfth, 13, and 14 D flip-flops. The twelfth D flip after performing an exclusive OR operation on the bit data output from the interleaver memory 200 and the output bit data of the eleventh XOR gate 506 at each shift time of (501, 502, 503). Output to flop 507.

On the other hand, the ninth XOR gate 504 mounted in the second turbo encoding processor 500 may shift the twelfth D flip-flop at every shift point of the twelfth, thirteen, and fourteenth D flip-flops 501, 502, and 503. Outputting the Y " 0 &quot; output signal to the IF block 3 by performing an exclusive OR operation on the input / output bit data of 501 and the output bit data of the fourteenth D flip-flop 503, The tenth XOR gate 505 is configured to input / output bit data of the twelfth D flip-flop 501 and the thirteenth and fourteenth shift points of the twelfth, thirteenth, and fourteenth D flip-flops 501, 502, and 503. The output bit data of the D flip-flops 502 and 503 is subjected to an Exclusive OR operation to output a "Y'1" output signal to the IF block 3.

Accordingly, the first turbo encoding processor 400 and the second turbo encoding processor 500 output the "Y0, Y1, Y'0, Y'1" output signals, which are encoding output signals, at the same time. Will print

Hereinafter, a process of convolutional encoding of voice, text, and video input bit data having a speed of less than 14400bps by the encoder of the present invention will be described.

First, the controller 100 receives the speed information of the input bit data from the call processing control unit 1, which is an upper block, and then determines whether the speed of the input bit data is 14400 bps or more.

At this time, when the speed of the input bit data is less than 14400bps, the controller 100 is the interleaver memory 200, the convolutional encoding processing unit 300, the first turbo encoding processing unit 400, the second turbo encoding processing unit And a convolution control signal to the switch 600.

Then, the interleaver memory 200 receives the convolutional control signal from the control unit 100 and is set as a simple buffer memory, while the switch 600 receives the convolutional control signal from the control unit 100. At the same time, the interleaver memory 200 and the convolutional encoding processing unit 300 are connected.

In addition, the convolutional encoding processing unit 300 is shifted to a driving state after receiving the convolutional control signal from the control unit 100, the first turbo encoding processing unit 400 and the second turbo encoding processing unit 500 is the control unit After receiving the convolutional control signal from the 100, the transition to the operation standby state.

Then, the first, second, third, fourth, fifth, sixth, seventh and eighth D flip-flops 301, 302, 303, 304, 305, 306, 307, and 308 mounted in the convolutional encoding processor 300 are After receiving audio, text, and video input bit data in order from the interleaver memory 200, the respective bits are shifted by one bit.

In this case, the first XOR gate 309 mounted in the convolutional encoding processing unit 300 may be the first, second, third, fourth, fifth, sixth, seventh, eighth D flip-flops 301, 302, 303, 304, and 305. , Input / output bit data of the first D flip-flop 301 and the second, third, fourth, sixth, eighth flip-flops 302, 303, 304, 306, The output bit data of 308 is processed by the exclusive OR operation to output the "C0" output signal to the IF block 3.

In addition, the second XOR gate 310 mounted in the convolutional encoding processor 300 may include the first, second, third, fourth, fifth, sixth, seventh, eighth D flip-flops 301, 302, 303, 304, and 305. Input / output bit data of the first D flip-flop 301 and outputs of the third, fourth, fifth, and eight D flip-flops 303, 304, 305, and 308 at each shift point of the first, second, third, fourth, third, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fifth, fourth, fifth, fourth, fifth, third, fourth, fifth, fourth, third, fourth, third, fourth, third, fourth, third, fourth, third, fourth, third, third, fourth, third and third embodiments The bit data is subjected to an exclusive OR operation to output a "C1" output signal to the IF block 3.

In addition, the third XOR gate 311 mounted in the convolutional encoding processing unit 300 includes the first, second, third, fourth, fifth, sixth, seventh and eighth D flip-flops 301, 302, 303, 304, and 305. and the output bit data of 306, 307, 308) wherein the 1 D flip-flop (input bit data, and wherein the 2, 5, 7, 8 D flip-flops (302, 305, 307, 308) 301) for each shift point, of the X or C2 outputs the "C2" output signal to the IF block (3).

In addition, the fourth XOR gate 312 mounted in the convolutional encoding processor 300 may include the first, second, third, fourth, fifth, sixth, seventh and eighth D flip-flops 301, 302, 303, 304, and 305. Input bit data of the first D flip-flop 301 and the third, fourth, five, seven, and eight D flip-flops 303, 304, 305, 307, and 308 at each shift point of the first, second, third, fourth, third, fourth, fourth, fourth, fourth, fifth, fourth, fifth, fourth, fifth, fourth, fifth, fourth, fifth, fourth, fifth, third, fourth, fifth, third, fourth, fourth, fifth, third, fourth, third, fourth, third, fourth, third, fourth, third, third, third, fourth, third, third, third, third, third, third, third, fourth, fourth, third, third, third, third, fourth, third, third, third, third, third, third, fourth, fifth, third, third, fourth, fifth, third, fourth, third, third, third, fourth, third, third, fourth, third, fourth, third, third, fourth, fourth, fifth ,,,, / ,, and third and fourth, as shown in The output bit data of " C3 " is output to the IF block 3 by the exclusive OR operation.

Accordingly, the convolutional encoding processing unit 300 outputs the "C0, C1, C2, C3" output signal, which is an encoding output signal, to the IF block 3 at the same time.

As described above, the encoder combining the convolutional encoding method and the turbo encoding method in the IMT-2000 system according to the present invention can satisfy the convolutional encoding method and the turbo encoding method simultaneously in implementing an encoder suitable for the IMT-2000 system. By implementing the encoder, the master makes it possible to simplify the design and manufacturing process of the encoder, and at the same time has an excellent effect of reducing the production cost.

Claims (5)

A control unit which outputs a turbo control signal when the speed of the input bit data is greater than or equal to the reference value after receiving the speed information of the input bit data from the call processing control unit, which is an upper block, and outputs a convolution control signal when the speed is less than the reference value; Receiving audio, text and video input bit data from the RF block, which is a preceding block, and simultaneously receiving a convolutional control signal from the controller, performing a simple buffering function and outputting it, while receiving a turbo control signal from the controller, the interleaver memory. An interleaver memory for outputting after performing a function; When receiving the convolutional control signal from the controller and receiving audio, text and video input bit data from the interleaver memory, the 4-bit output signal of "C0, C1, C2, C3" is processed by convolutional encoding of the input bit data. A convolutional encoding processor for outputting the IF block; After receiving the turbo control signal from the controller and receiving the audio, text and video input bit data from the RF block, which is a preceding block, turbo encoding the input bit data to output a 2-bit output signal of "Y0, Y1" to the IF. A first turbo encoding processor outputting the block; After receiving the turbo control signal from the control unit and receiving the interleaver-processed voice, text and video input bit data through the interleaver memory, turbo encoding the input bit memory to process "Y'0, Y'1". A second turbo encoding processor configured to output a 2-bit output signal to the IF block; And Connected to the signal output terminal of the interleaver memory and the signal input terminals of the convolutional encoding processing unit and the second turbo encoding processing unit, and upon receiving the convolutional control signal from the control unit, connects the interleaver memory and the convolutional encoding processing unit, And a convolutional encoding method and a turbo encoding method in an IMT-2000 system, comprising: a switch connecting the memory for the interleaver and a second turbo encoding processing unit when a turbo control signal is received. The method of claim 1, And a reference speed at which the control unit determines the speed of the input bit data is “14400 bps”. An encoder combining a convolutional encoding method and a turbo encoding method in an IMT-2000 system. The convolutional encoding processing unit is connected in series to a signal output terminal of the interleaver memory, and receives first audio, text and video input bit data in order, and then shifts each bit by one bit. , 6, 7, 8 D flip-flops; Input / output bit data of the first D flip-flop and the second, 3, 4, 6, and 8 D flips every shift point of the first, second, third, fourth, fifth, six, seven, and eight D flip-flops. A first XOR gate for outputting a " C0 " output signal by performing an exclusive OR operation on the output bit data of the flop; The input / output bit data of the first D flip-flop and the third, 4, 5, and 8 D flip-flops at each shift point of the first, second, third, fourth, fifth, six, seven, and eight D flip-flops. A second XOR gate that outputs a " C1 " output signal by processing the output bit data to an exclusive OR operation; Input bit data of the first D flip-flop and output bits of the second, 5, 7, 8 D flip-flop at each shift point of the first, second, third, fourth, fifth, six, seven, eight D flip-flop A third XOR gate for outputting a " C2 " output signal by processing the exclusive OR operation of the data; And The input bit data of the first D flip-flop and the third, 4, 5, 7, 8 D flip-flop at each shift point of the first, second, third, fourth, fifth, six, seven, eight D flip-flop. An encoder combining a convolutional encoding method and a turbo encoding method in an IMT-2000 system, characterized by comprising a fourth XOR OR gate which outputs a " C3 " output signal by processing the exclusive bit operation of the output bit data. The method of claim 1, The first turbo encoding processor is connected to a signal output terminal of an RF block, which is a front-end block, in series, respectively, to receive voice, text, and video input bit data in order, and to shift each bit by one bit. Flip-flops; "Y0" output signal by performing an exclusive OR operation on the input / output bit data of the ninth D flip-flop and the output bit data of the eleventh D flip-flop at each shift time of the ninth, 10, and 11 D flip-flops. A fifth XOR gate outputting the same; "Y1" by performing an exclusive OR operation on the input / output bit data of the ninth D flip-flop and the output bit data of the tenth and 11 D flip-flops at each shift time of the ninth, 10, and 11 D flip-flops. A sixth XOR gate configured to output an output signal; A seventh XOR gate configured to output the output bit data of the tenth and eleventh D flip-flops after an exclusive or arithmetic operation at every shift point of the ninth, ten, and eleven D flip-flops; And Exclusive OR operation processing bit data output from an RF block that is a front block and output bit data of the seventh XOR gate connected to the seventh XOR gate at each shift time of the ninth, 10, and 11D flip-flops. And a convolutional encoding method and a turbo encoding method in the IMT-2000 system, wherein the eighth XOR gate is output to the ninth D flip-flop. The method of claim 1, The second turbo encoding processor is connected to the signal output terminal of the memory for the interleaver in series, and receives the audio, text, and video input bit data in order, and then shifts each of the twelfth, 13, and 14 D flips by one bit. Flop; &Quot; Y'0 " by performing an exclusive OR operation on the input / output bit data of the twelfth D flip-flop and the output bit data of the fourteenth D flip-flop at every shift point of the twelfth, 13, and 14 D flip-flops. A ninth XOR gate configured to output an output signal; The Y / Y operation is performed by processing an exclusive or operation on the input / output bit data of the twelfth D flip-flop and the output bit data of the thirteenth and 14D flip-flops at every shift point of the twelfth, thirteenth, and fourteenth flip-flops. A tenth XOR gate for outputting a 1 ″ output signal; An eleventh XOR gate configured to output the output bit data of the thirteenth and fourteenth D flip-flops after an exclusive or arithmetic operation at every shift point of the twelfth, thirteenth and fourteenth flip-flops; And Exclusive or operation processing of bit data output from the interleaver memory and output bit data of the eleventh XOR gate connected to the eleventh XOR gate at each shift point of the twelfth, 13, and 14D flip-flops. And a twelfth XOR gate output to the twelfth D flip-flop, wherein the convolutional encoding method and the turbo encoding method are mixed in the IMT-2000 system.