KR20000003419A - Weaving coding equipment used for digital communication system - Google Patents

Abstract

PURPOSE: A weaving coding equipment is provided to apply the weaving coding used for correcting the error generated from a digital communication system by a byte unit. CONSTITUTION: The weaving coding equipment comprises: a bite storing device(210) for storing a certain bite that is decided by an input data; and coding devices(221-228) outputting the input data to be coded by the bite data using the certain bite that is stored in the bite storing device.

Description

Convolutional Coding Apparatus Used in Digital Communication Systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convolutional encoding device used in a digital communication system, and more particularly, to a convolutional encoding device for performing convolutional coding used for correcting an error generated in a digital communication system in units of bytes.

Encoding used in digital communication systems includes source encoding for reducing the amount of data of a given information and channel encoding for error correction. Convolutional coding belongs to channel coding and has excellent error correction capability, while being weak to aggregation errors. Normally, repeaters and interleavers are used to provide time diversity to secure these shortcomings.

1 is a block diagram illustrating a convolutional coding apparatus used in a conventional digital communication system, and includes a parallel-to-serial converter 110, a plurality of D-flip flops (121 to 127), and a plurality of exclusive logical gates (131). To 138), and serial / parallel converters 140 and 150.

The operation of the convolutional coding apparatus used in the conventional digital communication system having the structure as described above is as follows.

When the source encoder 160 outputs parallel data obtained by encoding and compressing data input from the outside to the parallel / serial converter 110, the parallel / serial converter 110 serializes the parallel data transferred from the source encoder 160. The data is converted into data and output to the D-flip flop 121.

The D-flip-flop 121 delays the serial data transmitted from the parallel / serial converter 110 according to a clock input from the outside, and then the D-flip-flop 122 and the exclusive logic gates 131 and 132. And the D-flip-flop 122 delays the bit transmitted from the D-flip-flop 121 according to a clock input from the outside, and then the D-flip-flop 123 and the exclusive logic gate 131. )

The exclusive logic gate 131 performs an exclusive logic on the bits transferred from the D-flip flips 12 and 122 and outputs the exclusive logic gate 133 to the exclusive logic gate 133.

The D-flip-flop 123 delays the bit transmitted from the D-flip-flop 122 according to a clock input from the outside, and then to the exclusive logic gates 132 and 133 and the D-flip-flop 124. Output

The exclusive logic gate 132 exclusively sums the bits transmitted from the D-flip flops 121 and 123 and outputs the exclusive logic gate 134 to the exclusive logic gate 134, and the exclusive logic gate 133 is a D-flip flop 123. An exclusive logic sum of the bit transferred from the output signal of the exclusive logic gate 131 and the output signal is output to the exclusive logic gate 135.

The D-flip-flop 124 delays the bit transmitted from the D-flip-flop 124 and then outputs to the exclusive logic gates 134 and 135 and the D-flip-flop 125.

The exclusive validity gate 134 exclusively combines the bit transmitted from the D-flip flop 124 with the output signal of the exclusive logic gate 132 and outputs the exclusive logic gate 136 to the exclusive logic gate 136. The bit transferred from the D-flip flop 124 and the output signal of the exclusive logic gate 133 are exclusively logically outputted to the exclusive logic gate 137.

The D-flip flops 125 and 126 sequentially delay bits transmitted from the D-flip flop 124 according to a clock input from the outside, and then the D-flip flop 127 and the exclusive logic gate 136. The D-flip-flop 127 also delays the bit transmitted from the D-flip-flop 126 to the exclusive logical gates 137 and 138.

The exclusive logic gate 136 exclusively combines the bit transmitted from the D-flip flop 126 and the output signal of the exclusive logic gate 134 and outputs the exclusive logic gate 138 to the exclusive logic gate 138. Subsequently, the exclusive logic gate 137 exclusively combines the bit transmitted from the D-flip flop 127 and the output signal of the exclusive logic gate 135 and outputs the signal to the serial / parallel converter 140. 138 exclusively combines the bit transmitted from the D-flip-flop 127 with the output signal of the exclusive logic gate 136 and outputs the signal to the serial / parallel converter 150.

When such a convolution process is performed and then convolution values are transferred to the serial / parallel converters 140 and 150, the serial / parallel converter 140 converts the serial output signal of the exclusive logic gate 137 into a parallel signal. The output signal is converted to the Q channel interleaver 170 and the serial / parallel converter 150 converts the serial output signal of the exclusive logic gate 138 into a parallel signal and outputs the parallel signal to the I channel interleaver 180.

The convolutional coding process as described above is represented by polynomials such as the following [Equation 1] and [Equation 2].

g ₁ (x) = 1 + x ² + x ³ + x ⁵ + x ⁶

g ₂ (x) = 1 + x + x ² + x ³ + x ⁶

Where g ₁ (x) and g ₂ (x) are the generator polynomials representing the convolutional encoding process, 1 is an input bit, x is a bit delayed for one clock, x ² is a bit delayed for two clocks, and x ³ is a bit delayed for 3 clocks, x ⁵ is a bit delayed for 5 clocks, and x ⁶ is a bit delayed for 6 clocks.

On the other hand, the conventional convolutional encoding apparatus convolutionally encodes the bits output from the source encoder 160 in order from the upper bits to the lower bits.

However, the conventional convolutional coding apparatus as described above serially converts data input in units of bytes from the outside by the parallel / serial converter 110, and then converts the serial data into a plurality of D-flip flops and an exclusive logic gate. After the encoding is performed bit by bit, the encoded data is converted in parallel through the serial / parallel converters 140 and 150 and output in byte units, which is inefficient when input / output with peripheral function devices operating in byte units. There was an issue that was.

Accordingly, the present invention has been made to solve the above problems, and in performing convolutional encoding used to correct an error occurring in a digital communication system, encoding the data input in the unit of byte from the outside in byte unit It is an object of the present invention to provide a convolutional encoding apparatus used in a digital communication system capable of improving a coding speed by performing the same.

1 is a block diagram of a convolutional coding apparatus used in a conventional digital communication system.

2 is a block diagram illustrating a convolutional coding apparatus used in a digital communication system according to an embodiment of the present invention.

3 is a circuit diagram of an embodiment of an encoder of FIG. 2.

Explanation of symbols on the main parts of the drawings

210: byte storage unit 221 to 228: encoding unit

230: I channel interleaver 240: Q channel interleaver

In order to achieve the above object, the present invention provides a convolutional coding apparatus in a digital communication system for convolutional coding of input data, comprising: byte storage means for storing a predetermined byte determined according to the input data; And encoding means for encoding and outputting the input data in byte units by using a predetermined byte stored in the byte storing means.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 and 3.

2 is a block diagram illustrating a convolutional coding apparatus used in a digital communication system according to an embodiment of the present invention.

Referring to FIG. 2, the convolutional coding apparatus used in the digital communication system of the present invention uses a byte storage unit 210 for storing a predetermined byte and a small byte stored in the byte storage unit 210 to store an external signal. And a plurality of encoders 221 to 228 for convolutionally encoding the input data input in the unit of bytes.

The byte storage unit 210 stores the immediately preceding byte of the byte input from the outside. If the byte input from the outside is 8 bits, the 6-bit byte is stored in the byte storage unit 210. That is, as shown in the figure, when an 8-bit byte having b _{i, 0} to b _{i, 7} bits is input from the outside, the byte storage unit 210 enters b _{(i-1), 0} to b _{(i -1),} 6-bit byte having ₅ bits is stored. However, i is a natural number of two or more, which is the sequence number of bytes input from the outside. And b _{i, 0} and b _{(i-1), 0} are the most significant bits, and b _{i, 7} and b _{(i-1), 5} are the least significant bits.

In addition, the plurality of encoders 221 to 228 are arranged in parallel to simultaneously perform an encoding operation.

The operation of the convolutional coding apparatus used in the digital communication system of the present invention having the above structure will be described in detail as follows.

The encoding unit 221 convolutionally encodes b _{i, 0} input from the outside using b _{i, 1} to b _{i, 6} except b _{i, 4} , and encodes the convolutional coded values i _{i, 0} , q _{i, 0} ) Are output to the RAMs of the I-channel interleaver 230 and the Q-channel interleaver 240, respectively. Encoder 222 convolutionally encodes b _{i, 1} input from the outside using b _{i, 2} to b _{i, 7} except b _{i, 5} , and convolutional coded values i _{i, 1} , q _{i, 1} ) Are output to the RAMs of the I-channel interleaver 230 and the Q-channel interleaver 240, respectively. The encoder 223 uses b _{i, 3} to b _{i, 7} except b _{i, 6} and b _{(i-1), 0} stored in the storage 210 to store b _{i, 2} input from the outside. The convolutional encoding is performed to output convolutional encoded values i _{i, 2} , q _{i, 2} to the RAMs of the I channel interleaver 230 and the Q channel interleaver 240, respectively. The encoder 224 uses b _{i, 4} through b _{i, 6} and b _{(i-1), 0} and b _{(i-1), 1} stored in the storage 210 to input b _i from the outside. _, the convolutional encoder _3, and outputs to the RAM of the convolutional encoder values (i _{i, 3,} q _{i, 3),} the I-channel interleaver 230 and the Q-channel interleaver 240, respectively. The encoder 225 uses b _{i, 5} to b _{i, 7} and b _{(i-1), 1} and b _{(i-1), 2} stored in the storage 210 to input b _i from the outside. _The convolutional encoding of _{, 4} is performed, and convolutional encoding values i _{i, 4} , q _{i, 4} are output to the RAM of the I channel interleaver 230 and the Q channel interleaver 240, respectively. The encoding unit 226 stores b _{i, 6} and b _{i, 7} and b _{(i-1), 0} , b _{(i-1), 2} and b _{(i-1), 3} stored in the storage unit 210. By convolutional coding b _{i, 5} input from the outside, the convolutional coded values i _{i, 5} , q _{i, 5} are output to RAM of the I channel interleaver 230 and the Q channel interleaver 240, respectively. . Encoder 227 is b _{i, 7} input from the outside and b _{(i-1), 0} , b _{(i-1), 1} , b _{(i-1), 3} and b stored in the storage 210 _By convolutionally encoding b _{i, 6} input from the outside using _{(i-1), 4} , the convolutional coded values i _{i, 6} , q _{i, 6} are concatenated into the I channel interleaver 230 and the Q channel interleaver, respectively. Output to the RAM of 240. Encoder 228 is b _{(i-1), 0} , b _{(i-1), 1} , b _{(i-1), 2} , b _{(i-1), 4} and b stored in storage 210 _By convolutionally encoding b _{i, 7} input from the outside using _{(i-1), 5} , the convolutional coded values i _{i, 7} , q _{i, 7} are respectively encoded by the I channel interleaver 230 and the Q channel interleaver. Output to the RAM of 240.

This convolutional encoding process is performed simultaneously in parallel.

3 is a circuit diagram of an encoder of FIG. 2 according to an embodiment.

As shown in FIG. 3, the encoder of FIG. 2 includes first and second exclusive logic gates 311 and 312 and exclusive first and second exclusive logic gates for exclusive logical sum of bits input to two input terminals. A third exclusive logic gate 313 for exclusive logical sum of the output signals of 311 and 312, and a fourth exclusive logic gate for exclusive logical sum of the output signal of the bit and the third exclusive logic gate 313 inputted from the outside ( 314 and a fifth exclusive logic gate 315 for exclusive logical sum of an externally input bit and an output signal of the third exclusive logic gate 314. Here, the output signals of the fourth and fifth exclusive logic gates 314 and 315 are transmitted to the I-channel and Q-channel interleavers 230 and 240, respectively.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can reduce the occupied area by encoding data input in the unit of bytes from the outside in units of bytes without using the existing serial / parallel converter and the parallel / serial converter. By simplifying the process, the speed of operation can be significantly improved.

Claims (5)

A convolutional coding apparatus in a digital communication system for convolutional coding of input data, Byte storing means for storing a predetermined byte determined according to the input data; And Encoding means for encoding the input data in units of bytes by using a predetermined byte stored in the byte storage means Convolutional encoding device used in a digital communication system comprising a. The method of claim 1, The encoding means, First and second encoders for encoding upper bits of the input data using lower bits of the input data; And Third to eighth encoders for encoding a specific bit of the input data using the specific bits stored in the byte storage unit. Convolutional encoding apparatus used in the digital communication system comprising a. The method of claim 2, The first to eighth encoders, And a convolutional encoding device arranged in parallel with the number of bits of the input data, and simultaneously encoding the bits of the input data input in parallel and outputting the data in byte units. The method of claim 3, wherein Each of the encoding units of the encoding means, The convolutional encoding device used for the digital communication system, characterized in that it can be expanded or reduced in accordance with the number of bits of the input data. The method of claim 4, wherein Each of the first to eighth encoders may include: First exclusive logical calculation means for exclusive logical sum of the first and second bits input to the two input terminals; Second exclusive logic calculating means for exclusive logical sum of the third and fourth bits inputted to the two input terminals; Third exclusive logical calculation means for exclusive logical sum of the output signals of said first and second exclusive logical calculation means; Fourth exclusive logic calculating means for exclusive logical sum of the fifth bit input from the outside and the output signal of the third exclusive logic calculating means; And Fifth exclusive logic calculation means for exclusive logical sum of the sixth bit inputted from the outside and the output signal of the third exclusive logic calculation means; Convolutional encoding device used in a digital communication system comprising a.