KR20020021260A - Clock stabilizing circuit - Google Patents

Abstract

PURPOSE: A circuit for stabilizing a clock is provided to improve the stability of the maintenance and the operation of a system by blocking a noise included in a transmission interval and outputting only clock with a normal period. CONSTITUTION: A clock receiving unit(10) receives a clock signal outputted from an external clock generating device. A clock monitoring unit(20) monitors whether the receiving clock received through the clock receiving unit(10) is continuously inputted. A reference clock generating unit(30) generates a clock with a uniform frequency. A clock counter(40) counts the clock outputted from the reference clock generating unit(30) to be suitable for the period of the receiving clock and outputs an enable pulse. A clock counter control unit(50) receives an output signal of the clock monitoring unit(20) and an output signal of the clock receiving unit(10), and controls an operation of the clock counter(40). A clock output control unit(60) logically combines the enable pulse and the receiving clock outputted from the clock counter(40).

Description

Clock Stabilization Circuit {CLOCK STABILIZING CIRCUIT}

The present invention relates to clock stabilization using a clock monitor. In particular, in a circuit that receives a clock from a redundant clock source, it is possible to increase the stability of a clock by blocking noise that may be included in a transmission section until the clock is input. It relates to a clock stabilization circuit that is suitable.

In general, digital circuits always process all data based on a clock. The clock is generated by its own circuit, and when there are many parts that use the clock in the system, a separate clock generator is provided. In some cases, a clock generated by the clock generator may be used.

However, when the clock is received and used by an external clock generator, care must be taken not to misinterpret the noise inserted through the transfer or transmission path of the clock source as the clock.

1 is a block diagram of a conventional clock receiving circuit, which is configured to receive a clock input from a clock source through a clock receiving unit 1 and use it directly in a board circuit after only level conversion without a separate filtering device.

Here, the clock monitoring unit 2 monitors whether the clock is continuously input without interruption, and reports the clock input when the clock input is interrupted.

Therefore, when the noise A is included in the clock pulse a input to the clock receiver 1 as shown in Fig. 2, the output pulse b also contains noise A.

Of course, the clock monitoring unit 2 only detects whether the clock input is stopped but cannot detect whether the clock contains noise. Therefore, the clock monitoring unit 2 continuously outputs only the normal signal of the 'high' level as shown in (c).

That is, in the conventional technology as described above, the clock monitoring unit that monitors the reception clock does not detect an abnormal clock state for a short time, thereby causing a malfunction by causing a clock containing noise to be input to the board as it is. Since the supervisory circuit and the receiver circuit operate separately, there is a problem that the malfunction of the board cannot be prevented because an abnormal clock cannot be supplied to the board.

Therefore, the present invention was created to solve the above-mentioned conventional problems, and cuts out noise that may be included in a transmission period until receiving a clock output from an external clock generator, and outputs only a clock of a normal period. It is an object of the present invention to provide a clock stabilization circuit that can improve the stability of the maintenance and operation of the system.

1 is a block diagram of a conventional clock receiving circuit.

2 is an exemplary view showing a waveform of a signal output from each component of FIG.

3 is a block diagram showing the configuration of a clock stabilization circuit according to the present invention;

4 is an exemplary view showing a waveform of a signal output from each component of FIG.

*** Description of the symbols for the main parts of the drawings ***

10: clock receiving unit 20: clock monitoring unit

30: reference clock generator 40: clock counter

50: clock counter control unit 60: clock output control unit

The present invention for achieving the above object, the clock receiving unit for receiving a clock signal output from an external clock generator; A clock monitor configured to monitor whether a received clock input through the clock receiver is input without interruption; A reference clock generator which generates a clock of a predetermined frequency by itself; A clock counter for counting a clock output from the reference clock generator in accordance with a period of the received clock and outputting an enable pulse; A clock counter controller which receives an output signal of the clock monitor and an output signal of the clock receiver to control an operation of a clock counter; And a clock output controller configured to logically combine the enable pulse and the received clock output from the clock counter.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

First, Figure 3 is a block diagram showing the configuration of a clock stabilization circuit according to the present invention, as shown in the clock receiving unit 10 for receiving a clock signal output from an external clock generator; A clock monitoring unit 20 for monitoring whether the received clock inputted through the clock receiving unit 10 is input without interruption; A reference clock generator 30 which generates a clock of a predetermined frequency by itself; A clock counter 40 for counting a clock output from the reference clock generator 30 so as to correspond to a period of the received clock and outputting an enable pulse; A clock counter controller (50) for controlling the operation of the clock counter (40) by receiving the output signal of the clock monitor (20) and the output signal of the clock receiver (10); And a clock output control unit 60 for logically combining the enable pulse output from the clock counter 40 and the reception clock.

Hereinafter, the operation and operation of the present invention configured as described above with reference to the waveform diagram of FIG.

First, as shown in (a), the clock receiver 10 performs only a level conversion and outputs the input clock as shown in (a).

Therefore, the noise component B included therein is also output as it is shown in (b).

In addition, the clock monitoring unit 20 also outputs a normal signal of the 'high' level as shown in (c) while the clock is continuously inputted at a predetermined period without stopping.

Next, the reference clock generator 30 generates a reference clock to be used in the clock stabilization circuit itself. As shown in (d), the reference clock generator 30 generates a clock having a frequency higher than that of the reception clock received from the outside.

Accordingly, the clock counter 40 counts the clock output from the reference clock generator 30 in accordance with the period of the reception clock to generate an enable pulse at a predetermined period as shown in (e).

In this case, the period in which the enable pulse is generated is synchronized with the reception clock by the clock counter controller 50.

That is, when the normal signal is input from the clock monitoring unit 20, the synchronization is detected from the received clock, and the clock counter 40 is controlled to start counting according to the synchronization.

Of course, when the abnormal signal is input from the clock monitoring unit 20 by controlling the clock counter 40 not to operate, the output of the clock is blocked to prevent the board malfunction due to the wrong reception clock.

Next, the clock output controller 60 receives the enable pulse output from the clock counter 40 and the received clock output through the clock receiver 10 and ends the two signals to input the signals as shown in (f). Control to output only the received clock input during the enable pulse period.

Accordingly, as illustrated in FIG. 4B, the noise component B included between the clocks output from the clock receiver 10 is not output, and only a pure clock of a normal period is output.

As described above, the clock stabilization circuit of the present invention blocks the noise that may be included in the transmission period until the clock output from the external clock generator is input, and outputs only the clock of the normal period to maintain and operate the system. There is an effect of improving the stability of.

Claims (1)

A clock receiver which receives a clock signal output from an external clock generator; A clock monitor configured to monitor whether a received clock input through the clock receiver is input without interruption; A reference clock generator which generates a clock of a predetermined frequency by itself; A clock counter for counting a clock output from the reference clock generator in accordance with a period of the received clock to output an enable pulse; A clock counter controller which receives an output signal of the clock monitor and an output signal of the clock receiver to control an operation of a clock counter; And a clock output controller configured to logically combine the enable pulse and the received clock output from the clock counter.